DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference signs mentioned in the description: “T9”, “T10”, “R8”, “R9”, “R10”, and “R11” (Paragraph 46). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-5 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the minimally-sized" in line 21. There is insufficient antecedent basis for this limitation in the claim. Amending the limitation to “the minimally-sized rectangle” is sufficient to overcome this rejection, which is how the limitation will be treated for examination purposes. Examiner notes that line 16 of claims 4 and 5 also recites the same limitation, and should be amended accordingly. Claims 2-5 are likewise rejected under this logic by virtue of their dependency on claim 1.
Claim 1 recites the limitation “an opposite of the balun” in line 26. This limitation is indefinite because it is unclear what feature of the balun is being referred to. Amending the limitation to “an opposite side of the balun” is sufficient to overcome this rejection, which is how the limitation will be treated for examination purposes. Claims 2-5 are likewise rejected under this logic by virtue of their dependency on claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over Hase (Patent Publication Number US 2021/0083633 A1), hereafter referred to as Hase, in view of Honda et al. (Patent Publication Number US 2021/0203289 A1), hereafter referred to as Honda, and Sasaki (Patent Publication Number US 2022/0093775 A1), as cited by applicant, hereafter referred to as Sasaki.
Regarding claim 1, Hase discloses:
A high-frequency amplifier circuit (Hase, Fig. 25) comprising: a substrate (Paragraph 7); a drive stage amplifier circuit on the substrate (Fig. 25, 160) and comprising a plurality of drive stage transistors (Fig. 25, Q1); a balun on the substrate (Fig. 25, 151) and configured to convert a high-frequency signal output from the drive stage amplifier circuit into a differential signal (Fig. 25, consider that balun 151 has a differential output); a power stage differential amplifier circuit on the substrate (Fig. 25, 180), comprising a plurality of power stage transistors (Fig. 25, Q5 and Q6), and configured to amplify the differential signal converted by the balun (Fig. 25, see connection between 180 and 151); but fails to disclose and a drive stage power supply terminal configured to supply power to the plurality of drive stage transistors via the balun, wherein when the substrate is viewed in plan view, long sides of a minimally-sized rectangle that encompasses the plurality of power stage transistors extend along a first direction and short sides of the minimally-sized rectangle extend along a second direction, wherein the balun is outside of the minimally-sized with respect to the second direction, and between the short sides of the minimally-sized rectangle with respect to the first direction, and wherein the drive stage power supply terminal is on the substrate at an opposite of the balun than the plurality of drive stage transistors in the second direction.
However, Honda teaches and a drive stage power supply terminal (Honda, Fig. 2, VCC2) configured to supply power to the plurality of drive stage transistors via the balun (Fig. 2, see connection between VCC2 and drive stage amplifier 7 via balun 5), but fails to teach wherein when the substrate is viewed in plan view, long sides of a minimally-sized rectangle that encompasses the plurality of power stage transistors extend along a first direction and short sides of the minimally-sized rectangle extend along a second direction, wherein the balun is outside of the minimally-sized with respect to the second direction, and between the short sides of the minimally-sized rectangle with respect to the first direction, and wherein the drive stage power supply terminal is on the substrate at an opposite of the balun than the plurality of drive stage transistors in the second direction.
However, Sasaki teaches wherein when the substrate is viewed in plan view, long sides of a minimally-sized rectangle that encompasses the plurality of power stage transistors extend along a first direction (Sasaki, Fig. 16, consider x-axis as first direction, and consider rectangle formed by transistors of power amplifier 72) and short sides of the minimally-sized rectangle extend along a second direction (Fig. 16, consider y-axis as second direction, and consider rectangle formed by transistors of power amplifier 72), wherein the balun is outside of the minimally-sized with respect to the second direction (Fig. 16, consider location of interstage matching circuit 74 with respect to transistors of power amplifier 72 in the y-direction), and between the short sides of the minimally-sized rectangle with respect to the first direction (Fig. 16, consider location of interstage matching circuit 74 with respect to transistors of power amplifier 72 in the x-direction), and wherein the drive stage power supply terminal is on the substrate at an opposite of the balun than the plurality of drive stage transistors in the second direction (Fig. 16, consider that Vcc2 is on opposite side of interstage matching circuit 74 than drive stage amplifier 71).
Hase, Honda, and Sasaki are all considered to be analogous to the claimed invention because they are in the same field of improving power amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Hase to incorporate the teachings of Honda and Sasaki to include the drive stage power supply terminal of Honda in the circuit of Hase, which would have the effect of providing an well-known alternative driving scheme for the driver amplifier of Hase (Honda, Paragraph 36, lines 1-15), and the semiconductor layout of Sasaki to implement the circuit of Hase, which would have the effect of reducing excess heat in the circuit of Hase (Sasaki, Paragraph 118, lines 1-11).
Regarding claim 2, Hase and Honda fail to disclose:
wherein the plurality of power stage transistors are side by side on the substrate in the first direction.
However, Sasaki further teaches wherein the plurality of power stage transistors are side by side on the substrate in the first direction (Sasaki, Fig. 16, consider side by side layout of the plurality of transistors of power stage amplifier 72).
Hase, Honda, and Sasaki are all considered to be analogous to the claimed invention because they are in the same field of improving power amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Hase to incorporate the teachings of Sasaki to include the semiconductor layout of Sasaki to implement the circuit of Hase, which would have the effect of reducing excess heat in the circuit of Hase (Sasaki, Paragraph 118, lines 1-11).
Regarding claim 3, Hase and Honda fail to disclose:
wherein the plurality of drive stage transistors are side by side on the substrate in the second direction.
However, Sasaki further teaches wherein the plurality of drive stage transistors are side by side on the substrate in the second direction (Sasaki, Fig. 16, consider side by side layout of the plurality of transistors of drive stage amplifier 71, and 90° rotation between the connection between drive stage bias circuit 76 and drive stage amplifier 71 and the connection between power stage bias circuit 77 and power stage amplifier 72).
Hase, Honda, and Sasaki are all considered to be analogous to the claimed invention because they are in the same field of improving power amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Hase to incorporate the teachings of Sasaki to include the semiconductor layout of Sasaki to implement the circuit of Hase, which would have the effect of reducing excess heat in the circuit of Hase (Sasaki, Paragraph 118, lines 1-11).
Claims 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Hase in view of Honda and Sasaki as applied to claims 1 and 2, respectively, above, and further in view of Hirotaka et al. (Patent Number JP 3,766,239 B2), hereafter referred to as Hirotaka.
Regarding claim 4, Hase further discloses:
further comprising: a signal input terminal (Hase, Fig. 25, PAin) to which a signal is input to the drive stage amplifier circuit (Fig. 25, see connection between PAin and 160); a drive stage bias circuit (Fig. 25, BB1) configured to supply a bias to the plurality of drive stage transistors (Fig. 25, see connection between BB1 and Q1); a power stage bias circuit (Fig. 25, BB2) configured to supply a bias to the plurality of power stage transistors (Fig. 25, see connection between BB2 and Q5 and Q6); but fails to disclose and a bias power supply terminal configured to supply power to the drive stage bias circuit and to the power stage bias circuit, wherein when viewed from the balun, the signal input terminal is farther than the drive stage amplifier circuit in the first direction, and wherein the bias power supply terminal is outside of the minimally-sized with respect to the second direction, and between the short sides of the minimally-sized rectangle with respect to the first direction.
However, Sasaki further teaches and a bias power supply terminal (Sasaki, Fig. 16, Vbatt) configured to supply power to the drive stage bias circuit (Fig. 16, see connection between Vbatt and drive stage bias circuit 76) and to the power stage bias circuit (Fig. 16, see connection between Vbatt and power stage bias circuit 77), wherein when viewed from the balun, the signal input terminal is farther than the drive stage amplifier circuit in the first direction (Fig. 16, see that distance in x-direction between interstage matching circuit 74 and RFin is larger than distance in x-direction between interstage matching circuit 74 and drive stage amplifier 71), and wherein the bias power supply terminal is outside of the minimally-sized with respect to the second direction (Fig. 16, see that Vbatt is not between sides of power amplifier 72 in y-direction), but fails to teach and [the bias power supply terminal] between the short sides of the minimally-sized rectangle with respect to the first direction.
However, Hirotaka teaches and [the bias power supply terminal] between the short sides of the minimally-sized rectangle with respect to the first direction (Hirotaka, Fig. 3, see that bias power supply terminal bias SW is between short sides of rectangle forming 1st and 2nd FETs).
Hase, Honda, Sasaki, and Hirotaka are all considered to be analogous to the claimed invention because they are in the same field of improving power amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Hase to incorporate the teachings of Sasaki and Hirotaka to include the semiconductor layout of Sasaki to implement the circuit of Hase, which would have the effect of reducing excess heat in the circuit of Hase (Sasaki, Paragraph 118, lines 1-11), and to include the bias power supply terminal location of Hirotaka in the circuit of Hase, which would have the effect of reducing the physical area of the circuit of Hase.
Regarding claim 5, Hase further discloses:
further comprising: a signal input terminal (Hase, Fig. 25, PAin) to which a signal is input to the drive stage amplifier circuit (Fig. 25, see connection between PAin and 160); a drive stage bias circuit (Fig. 25, BB1) configured to supply a bias to the plurality of drive stage transistors (Fig. 25, see connection between BB1 and Q1); a power stage bias circuit (Fig. 25, BB2) configured to supply a bias to the plurality of power stage transistors (Fig. 25, see connection between BB2 and Q5 and Q6); but fails to disclose and a bias power supply terminal configured to supply power to the drive stage bias circuit and to the power stage bias circuit, wherein when viewed from the balun, the signal input terminal is farther than the drive stage amplifier circuit in the first direction, and wherein the bias power supply terminal is outside of the minimally-sized with respect to the second direction, and between the short sides of the minimally-sized rectangle with respect to the first direction.
However, Sasaki further teaches and a bias power supply terminal (Sasaki, Fig. 16, Vbatt) configured to supply power to the drive stage bias circuit (Fig. 16, see connection between Vbatt and drive stage bias circuit 76) and to the power stage bias circuit (Fig. 16, see connection between Vbatt and power stage bias circuit 77), wherein when viewed from the balun, the signal input terminal is farther than the drive stage amplifier circuit in the first direction (Fig. 16, see that distance in x-direction between interstage matching circuit 74 and RFin is larger than distance in x-direction between interstage matching circuit 74 and drive stage amplifier 71), and wherein the bias power supply terminal is outside of the minimally-sized with respect to the second direction (Fig. 16, see that Vbatt is not between sides of power amplifier 72 in y-direction), but fails to teach and [the bias power supply terminal] between the short sides of the minimally-sized rectangle with respect to the first direction.
However, Hirotaka teaches and [the bias power supply terminal] between the short sides of the minimally-sized rectangle with respect to the first direction (Hirotaka, Fig. 3, see that bias power supply terminal bias SW is between short sides of rectangle forming 1st and 2nd FETs).
Hase, Honda, Sasaki, and Hirotaka are all considered to be analogous to the claimed invention because they are in the same field of improving power amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Hase to incorporate the teachings of Sasaki and Hirotaka to include the semiconductor layout of Sasaki to implement the circuit of Hase, which would have the effect of reducing excess heat in the circuit of Hase (Sasaki, Paragraph 118, lines 1-11), and to include the bias power supply terminal location of Hirotaka in the circuit of Hase, which would have the effect of reducing the physical area of the circuit of Hase.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lehtola (Patent Publication Number US 2023/0097146 A1) discloses (Fig. 2) a radio frequency power amplifier circuit.
Sawada et al. (Patent Publication Number US 2021/0288679 A1) discloses (Fig. 2) a radio frequency power amplifier circuit.
Tsutsui et al. (Patent Publication Number US 2021/0135657 A1) discloses (Fig. 1) a radio frequency power amplifier circuit.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lance T Bartol whose telephone number is (703)756-1267. The examiner can normally be reached Monday - Thursday 6:30 a.m. - 4:00 p.m. CT, Alternating Fridays 6:30 - 3:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached at 571-272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LANCE TORBJORN BARTOL/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843
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