DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 3/27/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 6, 12-13 and 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by (US Patent No. 11,239,232).
[Re claim 1] Lilak discloses the semiconductor structure, wherein the semiconductor structure comprises: a set of stacked transistors, wherein the set of stacked transistors comprises: a first transistor (130), wherein the first transistor comprises a first gate having a gate-all-around (GAA) structure; a second transistor (110), wherein the second transistor has a gate structure different than a GAA structure; and a dielectric bar (151) (see figure 1 and column 5 line 47-58 and column 7 line 32 through column 8 line 67).
[Re claim 2] Lilak discloses the semiconductor structure, wherein the second transistor (110) comprises a second gate having a tri-gate structure (see figure 1 and column 5 line 47-58 and column 8 lines 42-53).
[Re claim 3] Lilak discloses the semiconductor structure wherein the first transistor (130) is in a top region of the set of stacked transistors and the second transistor (110) is in a bottom region of the set of stacked transistors (see figure 1).
[Re claim 4] Lilak discloses the semiconductor structure, wherein the dielectric bar has a first width (W2) in the top region of the set of stacked transistors and a second width (W1), different from the first width, in the bottom region of the set of stacked transistors (see figure 1 and column 8 lines 54-67).
[Re claim 6] Lilak discloses the semiconductor structure, wherein the dielectric bar comprises a first layer (451) and a second layer (452) (see figure 4 and column 13 line 35-57).
[Re claim 12] Lilak discloses the system, wherein the system comprises: a semiconductor structure, wherein the semiconductor structure comprises: a set of stacked transistors, wherein the set of stacked transistors comprises: a first transistor (130), wherein the first transistor comprises a first one or more channels and a first gate having a gate-all-around (GAA) structure; a second transistor (110), wherein the second transistor comprises a second one or more channels and a second gate, the second transistor having a gate structure different than a GAA structure; and a dielectric bar (151) (see figure 1 and column 5 line 47-58 and column 7 line 32 through column 8 line 67).
[Re claim 13] Lilak discloses the system wherein the second gate has a tri-gate structure (see figure 1 and column 5 line 47-58 and column 8 lines 42-53).
[Re claim 18] Lilak discloses the system wherein the dielectric bar (151) has a first width (W2) in a top region of the set of stacked transistors and a second width (W1), different from the first width, in a bottom region of the set of stacked transistors(see figure 1 and column 8 lines 54-67).
Allowable Subject Matter
Claim 5, 7-11, 14-17 and 19 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 20 allowed.
The following is an examiner's statement of reasons for allowance: Claim 20 allowable because of the prior art, either singly or in combination, fails to anticipate or render obvious, the method, wherein the second layer is directly contacting the set of stacked nanosheets; selectively recessing the second layer of the dielectric bar, resulting in a space between the top nanosheets and the dielectric bar; depositing a first gate; and depositing a second gate, wherein the second gate surrounds all sides of the top nanosheets, resulting in a gate-all-around (GAA) structure for the second gate. These features in combination with the other elements of the claim are neither disclosed nor suggested by the prior art of record.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KYOUNG LEE whose telephone number is (571)272-1982. The examiner can normally be reached M to F, 10am to 6pm.
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/KYOUNG LEE/ Primary Examiner, Art Unit 2817
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