Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are presented for Examination.
DETAILED ACTION
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et.al. (U.S Patent Application Publication 2012/0210032; hereinafter Wang”; Reference cited as prior art in previous office action ) in view of Lee et.al. (U.S Patent Application Publication 2013/0198540; hereinafter Lee”; Reference cited as prior art in previous office action )
1
Regarding Claims 1, 9, 16, Wang discloses, A processor device, comprising:
a plurality of processing elements (PEs) [“ Host system 402 may include chipset 405, processor 410, host memory 412, storage 414, graphics subsystem 41”, 0039]; and
a low-power mode (LPM) selection circuit configured to: [“an operating system (OS) kernel 102 that communicates with device 150 and central processing unit (CPU) 152. “, 0014; “OS 102 can cause CPU 152 to enter a deeper power saving state Cx. For example, the idle state can be any of C1, C2, C4 or C6. .. “, 0015; “Idle governor 110 is to decide which lower power state (if any) that CPU 152 is to enter by considering at least two factors: (1) heuristic prediction and (2) device LTR or tLTR, as the case may be. ..”, 0027]
determine an average inter-processor interrupt (IPI) arrival interval for a PE of the plurality of PEs [ “ Device driver 108 is provided by the designer of device 150. In various embodiments, device driver 108 is to determine a temporary latency tolerance report (tLTR) value for device 150. …”, 0018; “driver 108 can post a relatively large tLTR value and observe the interrupt interval from device 150. .. Driver 108 can observe the interval between multiple device interrupts and the observed interval value can be used as tLTR. In another example, driver 108 can observe interrupt intervals during a period of time and determine the average interrupt interval. The tLTR can be set as the average interrupt value.”, 0020; ( i.e. determining an average interrupt arrival rate of a processor/ CPU from a device with in a system. Examiner interprets the inter-processor interrupt as the interrupt received from other devices or processors with in a system)].
determine whether the average IPI arrival interval is greater than a minimum residency interval for a first LPM of the PE, wherein the first LPM is associated with lower power consumption and higher entry and exit latency relative to a second LPM of the PE [ “the idle state can be any of C1, C2, C4 or C6. Idle states C1, C2, C4 or C6 are associated with processors from Intel Corporation, however idle states for other processors can be used. .. For these idle states, the clock signal for CPU 152 can be stopped and the internal CPU voltage can be reduced. In general, the higher the numeral for the idle state, the lower the power consumed .A lower power state consumes less power but there is a longer time to enter and exit the lower power state. In addition, the lower power states require longer energy break-even time, i.e., time to remain in that lower power state to justify entering and exiting that state. “, 0015; ( i.e plurality of low power/ idle states of the processor / CPU; the deepest power state / C6 has the highest entry and exit latency compared to C5 and C6 has the highest entry and exit latency compared to C4 and so on. ); “.. Processor-related information can include an energy breakeven time (Ex) and resume latency (Rx) for different Cx power states. An energy break-even time is a time taken for a device to recoup the power consumed to enter and exit a lower power state, Cx. ...”, 0016; (i.e. The break-even duration/ interval determines the minimum duration / time the processor has to remain in the respective low power state.. C6 has the maximum break even time compared to C5. Therefore, each idle state is associated with a break even time . Hence determining the minimum residency interval for a power state); “ If interrupt intervals are longer than the maximum Ex, which corresponds to energy break even time for the deepest Cx state, then the default device LTR value is not modified to be tLTR because the CPU does not need to respond faster even in its deepest sleep state. If interrupt intervals are shorter than the maximum Ex, then device driver 108 posts tLTR. Device driver 108 can obtain the Ex value, for example, from ACPI table 104 or another source, …”, 0022; ( i.e. determining whether the interrupt intervals are greater or lower than the break-even time of the deepest low power state (C6). Wang also teaches determining the average interrupt interval based on the interrupt intervals during a period of time ”, [para 0020]. Hence it is apparent to compare the average interrupt interval with the break-even time of the C6 idle state.)];
responsive to determining that the average IPI arrival interval is greater than the minimum residency interval for the first LPM, place the PE in the first LPM; and [“if interrupt intervals are longer than the maximum Ex, which corresponds to energy break even time for the deepest Cx state, then the default device LTR value is not modified to be tLTR because the CPU does not need to respond faster even in its deepest sleep state; ( i.e allowing to device to be placed in the deepest low power state C6) ; 0031];
responsive to determining that the average IPI arrival interval is not greater than the minimum residency interval for the first LPM, place the PE in the second LPM. [ “ If interrupt intervals are shorter than the maximum Ex, then device driver 108 posts tLTR.”, 0022; The tLTR value can be used to prevent the CPU from entering too deep a C state when device driver 108 anticipates multiple sequential interrupts for a transaction.. Thus, if the device rapidly generates interrupts, the tLTR can be set to a small value to potentially prevent the CPU from going into too deep a sleep state and thereby taking too long to exit sleep state and return to normal operation (e.g., C0) ...”, 0018; ( i.e preventing the device to enter the deepest idle power state(C6) and entering a shallower idle state ( C2/ C3/ C4). Hence entering a second low power idle state)] ;
However, Wang does not expressly disclose average inter-processor interrupt (IPI) arrival interval for a PE based on an IPI arrival history table for the PE. Specifically, Wang discloses determining average inter-processor interrupt (IPI) arrival interval for a PE and does not expressly disclose an IPI arrival history table for the PE.
In the same field of endeavor (e.g. Dynamically reducing power consumption by a processor in a computer system by determining a maximum number of times (token count) that the processor can incur a start-up delay after being placed into a low-power mode during a token period of time when executing a task for a token period of time), Lee teaches,
IPI arrival history table for the PE [“If the wake-up latency of a LPM is negligible, the processor may be put into LPM whenever the processor is idle, and wake it up in the event of a wake-up request, such as a wake-up interrupt.”, 0019; 0069; “Execution of the task is resumed by waking 916 the processor out of the low-power mode. This generally occurs as a result of a functional interrupt produced by a device or peripheral within the system, or by a counter or timer, for example. “, 0075; “The average number of times that CPU 202 receives an interrupt before DSC wakes it up may be monitored. This represents how well the DSC's wake-up mechanism is working. ..”, 0062; “Wakeup_time_slot Decision Map (WDM)' 500 illustrated in FIG. 5. “, 0043; “DSC 220 uses WDM 500 to decide when to wake the CPU up for each time-slot. …”, 0044; Fig.5, 6; “A token period 530 is pre-defined, and the period is divided into time-slots. If a wake-up request occurs at a certain time-slot, a counter corresponding to the time-slot is incremented. For example, wake-up request 545 is recorded for time slot 17 as indicated at 517a.”, 0046-0047; “Note that the wake-up probability map represents the history of the task activity pattern and the hypothesis is that such statistics of a past activity pattern will be somewhat valid for prediction of near future behavior of the system.”, 0048; Fig.5, (i.e. wake-up interrupt arrival history of the CPU is recorded in a table as illustrated in Fig.5, 6; (Wakeup_time_slot Decision Map (WDM)) based on which the dynamic sleep controller determines waking the CPU from low power mode to minimize the wake-up latency)].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Wang with Lee. Lee’s teaching of dynamically reducing power consumption by a processor in a computer system by determining a maximum number of times (token count) that the processor can incur a start-up delay after being placed into a low-power mode will substantially improve Wang’s system to reduce/ minimize the wake-up latency by preemptively wakeup the CPU before a functional interrupt occurs or placing the LPM in a low power mode if the wake-up latency is negligible.
Regarding Claims 2, 10 Lee teaches, wherein each PE of the plurality of PEs comprises a processor core [0064-0065; 0084].
Regarding Claims 3, 11, Lee teaches, wherein each PE of the plurality of PEs comprises a core cluster [0064-0065; claim10].
Regarding Claims 4, 12, 17, Wang teaches, the first LPM comprises a power collapse LPM [ 0015; ( i.e (it is apparent that the voltage / power is reduced for the deepest low power idle state (C6) compared to shallower idle state( C2/ C3/ C4) ; and the second LPM comprises a clock gating LPM [0015].
Regarding Claims 5, 13, 18, Wang discloses (LPM) selection circuit[0014; 0027]
Wang teaches detect an IPI received by the PE [ 0046];
determine an IPI arrival interval for the IPI based on an arrival time of the IPI and an arrival time of a previous IPI; and store the IPI arrival interval in the IPI arrival history table for the PE.[0062; 0043-0044; 0047-0049; Fig.5, 6].
Regarding Claims 6, 14, 19, Wang discloses the LPM selection circuit [0014; 0027] and other limitations as outlined in claim 1.
Lee teaches identify an arrival interval pattern in the IPI arrival history table [0043-0044; Fig.5]; and determine the average IPI arrival interval for the PE responsive to identifying the arrival interval pattern in the IPI arrival history table .[0062; 0043-0044; 0047-0049; Fig.5, 6].
Regarding claims 7, 15, 20, Wang discloses, wherein the LPM selection circuit is configured to place the PE in the first LPM by being configured to set an LPM interval for the first LPM [0014-0016;0022; 0027].
However, Wang does not expressly disclose determining lesser of the average IPI arrival interval and a next scheduled task interval, to place the CPU in low power mode.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Wang to “determine lesser of the average IPI arrival interval and a next scheduled task interval” to set an LPM interval for a low power mode as Wang teaches determining an average interrupt arrival rate [0020] and place the processor in the deepest idle power mode (C6) or shallower idle state (C1/C2/ C4) . Further Wang teaches anticipating multiple sequential interrupts [0018] of a transaction, the transaction including multiple tasks [0004] and estimating the next idle duration based on historical information [0006], to set a low power mode interval in order to justify the energy savings to enter and exit in the respective low power state[0007; 0015-0016].
Regarding Claim 8, Wang discloses, integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; and a vehicle component [0039].
Response to Arguments
Applicant's arguments filed on 02/03/2026 have been fully considered, but they are not persuasive to the extent that is applicable to the current pending claims.
Applicant argues in substances that:
Regarding claims 1, 9, 16 “Applicant respectfully submits that the cited combination of references fails to disclose or suggest claim’ s recitation of "plac[ing] the PE" in either a "first LPM" or a "second LPM" based on "whether the average IPI arrival interval is greater than a minimum residency interval for [the] first LPM."
Applicant first respectfully notes that the Office Action on page 5 alleges that the "device driver 108" of Wang is the element that performs the recited operations for "plac[ing] the PE in the first LPM..”, Wang nowhere discloses or suggests that the "device driver 108" actually places the disclosed "CPU 152" in different power modes. Instead, Wang only discloses that the "device driver 108" may set the value of the "tLTR" (or leave the value of the "tLTR" unchanged) based on whether or not an "interrupt interval" is longer than the "maximum Ex."
Applicant further respectfully submits that the element of Wang that appears to actually perform operations corresponding to the above-quoted recitations of claim 1 is the "idle governor 110," which is described as "decid[ing] which lower power state (if any) that CPU 152 is to enter. There is no disclosure or suggestion therein that the "idle governor 110," or any other element described by Wang, performs a comparison of "LTR" or "tLTR" with "Ex" to determine which of multiple lower power states to place a processor.
[Applicant’s remarks Pages 7-9]
The examiner respectfully traverses applicant’s arguments for the following reasons:
As to Point A:
Regarding claim 1, Wang teaches, “Driver 108 can provide the determined tLTR value to idle governor 110 in response a first interrupt from device 150 in a transaction after the transaction in which interrupts were measured to determine the tLTR value..”, 0024; “Idle governor 110 is to decide which lower power state (if any) that CPU 152 is to enter by considering at least two factors: (1) heuristic prediction and (2) device LTR or tLTR, as the case may be”, 0027; 0038;“The driver obtains Ex to decide whether it needs to post tLTR instead of LTR. The idle governor later compares tLTR to Rx to determine which state to enter. I..”, 0022; i.e posting the tLTR value determined by the driver to the idle governor .
Further Wang teaches , “The default device LTR value can be the highest LTR value permitted by an idle governor. If the determined tLTR value is less than the default device LTR value, then block 206 follows block 204. If the determined tLTR value is not less than the default device LTR value, then the process ends.”, 0034; 0020; Fig.3; i.e. the driver determines the tLTR value by comparing the interrupt intervals over a period of time with the minimum residence interval (break-even time of the deepest low power state (C6). The idle governor determines which idle state to enter based on the tLTR value received from the driver.
Wang also teaches , the OS includes the Advanced Configuration and Power Interface (ACPI) , Scheduler, Device driver , Idle governor components that interfaces with the devices and control the idles state of the Processor / CPU as illustrated in Fig.2. and “OS 102 can cause CPU 152 to enter a deeper power saving state Cx..”, [0015].
Therefore, the idle governor of the OS is configured to determine the low power / idle state based on the information received from the driver.
Further the claim only recites “a low-power mode (LPM) selection circuit configured to” , to place the processing element in a first or second LPM state in response to the determining steps.
In light of these teachings, Wang teaches “a low-power mode (LPM) selection circuit configured to: determine an average inter-processor interrupt (IPI) arrival interval for a PE of the plurality of PEs; determine whether the average IPI arrival interval is greater than a minimum residency interval for a first LPM of the PE, ..” to the extent the limitations are claimed.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Naveh et al., U.S Patent Application Publication 2012/0191995, teaches A processor may include power management techniques to, dynamically, chose an optimal C-state for the processing core. The power control logic may, dynamically, determine an optimal C-state based on the CPU idle residency times and variable rate wakeup events to match the expected wakeup event rate.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GAYATHRI SAMPATH whose telephone number is (571)272-5489. The examiner can normally be reached on Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached on 5712701640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/GAYATHRI SAMPATH/ Examiner, Art Unit 2176
/JAWEED A ABBASZADEH/ Supervisory Patent Examiner, Art Unit 2176
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