Prosecution Insights
Last updated: October 02, 2026
Application No. 18/618,180

DOHERTY AMPLIFIER CIRCUIT

Final Rejection §102§103
Filed
Mar 27, 2024
Priority
Mar 31, 2023 — JP 2023-058640
Examiner
RAHMAN, HAFIZUR
Art Unit
Tech Center
Assignee
Murata Manufacturing Co., Ltd.
OA Round
2 (Final)
93%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 93% — above average
93%
Career Allowance Rate
700 granted / 750 resolved
+33.3% vs TC avg
Moderate +9% lift
Without
With
+8.6%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
36 currently pending
Career history
775
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
45.8%
+5.8% vs TC avg
§102
35.1%
-4.9% vs TC avg
§112
13.1%
-26.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 750 resolved cases

Office Action

§102 §103
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claim 1 of the current application is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of copending Application No. 18/441,291. Although the claims at issue are not identical, they are not patentably distinct from each other because both independent claims are directed to a Doherty amplifier circuit invented by IMAI, comprising a carrier amplifier, a peak amplifier, and a control circuit that regulates the peak amplifier based on the drive level of the carrier amplifier. The primary differences between the two claims are: Bias Circuits: The present application explicitly recites a "first bias circuit" for the carrier amplifier and a "second bias circuit" for the peak amplifier, whereas the copending application broadly recites controlling the "peak amplifier" without explicitly naming the bias circuits. Control Signals: The present application specifies that the control circuit controls the second bias circuit based on "an input high frequency signal, and a signal indicating a drive level". The copending application states the control circuit detects the drive level "based on an input of the carrier amplifier" and controls the peak amplifier "based on the detected drive level". However, the differences between the claims are not patentably distinct. In the art of RF amplifiers, controlling the operation of a peak amplifier in a Doherty configuration is universally and inherently achieved by controlling the bias applied to that amplifier. Therefore, adding explicit "first" and "second bias circuits" is an obvious structural recitation of the functional limitation claimed in the copending application. Furthermore, utilizing the "input high frequency signal" in addition to a "signal indicating a drive level" to control the second bias circuit is an obvious variant of detecting the drive level "based on an input of the carrier amplifier". Because the claims are effectively directed to the same core invention and are obvious variations of one another, a Provisional Nonstatutory Obviousness-Type Double Patenting rejection is appropriate. This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 4 and 5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lehtola (US 2021/0036661 A1). PNG media_image1.png 578 505 media_image1.png Greyscale Fig. 4 of Lehtola reproduced for ease of reference. Regarding Claim 1, Lehtola discloses a Doherty power amplifier circuit (power amplifier system 110). Lehtola also discloses a carrier amplifier configured to amplify a high frequency signal (carrier amplification stage 101 receives and amplifies the RF input signal). Lehtola also discloses a peak amplifier configured to amplify the high frequency signal (peaking amplification stage 102). Finally, Lehtola discloses a control circuit (saturation detector 103) configured to detect a drive level of the carrier amplifier based on an input of the carrier amplifier (the saturation detector 103 includes an input electrically connected to the input of the carrier amplification stage 101 to monitor for saturation, which directly corresponds to the drive level/compression state of the amplifier). Furthermore, Lehtola teaches that the control circuit controls the peak amplifier based on the detected drive level (the saturation detector 103 outputs a saturation detection signal SAT_DETECT which is provided to the peaking amplification stage 102 to turn it on or adjust its bias level in response to the saturation/drive level of the carrier stage). Regarding Claim 4: Lehtola discloses a Doherty amplifier circuit where the control circuit (saturation detector 103) is configured to detect the input signal of the carrier amplifier. Lehtola explicitly states that the input of the saturation detector 103 is "electrically connected to the input of the carrier amplification stage 101" to monitor the RF input signal voltage. Furthermore, Lehtola discloses that this monitored input voltage is used to detect the saturation state (which is the drive level) of the carrier amplifier, noting that the base voltage decreases below VBE as the amplifier enters saturation. Therefore, Lehtola fully anticipates detecting the drive level based on the detected input signal. Regarding Claim 5: Lehtola discloses that the control circuit has a defined sensitivity or threshold value for detecting this drive level based on the input signal. Specifically, Lehtola teaches that the saturation detector is specifically calibrated to "detect for very small changes in base voltage, for instance, tens of mV". This sharp sensitivity threshold triggers the saturation detection signal (SAT_DETECT) to switch between a high and low voltage state to activate the peaking stage. Thus, the limitation is anticipated. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Lehtola in view of Marr (US 2022/0158346 A1). Regarding claims 2 and 3, Lehtola teaches a Doherty amplifier circuit comprising a carrier amplifier and a peak amplifier, along with a control circuit (saturation detector 103) configured to detect the drive level (saturation) of the carrier amplifier and control the peak amplifier based on that detected drive level. Lehtola, however, does not disclose detecting the drive level of the carrier amplifier based on a supply current of an amplifying transistor in the carrier amplifier. Instead, Lehtola detects saturation by monitoring the base voltage and utilizing thermal coupling between a gain transistor and a detection transistor. PNG media_image2.png 495 693 media_image2.png Greyscale Fig. 8B of Marr reproduced for ease of reference. Marr, in a similar field of endeavor, discloses an advanced power management system for RF field effect transistor (FET) amplifiers that actively monitors the operational state and drive level of an amplifier by directly sensing the supply current (drain current) of the amplifying transistor. Per Claim 2, Marr teaches a sensing system 821 (Fig. 8B) configured to sense current values (e.g., drain supply current) of individual amplifiers, stating that the "sensed current value can be analyzed… to determine an operational or a physical characteristic", §0330, of the amplifier and adjust the bias accordingly. Per Claim 3, Marr explicitly teaches that the control circuit evaluates the supply current using a threshold value to determine the amplifier's state. Marr discloses defining an "upper current threshold value and lower current threshold value", §0357, Fig. 12, to determine if the measured supply current dictates that the operating state has deviated and requires a bias adjustment. PNG media_image3.png 244 523 media_image3.png Greyscale Fig. 12 of Marr reproduced for ease of reference. It would have been obvious to a person of ordinary skill in the art at the time of the invention to modify the drive-level detection mechanism of Lehtola to incorporate the supply current (drain current) sensing mechanism taught by Marr. Specifically, instead of relying on the complex thermal coupling and base-voltage monitoring of Lehtola, the control circuit would be configured to measure the drain supply current of the carrier amplifier and compare it against predefined current thresholds (as taught by Marr) to determine when the carrier amplifier is reaching its saturation drive level. The motivation to implement this modification is to provide a more direct, accurate, and layout-independent electrical measurement of the carrier amplifier's drive level. As Lehtola's thermal coupling requires strict spatial constraints (e.g., fabricating transistors within 20 µm of each other or within half a substrate thickness), a person of ordinary skill in the art would be highly motivated to adopt Marr's supply current sensing technique. Measuring the drain supply current eliminates restrictive thermal layout requirements while providing a highly reliable, instantaneous threshold metric to determine the amplifier's operational state and saturation limits. Conclusion The prior arts, Hayakawa (US20110199156), Murao (US20110285460), Huo (US20190158030), Imai (US20240186956), Imai et al., “Dual-Adaptive Bias Scheme of Condition-Tolerant Doherty Power Amplifier for 5G Handsets”, IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 73, NO. 5, MAY 2025. Yong-Sub Lee et al., “Highly Linear and Efficient Doherty Amplifier Employing Power Tracking Bias Supply Scheme for WCDMA Applications”, Run-Ze Zhan et al., “A Highly Efficient 60 GHz CMOS Doherty Power Amplifier With Adaptive Gate Biases”, Zhang et al., “High Efficiency Doherty Power Amplifier Using Dual-Adaptive Biases”, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS, VOL. 67, NO. 8, AUGUST 2020. Yong-Sub Lee et al., “Highly Linear Power Tracking Doherty Amplifier for WCDMA Repeater Applications”, IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 18, NO. 7, JULY 2008, made of record and not relied upon is considered pertinent to applicant's disclosure. Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAFIZUR RAHMAN whose telephone number is (571)270-0659. The examiner can normally be reached M-F: 10-6. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached on (571) 272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HAFIZUR RAHMAN/Primary Examiner, Art Unit 2843.
Read full office action

Prosecution Timeline

Mar 27, 2024
Application Filed
Jun 09, 2026
Non-Final Rejection mailed — §102, §103
Sep 08, 2026
Response Filed
Sep 29, 2026
Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
93%
Grant Probability
99%
With Interview (+8.6%)
2y 1m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 750 resolved cases by this examiner. Grant probability derived from career allowance rate.

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