Prosecution Insights
Last updated: July 17, 2026
Application No. 18/618,226

FLYING CAPACITOR VOLTAGE AND INDUCTOR CURRENT COMPENSATION FOR NONLINEAR COUPLING IN A THREE-LEVEL CONVERTER

Non-Final OA §102§112
Filed
Mar 27, 2024
Priority
Feb 01, 2024 — provisional 63/548,677 +1 more
Examiner
LAXTON, GARY L
Art Unit
2838
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Cirrus Logic International Semiconductor Ltd.
OA Round
2 (Non-Final)
86%
Grant Probability
Favorable
2-3
OA Rounds
0m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
957 granted / 1107 resolved
+18.4% vs TC avg
Moderate +6% lift
Without
With
+5.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
20 currently pending
Career history
1127
Total Applications
across all art units

Statute-Specific Performance

§101
0.8%
-39.2% vs TC avg
§103
50.2%
+10.2% vs TC avg
§102
13.3%
-26.7% vs TC avg
§112
11.5%
-28.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1107 resolved cases

Office Action

§102 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant's arguments filed 3/23/2026 have been fully considered but they are not persuasive. First, the applicant argues there are no problems with claim 9. The applicant points to the specification paragraph [0050] in attempting to explain the term fade out control. Paragraph [0050] states fading out its reliance on offset signal. This does nothing to explain what exactly the applicant means by fade out control of switch signals. It also does nothing to explain the exact operation or function of fading out. [0050] As duty cycle signal D approaches 0 or 1, either reference signal REF1 or REF2 may saturate. In such cases, it may be desirable to preserve duty cycle signal D (including the duty cycle compensation described above) and “sacrifice” α. In other words, as duty cycle signal D approaches 0 or 1, reference generator 410 may continue to rely on duty cycle signal D to control reference signals REF1 and REF2, while fading out its reliance on offset signal α in the control of reference signals REF1 and REF2 when duty cycle signal D is within a predefined margin of 0 or 1. The following pseudocode describes an algorithm to take in account such saturation: “Fade out” is commonly known as a term in Film, Radio or Tv meaning gradual disappearance or becoming indistinct of a scene or sound, according to Websters Dictionary. Fade out is not an electrical term. Beside paragraph [0050], the specification is completely silent as to what exactly the applicant means. How is it faded out, where is it faded to, what is being faded, how far is it faded? Claim 9 is indefinite. Second, the applicant argues that Assaad does not disclose flying capacitor voltage control loop that generates signals for switching the switch configuration to regulate the flying capacitor voltage. Just reading the abstract of Assaad it is clearly explained how the flying capacitor voltage is balanced (i.e. regulated) by sense and control circuitry providing duty cycle adjustment (i.e. changing switch configurations: ON/OFF.) Next, the applicant argues that Assaad does not sense inductor current. see figure 4 below. PNG media_image1.png 504 804 media_image1.png Greyscale Concerning prior art reference Kim, the applicant argues that Kim does not show provide compensation. This is a broad term and while it may not compensate as the applicant envisions and change provided by the circuit is compensation. If the applicant wants a particular type of “compensation” then it should be claimed. The applicant is reminded that although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). The applicant also argues the compensator is distinct, separately identified and performs a separate function. This is unpersuasive. As explained, the claim reads on the prior art reference Kim perfectly. Nothing in the claim supports the applicant’s argument. If the applicant wishes separate distinct circuits performing separate functions then provide claim language that excludes how Kim reads on the claim. Currently, the claim is silent about which circuits are doing what and whether they must be separate, distinct or perform separate functions. Be exact when claiming your invention. The examiner finds the applicants argument unpersuasive. The claims are clearly broad enough to encompass the cited prior art and therefore, the examiner maintains the rejections with the cited prior art as set forth below from the previous office action dated 3/03/2026. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 9 and 23 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 9 recites the limitation "fade out control" in line 6. The specification is silent in regards to what exactly the applicant means by fade out control. Claim23 has the same existing issue as claim 9 with the term fading out control. Those terms are not common electrical terms and are undefined. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1, 6, 14, 15, 17, 20, 21 and 28 is/are rejected under 35 U.S.C. 102a1/a2 as being anticipated by y Assaad et al. (US 9866113). Claims 1, 14, 15 and 28; Assaad et al. disclose a system (and method) comprising: a multi-level power converter comprising a plurality of switches (110), a power inductor (122A) electrically coupled to the plurality of switches, and a flying capacitor (120) coupled to the plurality of switches, wherein the plurality of switches are controllable among a plurality of switch configurations in order to generate an output voltage (Vout) from an input voltage (Vin) received by the multi-level power converter; a flying capacitor voltage control loop (VCFLY) configured to, based on an error signal (226) between a measurement of a flying capacitor voltage across (+ input VCFLY) terminals of the flying capacitor (120) and a flying capacitor reference voltage (- input), generate switch control signals (254A/B) for switching among the plurality of switch configurations in order to regulate the flying capacitor voltage; and a compensator (224A, 230A, 224B, 230B) configured to apply compensation to the flying capacitor voltage control loop based on a measurement of an inductor current (122A, 210, 212, 218, 220) flowing through the power inductor. Claims 6 and 20; Assaad et al. disclose a system comprising: a multi-level power converter comprising a plurality of switches (110), a power inductor (122A) electrically coupled to the plurality of switches, and a flying capacitor (120) coupled to the plurality of switches, wherein the plurality of switches are controllable among a plurality of switch configurations in order to generate an output voltage (VIN) from an input voltage (VOUT) received by the multi-level power converter; a power inductor current control loop (146: e.g. L, 210, 218, 212, 220) configured to, based on an error signal (from diff amp 218: col. 6 line 17) between a measurement of an inductor current flowing through the power inductor (122A) and a reference inductor current (from 216), generate switch control signals for switching among the plurality of switch configurations in order to regulate the inductor current; and a compensator configured (148) to apply compensation to the power inductor current control loop based on a measurement of a flying capacitor voltage (VCFLY) across terminals of the flying capacitor (CFLY). Claim 17; generating a control parameter (GMdc) with a loop controller based on the error signal (226) and generating the switch control signals based on the control parameter; and applying a compensation to the control parameter (224A) based on the measurement of the inductor current (from 218). Claim 21; generating with a loop controller a control parameter (R from 224A) based on the error signal (218) and generating the switch control signals based on the control parameter; and applying a compensation (GMdc) to the control parameter based on the measurement of the flying capacitor voltage (226). Claim(s) 1, 3, 4, 6, 7, 14, 15, 17, 20, 21 and 28 is/are rejected under 35 U.S.C. 102a1/a2 as being anticipated by Kim (US 11356021). Claims 1, 14, 15 and 28; Kim et al. disclose a system (and method) comprising: a multi-level power converter comprising a plurality of switches (S1-S4), a power inductor (L) electrically coupled to the plurality of switches, and a flying capacitor (CFC) coupled to the plurality of switches, wherein the plurality of switches are controllable among a plurality of switch configurations in order to generate an output voltage (T11) from an input voltage (T21) received by the multi-level power converter; a flying capacitor voltage control loop (VFC, 13) configured to, based on an error signal (131) between a measurement of a flying capacitor voltage across (+ VFC) terminals of the flying capacitor (CFC) and a flying capacitor reference voltage (- VFC), generate switch control signals (144/145) for switching among the plurality of switch configurations in order to regulate the flying capacitor voltage; and a compensator (IL, 133, 134) configured to apply compensation to the flying capacitor voltage control loop based on a measurement of an inductor current (IL) flowing through the power inductor (L). Claim 3; Kim et al. disclose the loop controller configured to generate a control parameter based on the error signal and generate the switch control signals based on the control parameter; and the compensator is configured to apply a compensation to the control parameter based on the measurement of the inductor current. Claim 4; Kim et al. disclose the flying capacitor voltage control loop comprises a loop controller configured to generate a control parameter based on the error signal and generate the switch control signals based on the control parameter; and the compensator is configured to apply a compensation to a gain (134) of the loop controller based on the measurement of the inductor current. Claims 6 and 20; Kim et al. disclose a system (and method) comprising: a multi- level power converter comprising a plurality of switches (S1-S4), a power inductor (L) electrically coupled to the plurality of switches, and a flying capacitor (CFC) coupled to the plurality of switches, wherein the plurality of switches are controllable among a plurality of switch configurations in order to generate an output voltage (T11) from an input voltage (T21) received by the multi-level power converter; a power inductor current control loop (12) configured to, based on an error signal (121) between a measurement of an inductor current (IL) flowing through the power inductor and a reference inductor current (IL*), generate switch control signals for switching among the plurality of switch configurations in order to regulate the inductor current; and a compensator (141, 142, 143) configured to apply compensation (VCM*) to the power inductor current control loop based on a measurement of a flying capacitor voltage (VFC from 13) across terminals of the flying capacitor. Claim 7; a loop controller configured to generate a control parameter (VDM* based on the error signal (121) and generate the switch control signals (144, 145) based on the control parameter; and the compensator (141, 142, 143) is configured to apply a compensation to the control parameter based on the measurement of the flying capacitor voltage (VCM* from 13). Claim 17; generating a control parameter (132) with a loop controller based on the error signal (131) and generating the switch control signals based on the control parameter; and applying a compensation to the control parameter (at 134) based on the measurement of the inductor current (IL). Claim 18; generating a control parameter (132) with a loop controller based on the error signal and generating the switch control signals based on the control parameter; and applying a compensation (at 133) to a gain (134) of the loop controller based on the measurement of the inductor current (IL). Claim 21; a loop controller configured to generate a control parameter (VDM* based on the error signal (121) and generate the switch control signals (144, 145) based on the control parameter; and the compensator (141, 142, 143) is configured to apply the compensation to the control parameter based on the measurement of the flying capacitor voltage (VCM* from 13). Allowable Subject Matter Claims 2, 5, 8, and 10-13, 16, 19, 22 and 24-27 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 9 and 23 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to GARY L LAXTON whose telephone number is (571)272-2079. The examiner can normally be reached Monday-Friday, 8 am-4 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal Hammond can be reached at 571-270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /GARY L LAXTON/Primary Examiner, Art Unit 2838 5/29/2026
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Prosecution Timeline

Mar 27, 2024
Application Filed
Mar 03, 2026
Non-Final Rejection mailed — §102, §112
Mar 23, 2026
Response Filed
Jun 01, 2026
Final Rejection mailed — §102, §112
Jun 24, 2026
Response after Non-Final Action

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
86%
Grant Probability
92%
With Interview (+5.6%)
2y 2m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1107 resolved cases by this examiner. Grant probability derived from career allowance rate.

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