DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to claims filed 03/27/2024.
Claims 1-20 are pending.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in China on 03/31/2023. It is noted, however, that applicant has not filed a certified copy of the CN202310345043.2 application as required by 37 CFR 1.55.
Drawings
The drawings are objected to under 37 CFR 1.83(a) because they fail to show determining a target address based on the type of processing command, obtaining a node code, a node code and preset mapping relationship, determining at least one task in a running process, configuring a node code corresponding to a task, a command and target address being written into a buffer, a target storage area being determined from multiple storage areas of different processing units, and the command written into a target storage area as described in the specification. Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to because FIG 3 S301 and S302 are the exact same step. In the specification, both of these steps refer to Step 302. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The abstract of the disclosure is objected to because it merely recites word for word the claim language recited in claim 1. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The disclosure is objected to because of the following informalities: drawings that do not exist are referred to in at least the following paragraphs [0034], [0035], [0038], [0040], [0042], [0045], [0048], [0049], [0052], [0053], [0056]-[0059], [0062]-[0065], [0067]. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
the specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 2, 3, 10,11, 18, 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 2, 10, and 18 recite the limitation “the target processing module includes a first target processing module” and “the target processing unit determined to be a first target processing unit”. It is indefinite and not clearly understood whether the target processing module is a first target processing module or whether a first target processing module is a component within the target processing module. Similarly, it is indefinite and not clearly understood whether the target processing unit is a first target processing unit or whether a first target processing unit is a component within the target processing unit. For the purpose of compact prosecution, Examiner will interpret the first target processing module to be a first target processing module and a first target processing unit to be a processing unit within the processing module.
Claims 3, 11, and 19 recite the limitation “the target processing module includes a first target processing module and a second target processing module” and “the target processing unit being determined to be a second target processing unit”. It is indefinite and not clearly understood whether the target processing module is a second target processing module or whether a second target processing module is a component within the target processing module. Similarly, it is indefinite and not clearly understood whether the target processing unit is a second target processing unit or whether a second target processing unit is a component within the target processing unit. For the purpose of compact prosecution, Examiner will interpret the second target processing module to be a second target processing module and a second target processing unit to be a processing unit within the processing module.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention recites a judicial exception, is directed to that judicial exception, an abstract idea, as it has not been integrated into practical application and the claims further do not recite significantly more than the judicial exception. Examiner has evaluated the claims under the framework provided in the 2019 Patent Eligibility Guidance published in the Federal Register 01/07/2019 and has provided such analysis below. Step 1: Claims 1-8 are directed to methods and fall within the statutory category of processes; Claims 9-16 are directed to a processing apparatus and falls within the statutory category of articles of manufacture; and Claim 17-20 are directed to an electronic device and falls within the statutory category of machines. Therefore, “Are the claims to a process, machine, manufacture or composition of matter?” Yes.
In order to evaluate the Step 2A inquiry “Is the claim directed to a law of nature, a natural phenomenon or an abstract idea?” we must determine, at Step 2A Prong 1, whether the claim recites a law of nature, a natural phenomenon or an abstract idea and further whether the claim recites additional elements that integrate the judicial exception into a practical application.
Step 2A Prong 1: Claims 1, 9, and 17: The limitations of “recognizing the processing command to obtain a recognition result; determining a target processing unit, such that the target processing unit is able to process the processing command”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of limitation in the mind. For example, a person can think and observe, judge and evaluate recognizing a processing command to obtain a recognition result and based on the recognition result, determine a target processing unit. Therefore, Yes, claim 1 recites judicial exception. Step 2A Prong 2: Claims 1, 9, and 17: The judicial exception is not integrated into a practical application. In particular, the claim recites the following additional elements – “A processing apparatus, comprising a memory storing a computer program and a processor coupled to the memory, wherein being executed by the processor, the computer program causes the processor”, “An electronic device, comprising a memory storing a computer program and a processor coupled to the memory, when being executed by the processor, the computer program causing the processor to”, which are merely recitations of generic computing components and functions merely being used as a tool to apply the abstract idea (see MPEP 2106.05(f)) which does not integrate a judicial exception into a practical application. Further, claim 1 recites the following additional elements – “obtaining a processing command issued by an application program” which is merely a recitation of insignificant extra-solution activity of mere data gathering (see MPEP 2106.05(g)) and “the target processing unit including at least one of processing units used to form a target processing module” which is merely a recitation of a field of use/technological environment (see MPEP 2106.05(h)) which does not integrate a judicial exception into a practical application. These limitations will be further addressed below at Step 2B as also being Well-Understood, Routine, and Conventional (WURC). Therefore, “Do the claims recite additional elements that integrate the judicial exception into a practical application? No, these additional elements do not integrate the abstract idea into a practical application and they do not impose any meaningful limits on practicing the abstract idea. The claim is directed to an abstract idea.
After having evaluating the inquires set forth in Steps 2A Prong 1 and 2, it has been concluded that the claim 1 not only recites a judicial exception but that the claim is directed to the judicial exception as the judicial exception has not been integrated into practical application.
Step 2B:
Claims 1, 9, and 17: The claims do not include additional elements, alone or in combination, that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements amount to no more than generic computing components and field of use/technological environment which do not amount to significantly more than the abstract idea. Moreover, this insignificant extra-solution of data gathering is WURC, see MPEP 2106.05(d)(II) “The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. i. Receiving or transmitting data over a network …iv. Storing and retrieving information in memory”.
Therefore, “Do the claims recite additional elements that amount to significantly more than the judicial exception? No, these additional elements, alone or in combination, do not amount to significantly more than the judicial exception.
Having concluded analysis within the provided framework, claims 1, 9, and 17 do not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claims 2, 10, and 18, they recite additional abstract recitations of “in response to the target processing unit being determined to be a first target processing unit” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can think about and observe, judge and evaluate determining a first processing unit. Further claims 2, 10, and 18 recite “wherein: the target processing module includes a first target processing module and the first target processing unit belonging to the first target processing module” which is merely a recitation of a field of use/technological environment (see MPEP 2106.05(h)) as well as “using the first target processing unit to process the processing command” which is merely recitations of generic computing components and functions merely being used as a tool to apply the abstract idea (see MPEP § 2106.05(f)) without imposing meaningful limitation which does not integrate a judicial exception into practical application and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claims 2, 10, and 18 also fail both Step 2A prong 2, thus the claims are directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, Claims 2, 10, and 18 do not recite patent eligible subject matter under 35 U.S.C. § 101. With regard to claims 3, 11, 19, they recite additional abstract recitations of “in response to the target processing unit being determined to be a second target processing unit”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can think about and observe, judge and evaluate determining a first processing unit. Further claims 2, 10, and 18 recite “wherein: the target processing module includes a first target processing module and the first target processing unit belonging to the first target processing module” which is merely a recitation of a field of use/technological environment (see MPEP 2106.05(h)). Further claims 3, 11, and 19 recite “sending the processing command to the second target processing unit through the first target processing module” which is merely a recitation of insignificant extra-solution activity of mere data transmission (see MPEP 2106.05(g)). This insignificant extra-solution activity is WURC, see MPEP 2106.05(d)(II) “The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. i. Receiving or transmitting data over a network …iv. Storing and retrieving information in memory”, and “such that the second target processing unit is able to process the processing command” which is merely recitations of generic computing components and functions merely being used as a tool to apply the abstract idea (see MPEP § 2106.05(f)) without imposing meaningful limitation which does not integrate a judicial exception into practical application and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claims 3, 11, and 19 also fail both Step 2A prong 2, thus the claims are directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more Therefore, Claims 3, 11, and 19 not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claims 4,12, and 20, they recite additional abstract recitations of “wherein: the recognition result includes a type of the processing command; and determining the target processing unit based on the recognition result includes: determining a target address based on the type of the processing command, such that the target processing unit is called through the target address to process the processing command”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can think about and observe, judge and evaluate determining a type of result as well as a target address based on that type of result. Further, the target processing unit processing the processing command is merely recitations of generic computing components and functions merely being used as a tool to apply the abstract idea (see MPEP § 2106.05(f)) without imposing meaningful limitation which does not integrate a judicial exception into practical application and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claims 4, 12, and 20 also fail both Step 2A prong 2, thus the claims are directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more Therefore, Claims 4, 12, and 20 not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claim 5 and 13, they recite additional abstract recitations of “wherein determining the target address based on the type of the processing command, such that the target processing unit is called through the target address to process the processing command comprises: based on the type of the processing command, determining the target address; and writing the processing command and the target address into a buffer area, such that the target processing unit is driven based on the target address to respond to the processing command” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can think about and observe, judge and evaluate determining a target address based on a type of command. Further, the target processing unit processing the processing command is merely recitations of generic computing components and functions merely being used as a tool to apply the abstract idea (see MPEP § 2106.05(f)) without imposing meaningful limitation which does not integrate a judicial exception into practical application and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claims 5 and 13 also fail both Step 2A prong 2, thus the claims are directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more Therefore, Claims 5 and 13 do not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claim 6 and 14, they recite additional abstract recitations of “wherein: the recognition result includes a type of the processing command; and determining the target processing unit based on the recognition result includes: based on the type of the processing command, determining a target storage area from multiple storage areas on a storage module, different storage areas from the multiple storage areas correspond to different processing units; and writing the processing command into the target storage area, such that the target processing unit corresponding to the target storage area is able to process the processing command” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can think about and observe, judge and evaluate storage modules and determining a target storage area based on a type of processing command (see MPEP 2106.05(g)). This insignificant extra-solution activity of data storage and data transmission is WURC, see MPEP 2106.05(d)(II) “The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. i. Receiving or transmitting data over a network …iv. Storing and retrieving information in memory”. Further, the target processing unit processing the processing command is merely recitations of generic computing components and functions merely being used as a tool to apply the abstract idea (see MPEP § 2106.05(f)) without imposing meaningful limitation which does not integrate a judicial exception into practical application and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claims 6 and 14 also fail both Step 2A prong 2, thus the claims are directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more Therefore, Claims 6 and 14 do not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claim 7 and 15, they recite additional abstract recitations of “based on the node code and a preset mapping relationship, determining the processing command, the preset mapping relationship including mapping relationships between multiple node codes and multiple processing commands” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can think about and observe, judge and evaluate mapping relationships between node codes and processing commands as well as determining a command based on that relationship. Further, obtaining a node code during a running process is merely a recitation of insignificant extra-solution activity of mere data gathering (see MPEP 2106.05(g)). This insignificant extra-solution activity is WURC, see MPEP 2106.05(d)(II) “The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. i. Receiving or transmitting data over a network …iv. Storing and retrieving information in memory”, and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claims 7 and 15 also fail both Step 2A prong 2, thus the claims are directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more Therefore, Claims 7 and 15 do not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claim 8 and 16, they recite additional abstract recitations of “wherein the processor is further configured to: analyze the application program to determine at least one task during a running process of the application program” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can think about and observe, judge and evaluate an application program to analyze and determine a task is running. Further, configuring a node code which is merely writing data to a config file is merely insignificant extra solution data analysis and storage (see MPEP 2016.05(g)). Moreover, these insignificant extra-solution activities are WURC, see MPEP 2106.05(d)(II) “The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. i. Receiving or transmitting data over a network …iv. Storing and retrieving information in memory”. For the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claims 8 and 16 also fail both Step 2A prong 2, thus the claims are directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more Therefore, Claims 8 and 16 do not recite patent eligible subject matter under 35 U.S.C. § 101.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2, 4, 9, 10, 12, 17, 18, and 20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Qi et al. Pub. No. US 2017/0242733 A1 (hereafter Qi).
With regard to claim 1, Qi teaches a processing method, comprising (This embodiment provides a method for system call command batch processing. The method is applied to a multi-core system including multiple CPU cores, and the multiple CPU cores concurrently process system call commands. ¶ [0054]): obtaining a processing command issued by an application program; (Obtain multiple system call commands, where the multiple system call commands are commands that need to call a kernel function. ¶ [0055], When executing the task, the user program calls two system call commands; an open command and a read command. These two system call commands have a same task identifier, and the open command enters the kernel first and the read command enters the kernel later. ¶[0065])recognizing the processing command to obtain a recognition result; (Before performing batch processing on the system call commands, the apparatus for system call command batch processing classifies the multiple system call commands in the system call cache table according to the task identifiers of the system call commands. System call commands, of a same type have a same task identifier. ¶ [0061])and based on the recognition result, determining a target processing unit, such that the target unit is able to process the processing command, the target processing unit including at least one of processing units used to form a target processing module. (Send, according to a sequence of obtaining the multiple system call commands, system call commands of a same type to a same CPU core for processing. ¶ [0064], The processor 20 is further configured to obtain a call count of each system call command processed by a first CPU core, where the first CPU core is any CPU core of the multiple CPU cores, and the call count of each system call command is an execution count of each system call command in the multi-core system ¶[0142]).
With regard to claim 2, Qi teaches wherein: the target processing module includes a first target processing module; and the processing method further includes: in response to the target processing unit being determined to be a first target processing unit, using the first target processing unit to process the processing command, the first target processing unit belonging to the first target processing module. (Allocate a first CPU core to the system call command of the first type. ¶ [0087]. It may be ensured that the system call commands that have a same task identifier are distributed to a same CPU core for processing ¶ [0089]).
With regard to claim 4, Qi teaches wherein: the recognition result includes a type of the processing command; and determining the target processing unit based on the recognition result includes: determining a target address based on the type of the processing command, such that the target processing unit is called through the target address to process the processing command. (It can be learned from Table 3 that, the apparatus for system call command batch processing classifies the 12 system call commands in the system call cache cable according to task identifiers task ID. and allocates a same CPU core identifier to system call commands of a same type. ¶ [0112] Examiner notes a core identifier is a target address that identifies which core will process the command).
With regard to claim 9, Qi teaches a processing apparatus, comprising a memory storing a computer program and a processor coupled to the memory, when being executed by the processor, the computer program causing the processor to: (When the foregoing integrated module is implemented in a form of a software functional module, the integrated unit may be stored in a computer-readable storage medium. The software functional module is stored in a storage medium and includes several instructions for instructing a computer device (which may be a personal computer, a server, or a network device) to perform some of the steps of the methods described in the embodiments of the present disclosure.)obtain a processing command issued by an application program; (Obtain multiple system call commands, where the multiple system call commands are commands that need to call a kernel function. ¶ [0055], When executing the task, the user program calls two system call commands; an open command and a read command. These two system call commands have a same task identifier, and the open command enters the kernel first and the read command enters the kernel later. ¶[0065])recognize the processing command to obtain a recognition result; (Before performing batch processing on the system call commands, the apparatus for system call command batch processing classifies the multiple system call commands in the system call cache table according to the task identifiers of the system call commands. System call commands, of a same type have a same task identifier. ¶ [0061])and based on the recognition result, determine a target processing unit, such that the target unit is able to process the processing command, the target processing unit including at least one of processing units used to form a target processing module. (Send, according to a sequence of obtaining the multiple system call commands, system call commands of a same type to a same CPU core for processing. ¶ [0064], The processor 20 is further configured to obtain a call count of each system call command processed by a first CPU core, where the first CPU core is any CPU core of the multiple CPU cores, and the call count of each system call command is an execution count of each system call command in the multi-core system ¶[0142]).
With regard to claim 10, Qi teaches wherein: the target processing module includes a first target processing module; and the processor is further configured to: in response to the target processing unit being determined to be a first target processing unit, use the first target processing unit to process the processing command, the first target processing unit belonging to the first target processing module. (Allocate a first CPU core to the system call command of the first type. ¶ [0087]. It may be ensured that the system call commands that have a same task identifier are distributed to a same CPU core for processing ¶ [0089]).
With regard to claim 12, Qi teaches wherein: the recognition result includes a type of the processing command; and correspondingly, when determining the target processing unit based on the recognition result, the processor is further configured to: determine a target address based on the type of the processing command, such that the target processing unit is called through the target address to process the processing command. (It can be learned from Table 3 that, the apparatus for system call command batch processing classifies the 12 system call commands in the system call cache cable according to task identifiers task ID. and allocates a same CPU core identifier to system call commands of a same type. ¶ [0112] Examiner notes a core identifier is a target address that identifies which core will process the command).
With regard to claim 17, Qi teaches an electronic device, comprising a memory storing a computer program and a processor coupled to the memory, when being executed by the processor, the computer program causing the processor to: (The apparatus includes multiple CPU cores. FIG. 3 shows a schematic structural diagram of the apparatus, and the apparatus includes an obtaining module 10, a classification module 11, and a sending module 12. ¶ [0128] As shown in FIG. 6, the apparatus further includes: a memory 22, ¶ [0144]-[0145])obtain a processing command issued by an application program; (Obtain multiple system call commands, where the multiple system call commands are commands that need to call a kernel function. ¶ [0055], When executing the task, the user program calls two system call commands; an open command and a read command. These two system call commands have a same task identifier, and the open command enters the kernel first and the read command enters the kernel later. ¶[0065])recognize the processing command to obtain a recognition result; (Before performing batch processing on the system call commands, the apparatus for system call command batch processing classifies the multiple system call commands in the system call cache table according to the task identifiers of the system call commands. System call commands, of a same type have a same task identifier. ¶ [0061])and based on the recognition result, determine a target processing unit, such that the target unit is able to process the processing command, the target processing unit including at least one of processing units used to form a target processing module. (Send, according to a sequence of obtaining the multiple system call commands, system call commands of a same type to a same CPU core for processing. ¶ [0064], The processor 20 is further configured to obtain a call count of each system call command processed by a first CPU core, where the first CPU core is any CPU core of the multiple CPU cores, and the call count of each system call command is an execution count of each system call command in the multi-core system ¶[0142]).
With regard to claim 18, Qi teaches wherein: the target processing module includes a first target processing module; and the processor is further configured to: in response to the target processing unit being determined to be a first target processing unit, use the first target processing unit to process the processing command, the first target processing unit belonging to the first target processing module. (Allocate a first CPU core to the system call command of the first type. ¶ [0087]. It may be ensured that the system call commands that have a same task identifier are distributed to a same CPU core for processing ¶ [0089]).
With regard to claim 20, Qi teaches wherein: the recognition result includes a type of the processing command; and when determining the target processing unit based on the recognition result, the processor is further configured to: determine a target address based on the type of the processing command, such that the target processing unit is called through the target address to process the processing command. (It can be learned from Table 3 that, the apparatus for system call command batch processing classifies the 12 system call commands in the system call cache cable according to task identifiers task ID. and allocates a same CPU core identifier to system call commands of a same type. ¶ [0112] Examiner notes a core identifier is a target address that identifies which core will process the command).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 11, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Qi et al. Pub. No. US 2017/0242733 A1 (hereafter Qi) as applied to claims 1, 2, 4, 9, 10, 12, 17, 18 and 20 above and in further view of Zeng Pub. No. US 2022/0083375 A 1(hereafter Zeng).
With regard to claim 3, Qi teaches the method according to claim 1, wherein: the target processing module includes a first target processing module and a second target processing module; and the processing method further includes: in response to the target processing unit being determined to be a second target processing unit, sending the processing command to the second target processing unit through the first target processing module, such that the second target processing unit is able to process the processing command, the second target processing unit belonging to the second target processing module. (First, system call commands command1, command2, and command3 have a same task identifier task_ID1. Therefore, the three system call commands are of a same task type (referred to as task 1), and a first CPU core identifier coreid1 is allocated to the three system call commands. System call commands command4, command5, command6, and command7 have a same task identifier task_ID2. Therefore, the four system call commands are of a same task type (referred to as task 2), and a second CPU core identifier coreid2 is allocated to the four system call commands. ¶ [0113]).Qi does not specifically teach sending the processing command to the second target processing unit through the first target processing module.
However, in analogous art, Zeng teaches sending the processing command to the second target processing unit through the first target processing module. (In this way, the first task processing entity may receive a task processing request message. The task processing request message carries resource requirement information required by a to-be-processed task, and the resource requirement information includes a quantity of required resources and a resource type that are required by the to-be-processed task. When an idle resource included in the first task processing entity does not meet the resource requirement information, the first task processing entity determines m second task processing entities based on the entity status information table and the resource requirement information. A status of each of the m second task processing entities is the idle state, a quantity of idle resources corresponding to the resource type that are in each second task processing entity is greater than the quantity of required resources, and m is an integer greater than or equal to 1.The first task processing entity queries, from the m second task processing entities, a second task processing entity that includes an idle resource meeting the resource requirement information, and schedules the found second task processing entity to process the to-be-processed task. ¶ [0032] [0033])
It would have been obvious to a person have ordinary skill in the art prior to the effective filing date of the claimed invention to combine determining a first and second processing unit of Qi with the system and methods of Zeng resulting in a system that can send the processing command to the second target processing unit through the first target processing module, such that the second target processing unit is able to process the processing command.
A person having ordinary skill in the art would have motivated to make this combination, with a reasonable expectation of success for the purpose of further improving scheduling efficiency. (Zeng ¶ [0014])
With regard to claim 11, wherein: the target processing module includes a first target processing module and a second target processing module; and the processor is further configured to: in response to the target processing unit being determined to be a second target processing unit, send the processing command to the second target processing unit through the first target processing module, such that the second target processing unit is able to process the processing command, the second target processing unit belonging to the second target processing module. (First, system call commands command1, command2, and command3 have a same task identifier task_ID1. Therefore, the three system call commands are of a same task type (referred to as task 1), and a first CPU core identifier coreid1 is allocated to the three system call commands. System call commands command4, command5, command6, and command7 have a same task identifier task_ID2. Therefore, the four system call commands are of a same task type (referred to as task 2), and a second CPU core identifier coreid2 is allocated to the four system call commands. ¶ [0113]).Qi does not specifically teach sending the processing command to the second target processing unit through the first target processing module.
However, in analogous art, Zeng teaches send the processing command to the second target processing unit through the first target processing module. (In this way, the first task processing entity may receive a task processing request message. The task processing request message carries resource requirement information required by a to-be-processed task, and the resource requirement information includes a quantity of required resources and a resource type that are required by the to-be-processed task. When an idle resource included in the first task processing entity does not meet the resource requirement information, the first task processing entity determines m second task processing entities based on the entity status information table and the resource requirement information. A status of each of the m second task processing entities is the idle state, a quantity of idle resources corresponding to the resource type that are in each second task processing entity is greater than the quantity of required resources, and m is an integer greater than or equal to 1.The first task processing entity queries, from the m second task processing entities, a second task processing entity that includes an idle resource meeting the resource requirement information, and schedules the found second task processing entity to process the to-be-processed task. ¶ [0032] [0033])
It would have been obvious to a person have ordinary skill in the art prior to the effective filing date of the claimed invention to combine determining a first and second processing unit of Qi with the system and methods of Zeng resulting in a system that can send the processing command to the second target processing unit through the first target processing module, such that the second target processing unit is able to process the processing command.
A person having ordinary skill in the art would have motivated to make this combination, with a reasonable expectation of success for the purpose of further improving scheduling efficiency. (Zeng ¶ [0014])
With regard to claim 19, wherein: the target processing module includes a first target processing module and a second target processing module; and the processor is further configured to: in response to the target processing unit being determined to be a second target processing unit, send the processing command to the second target processing unit through the first target processing module, such that the second target processing unit is able to process the processing command, the second target processing unit belonging to the second target processing module. (First, system call commands command1, command2, and command3 have a same task identifier task_ID1. Therefore, the three system call commands are of a same task type (referred to as task 1), and a first CPU core identifier coreid1 is allocated to the three system call commands. System call commands command4, command5, command6, and command7 have a same task identifier task_ID2. Therefore, the four system call commands are of a same task type (referred to as task 2), and a second CPU core identifier coreid2 is allocated to the four system call commands. ¶ [0113]).Qi does not specifically teach sending the processing command to the second target processing unit through the first target processing module.
However, in analogous art, Zeng teaches send the processing command to the second target processing unit through the first target processing module. (In this way, the first task processing entity may receive a task processing request message. The task processing request message carries resource requirement information required by a to-be-processed task, and the resource requirement information includes a quantity of required resources and a resource type that are required by the to-be-processed task. When an idle resource included in the first task processing entity does not meet the resource requirement information, the first task processing entity determines m second task processing entities based on the entity status information table and the resource requirement information. A status of each of the m second task processing entities is the idle state, a quantity of idle resources corresponding to the resource type that are in each second task processing entity is greater than the quantity of required resources, and m is an integer greater than or equal to 1.The first task processing entity queries, from the m second task processing entities, a second task processing entity that includes an idle resource meeting the resource requirement information, and schedules the found second task processing entity to process the to-be-processed task. ¶ [0032] [0033])
It would have been obvious to a person have ordinary skill in the art prior to the effective filing date of the claimed invention to combine determining a first and second processing unit of Qi with the system and methods of Zeng resulting in a system that can send the processing command to the second target processing unit through the first target processing module, such that the second target processing unit is able to process the processing command.
A person having ordinary skill in the art would have motivated to make this combination, with a reasonable expectation of success for the purpose of further improving scheduling efficiency. (Zeng ¶ [0014])
Claims 5, 6, 13, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Qi et al. Pub. No. US 2017/0242733 A1 (hereafter Qi) as applied to claims 1, 2, 4, 9, 10, 12, 17, 18 and 20 above and in further view of Park et al Pub. No. US11194510B2 (hereafter Park).
With regard to claim 5, Qi teaches wherein determining the target address based on the type of the processing command, such that the target processing unit is called through the target address to process the processing command comprises: based on the type of the processing command, determining the target address; (It can be learned from Table 3 that, the apparatus for system call command batch processing classifies the 12 system call commands in the system call cache cable according to task identifiers task ID. and allocates a same CPU core identifier to system call commands of a same type. ¶ [0112] Examiner notes a core identifier is a target address that identifies which core will process the command).Qi does not teach and writing the processing command and the target address into a buffer area, such that the target processing unit is driven based on the target address to respond to the processing command.However, in analogous art, Park teaches writing the processing command and the target address into a buffer area, such that the target processing unit is driven based on the target address to respond to the processing command. (When the storage device 100 operates in a cache-on mode, the data buffer included in the device controller 110 may be operated as a cache memory. Col 4 lines 62 – 65. The scheduler 11 may determine an execution order of the plurality of tasks so that tasks in the first mode may be executed prior to the tasks in the second mode. Data of the tasks in the first mode may be stored in the data buffer, and when the data in the program unit are stored in the data buffer, subsequently, the scheduler 11 may execute the tasks in the second mode. In an embodiment of the inventive concept, the scheduler 11 may check an address to be accessed by the tasks from the command argument of the tasks and may determine an execution order of the plurality of tasks so that the tasks to have access to the same address region may be consecutively executed. Col 5 lines 8 - 21)It would have been obvious to a person have ordinary skill in the art prior to the effective filing date of the claimed invention to combine the methods of Qi of determining the target address based on the type of the processing command, such that the target processing unit is called through the target address to process the processing command comprises: based on the type of the processing command, determining the target address with the methods of Park resulting in a system that can write the processing command and the target address into a buffer area.
A person having ordinary skill in the art would have motivated to make this combination, with a reasonable expectation of success for the purpose of an improvement in computer functionality as operations of the same mode may tend to utilize the same or similar resources that, for example, may be loaded into storage, e.g., a cache memory, etc., and can reduce the time of execution of some operations, and provide a resultant savings in power, over a conventional selection and execution of tasks from a task queue. (Col 7 lines 63 – 67 Col 8 lines 1 -3)
With regard to claim 6, Qi teaches wherein: the recognition result includes a type of the processing command; and determining the target processing unit based on the recognition result includes: (Send, according to a sequence of obtaining the multiple system call commands, system call commands of a same type to a same CPU core for processing. ¶ [0064]).Qi does not teach based on the type of the processing command, determining a target storage area from multiple storage areas on a storage module, different storage areas from the multiple storage areas correspond to different processing units; and writing the processing command into the target storage area, such that the target processing unit corresponding to the target storage area is able to process the processing command.However, in analogous art, Park teaches based on the type of the processing command, determining a target storage area from multiple storage areas on a storage module, different storage areas from the multiple storage areas correspond to different processing units; and writing the processing command into the target storage area, such that the target processing unit corresponding to the target storage area is able to process the processing command. (The memory 20 a may include a data buffer 23, and the task queue 21 and the mapping table 22 may be loaded into the memory 20 a. For example, one region (or a memory chip) of the memory 20 a may be configured to operate as the data buffer 23, and the task queue 21 and the mapping table 22 may be loaded into another region (or another memory chip) of the memory 20 a. The task queue 21 may include a plurality of registers, and each of the plurality of registers may include task information about each of the plurality of tasks. Tasks according to the commands CMD received from the host 200, for example, task-setting commands may be sequentially stored in the task queue 21. However, the tasks are not executed in a stored order, and the queue manager 72 may determine an execution order of the tasks. In an embodiment of the inventive concept, the task manager 32 may inform to the host 200 that a predetermined task is in a ready state according to the determined execution order. The mapping table 22 may store mapping information about a logic address received from the host 200 and a physical address of the non-volatile memory 120. Col 8 line 40 - 60).It would have been obvious to a person have ordinary skill in the art prior to the effective filing date of the claimed invention to combine the methods of Qi that the recognition result includes a type of the processing command; and determining the target processing unit based on the recognition result includes with the methods of Park resulting in a system that based on the type of the processing command, determining a target storage area from multiple storage areas on a storage module, different storage areas from the multiple storage areas correspond to different processing units; and writing the processing command into the target storage area, such that the target processing unit corresponding to the target storage area is able to process the processing command.
A person having ordinary skill in the art would have motivated to make this combination, with a reasonable expectation of success for the purpose of tasks according to the plurality of received commands CMD may be queued in the task queue 21. Thus, the storage device 100 may perform an asynchronous input/output operation of receiving new commands CMD while executing tasks according to the previously-received commands CMD. Thus, increased operating speeds of the storage device 100 may be realized. (Col 4 lines 12 - 19).
With regard to claim 13, Qi teaches wherein when determining the target address based on the type of the processing command, such that the target processing unit is called through the target address to process the processing command, the processor is further configured to: based on the type of the processing command, determine the target address; (It can be learned from Table 3 that, the apparatus for system call command batch processing classifies the 12 system call commands in the system call cache cable according to task identifiers task ID. and allocates a same CPU core identifier to system call commands of a same type. ¶ [0112] Examiner notes a core identifier is a target address that identifies which core will process the command).Qi does not teach and write the processing command and the target address into a buffer area, such that the target processing unit is driven based on the target address to respond to the processing command.However, in analogous art, Park teaches and write the processing command and the target address into a buffer area, such that the target processing unit is driven based on the target address to respond to the processing command. (When the storage device 100 operates in a cache-on mode, the data buffer included in the device controller 110 may be operated as a cache memory. Col 4 lines 62 – 65. The scheduler 11 may determine an execution order of the plurality of tasks so that tasks in the first mode may be executed prior to the tasks in the second mode. Data of the tasks in the first mode may be stored in the data buffer, and when the data in the program unit are stored in the data buffer, subsequently, the scheduler 11 may execute the tasks in the second mode. In an embodiment of the inventive concept, the scheduler 11 may check an address to be accessed by the tasks from the command argument of the tasks and may determine an execution order of the plurality of tasks so that the tasks to have access to the same address region may be consecutively executed. Col 5 lines 8 - 21)It would have been obvious to a person have ordinary skill in the art prior to the effective filing date of the claimed invention to combine the methods of Qi of determining the target address based on the type of the processing command, such that the target processing unit is called through the target address to process the processing command comprises: based on the type of the processing command, determining the target address with the methods of Park resulting in a system that can write the processing command and the target address into a buffer area.
A person having ordinary skill in the art would have motivated to make this combination, with a reasonable expectation of success for the purpose of an improvement in computer functionality as operations of the same mode may tend to utilize the same or similar resources that, for example, may be loaded into storage, e.g., a cache memory, etc., and can reduce the time of execution of some operations, and provide a resultant savings in power, over a conventional selection and execution of tasks from a task queue. (Col 7 lines 63 – 67 Col 8 lines 1 -3)
With regard to claim 14, Qi teaches wherein: the recognition result includes a type of the processing command; and when determining the target processing unit based on the recognition result, the processor is further configured to: (Send, according to a sequence of obtaining the multiple system call commands, system call commands of a same type to a same CPU core for processing. ¶ [0064]).Qi does not teach based on the type of the processing command, determine a target storage area from multiple storage areas on a storage module, different storage areas from the multiple storage areas correspond to different processing units; and write the processing command into the target storage area, such that the target processing unit corresponding to the target storage area is able to process the processing command.However, in analogous art, Park teaches teach based on the type of the processing command, determine a target storage area from multiple storage areas on a storage module, different storage areas from the multiple storage areas correspond to different processing units; and write the processing command into the target storage area, such that the target processing unit corresponding to the target storage area is able to process the processing command. (The memory 20 a may include a data buffer 23, and the task queue 21 and the mapping table 22 may be loaded into the memory 20 a. For example, one region (or a memory chip) of the memory 20 a may be configured to operate as the data buffer 23, and the task queue 21 and the mapping table 22 may be loaded into another region (or another memory chip) of the memory 20 a. The task queue 21 may include a plurality of registers, and each of the plurality of registers may include task information about each of the plurality of tasks. Tasks according to the commands CMD received from the host 200, for example, task-setting commands may be sequentially stored in the task queue 21. However, the tasks are not executed in a stored order, and the queue manager 72 may determine an execution order of the tasks. In an embodiment of the inventive concept, the task manager 32 may inform to the host 200 that a predetermined task is in a ready state according to the determined execution order. The mapping table 22 may store mapping information about a logic address received from the host 200 and a physical address of the non-volatile memory 120. Col 8 line 40 - 60).It would have been obvious to a person have ordinary skill in the art prior to the effective filing date of the claimed invention to combine the methods of Qi that the recognition result includes a type of the processing command; and determining the target processing unit based on the recognition result includes with the methods of Park resulting in a system that based on the type of the processing command, determining a target storage area from multiple storage areas on a storage module, different storage areas from the multiple storage areas correspond to different processing units; and writing the processing command into the target storage area, such that the target processing unit corresponding to the target storage area is able to process the processing command.
A person having ordinary skill in the art would have motivated to make this combination, with a reasonable expectation of success for the purpose of tasks according to the plurality of received commands CMD may be queued in the task queue 21. Thus, the storage device 100 may perform an asynchronous input/output operation of receiving new commands CMD while executing tasks according to the previously-received commands CMD. Thus, increased operating speeds of the storage device 100 may be realized. (Col 4 lines 12 - 19).
Claim 7, 8, 15 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Qi et al. Pub. No. US 2017/0242733 A1 (hereafter Qi) as applied to claims 1, 2, 4, 9, 10, 12, 17, 18 and 20 above and in further view of Gu Pub. No. US20240160474A1 (hereafter Gu).
With regard to claim 7, Qi teaches the method of claim 1. Qi does not teach wherein obtaining the processing command issued by the application program comprises: obtaining a node code during a running process of an application program; and based on the node code and a preset mapping relationship, determining the processing command, the preset mapping relationship including mapping relationships between multiple node codes and multiple processing commands. However, in analogous art, Gu teaches wherein obtaining the processing command issued by the application program comprises: obtaining a node code during a running process of an application program; and based on the node code and a preset mapping relationship, determining the processing command, the preset mapping relationship including mapping relationships between multiple node codes and multiple processing commands. (As shown in FIG. 2, the above-mentioned multi-core processor task scheduling method includes following steps. Step S202, acquiring a target task to be executed; Step S204, selecting, based on attribute information of the target task, a target processor from a multi-core processor, wherein the attribute information includes binding relationship information and priority information, the binding relationship information is used for describing whether the target task needs to be run on a processor having a binding relationship, and the priority information is used for describing a priority of the target task; Step S206, scheduling the target task to the target processor; and Step S208, running the target task on the target processor. ¶ [0039]- [0042] Examiner notes a node code is merely an identifier included in attribute information that includes binding relationship information for determining the processing command.)It would have been obvious to a person have ordinary skill in the art prior to the effective filing date of the claimed invention to combine the methods of Qi to obtain a processing command, recognition result or type, and determining a target processing unit with the methods of Gu resulting in a system that can obtain a node code during a running process of an application program; and based on the node code and a preset mapping relationship, determining the processing command, the preset mapping relationship including mapping relationships between multiple node codes and multiple processing commands.
A person having ordinary skill in the art would have motivated to make this combination, with a reasonable expectation of success for the purpose of accurately determining the target processor for running the task to be executed, thereby achieving the technical effect of reducing the number of times of task scheduling of the multi-core processor and improving the overall performance of the system, and then thereby solving the technical problem that the existing multi-core scheduling algorithms cannot accurately determine a target processor for running a task to be executed. [0044].
With regard to claim 8, Qi teaches the method of claim 1. Qi does not teach further comprising: analyzing the application program to determine at least one task during a running process of the application program; and configuring one node code corresponding to each task of the at least one task. However, in analogous art, Gu teaches further comprising: analyzing the application program to determine at least one task during a running process of the application program; and configuring one node code corresponding to each task of the at least one task. (Inter-processor interrupt: refers to a procedure in which the processor that is currently running a task, in a multi-core processor, sends an interrupt signal to a target processor, to trigger the execution of task schedule on the target processor. ¶0024] Still as shown in FIG. 3, when the priority of the target task is higher than the priority of the current task, it is checked whether the first processor is a processor currently scheduling the target task. If the first processor is not the processor currently scheduling the target task, an inter-processor interrupt is sent to the first processor by the processor currently scheduling the target task, to determine the first processor as the target processor, and a scheduler is executed on the first processor. ¶[0059])It would have been obvious to a person have ordinary skill in the art prior to the effective filing date of the claimed invention to combine the methods of Qi to obtain a processing command, recognition result or type, and determining a target processing unit with the methods of Gu resulting in a system that can analyze the application program to determine at least one task during a running process of the application program; and configuring one node code corresponding to each task of the at least one task.
A person having ordinary skill in the art would have motivated to make this combination, with a reasonable expectation of success for the purpose of significantly improve the affinity of the target task to the target processor in the multi-core processor. [0067]
With regard to claim 15, Qi teaches the method of claim 1. Qi does not teach wherein when obtaining the processing command issued by the application program, the processor is further configured to: obtain a node code during a running process of an application program; and based on the node code and a preset mapping relationship, determine the processing command, the preset mapping relationship including mapping relationships between multiple node codes and multiple processing commands.However, in analogous art, Gu teaches wherein when obtaining the processing command issued by the application program, the processor is further configured to: obtain a node code during a running process of an application program; and based on the node code and a preset mapping relationship, determine the processing command, the preset mapping relationship including mapping relationships between multiple node codes and multiple processing commands. (As shown in FIG. 2, the above-mentioned multi-core processor task scheduling method includes following steps. Step S202, acquiring a target task to be executed; Step S204, selecting, based on attribute information of the target task, a target processor from a multi-core processor, wherein the attribute information includes binding relationship information and priority information, the binding relationship information is used for describing whether the target task needs to be run on a processor having a binding relationship, and the priority information is used for describing a priority of the target task; Step S206, scheduling the target task to the target processor; and Step S208, running the target task on the target processor. ¶ [0039]- [0042] Examiner notes a node code is merely an identifier included in attribute information that includes binding relationship information for determining the processing command.)It would have been obvious to a person have ordinary skill in the art prior to the effective filing date of the claimed invention to combine the methods of Qi to obtain a processing command, recognition result or type, and determining a target processing unit with the methods of Gu resulting in a system that can obtain a node code during a running process of an application program; and based on the node code and a preset mapping relationship, determining the processing command, the preset mapping relationship including mapping relationships between multiple node codes and multiple processing commands.
A person having ordinary skill in the art would have motivated to make this combination, with a reasonable expectation of success for the purpose of accurately determining the target processor for running the task to be executed, thereby achieving the technical effect of reducing the number of times of task scheduling of the multi-core processor and improving the overall performance of the system, and then thereby solving the technical problem that the existing multi-core scheduling algorithms cannot accurately determine a target processor for running a task to be executed. [0044].
With regard to claim 16, Qi teaches the method of claim 1. Qi does not teach wherein the processor is further configured to: analyze the application program to determine at least one task during a running process of the application program; and configure one node code corresponding to each task of the at least one task.
However, in analogous art, Gu teaches wherein the processor is further configured to: analyze the application program to determine at least one task during a running process of the application program; and configure one node code corresponding to each task of the at least one task. (Inter-processor interrupt: refers to a procedure in which the processor that is currently running a task, in a multi-core processor, sends an interrupt signal to a target processor, to trigger the execution of task schedule on the target processor. ¶0024] Still as shown in FIG. 3, when the priority of the target task is higher than the priority of the current task, it is checked whether the first processor is a processor currently scheduling the target task. If the first processor is not the processor currently scheduling the target task, an inter-processor interrupt is sent to the first processor by the processor currently scheduling the target task, to determine the first processor as the target processor, and a scheduler is executed on the first processor. ¶[0059])It would have been obvious to a person have ordinary skill in the art prior to the effective filing date of the claimed invention to combine the methods of Qi to obtain a processing command, recognition result or type, and determining a target processing unit with the methods of Gu resulting in a system that can analyze the application program to determine at least one task during a running process of the application program; and configuring one node code corresponding to each task of the at least one task.
A person having ordinary skill in the art would have motivated to make this combination, with a reasonable expectation of success for the purpose of significantly improve the affinity of the target task to the target processor in the multi-core processor. [0067]
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Todd Jeffrey Johnson whose telephone number is (571)270-0929. The examiner can normally be reached M-F, 7:30am to 5pm ET.
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/T.J.J./Examiner, Art Unit 2197
/BRADLEY A TEETS/Supervisory Patent Examiner, Art Unit 2197
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