Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-15 are presented for examination.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
4. Claims 1-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by CHAO et al hereafter CHAO (US pat. app. pub. 20240078151).
5. As per claim 1, CHAO teaches a coupling and chaining bridge circuit, comprising: a first coupling to a volatile memory; a second coupling to a cryptographic circuit; a third coupling to a processor (fig. 1, and paragraphs: 41, wherein it emphasizes a memory controller acts as coupling and chaining bridge circuit which establishes connection with memory, crypto logic module); wherein the coupling and chaining bridge circuit is configured to: perform a coupling operation between the volatile memory and the cryptographic circuit in response to a write access request received from a processor for writing one or more data values to the volatile memory, wherein the write access request includes an address for storing in the volatile memory (paragraphs: 8, wherein it elaborates the memory controller perform a write request into the memory instructed by the crypto module by writing data in a storage address of the memory); wherein the coupling operation comprises: writing the one or more data values to the volatile memory; and for each of the one or more data values, generating a first write access request, in the cryptographic circuit, for the data value, and generating a second write access request, in the cryptographic circuit, for the storage address (abstract, and paragraphs: 18, and 55, wherein it illustrates that the data writing request comprises with a write the data in the memory and the storage address of the memory); and operate a verification operation between the cryptographic circuit and the volatile memory, in response to a read access request received from the processor, of a verification value stored in the cryptographic circuit (paragraphs: 15-16, and 19, wherein it describes that when the read request is received then the memory controller runs a verification operation by a verification value of crypto module); wherein the verification operation comprises: comparing the verification value with a reference value stored in the coupling and chaining bridge circuit (paragraphs: 17, and 52, wherein it discusses that the verification will be accomplished by comparing the MAC value to the prestored standard MAC value (reference value)); and authorizing access to the volatile memory only for reading in response to a result of the comparing (paragraphs: 62-66, wherein it confers that if the comparison result is positive then it will authorize to access the memory for reading the data).
6. As per claim 2, CHAO teaches the coupling and chaining bridge circuit, further configured to return a default value to the processor in response to the read access request of the verification value received from the processor (paragraphs: 14-16).
7. As per claim 3, CHAO teaches the coupling and chaining bridge circuit, further configured to delete the content of the volatile memory when the result of the comparing indicates that the verification value does not correspond to the reference value (paragraphs: 31, and 37-38).
8. As per claim 4, CHAO teaches the coupling and chaining bridge circuit, further comprising a register programmable by the processor allowing the configuration of the coupling and chaining bridge circuit (paragraphs: 44-45, and 50).
9. As per claim 5, CHAO teaches the coupling and chaining bridge circuit, further comprising a second register configured to receive the reference value from the processor (paragraphs: 9, and 12-13).
10. As per claim 6, CHAO teaches an electronic device, comprising: the coupling and chaining bridge circuit; the cryptographic circuit coupled to the coupling and chaining bridge circuit via a first bus at the second coupling; the volatile memory coupled to the coupling and chaining bridge circuit via a second bus at the first coupling; and the processor coupled to the coupling and chaining bridge circuit via a system bus and a third bus at the third coupling (fig. 1, and paragraphs: 41-43).
11. As per claim 7, CHAO teaches the electronic device, wherein the cryptographic circuit is configured to generate the verification value by performing one or more cryptographic operations on each data value and storage address and based on a secret key, wherein the secret key is accessible only in read-only mode on the cryptographic circuit (paragraphs: 17-19).
12. As per claim 8, CHAO teaches the electronic device, further comprising a second cryptographic circuit coupled to the coupling and chaining bridge circuit and comprising the volatile memory (paragraphs: 41-43).
13. As per claim 9, CHAO teaches a process, comprising: performing a coupling operation through a coupling and chaining bridge circuit of an electronic device, based on the reception, by the coupling and chaining bridge circuit, of a write access request, from a processor of the device, for writing one or more data values in a volatile memory of the device, each data value being associated with a storage address in the volatile memory (paragraphs: 8, and 18, wherein it elaborates the memory controller perform a write request into the memory instructed by the crypto module by writing data in a storage address of the memory); wherein the coupling operation comprises: intercepting the write access request by the coupling and chaining bridge circuit; for each of the one or more data values, generating a first write access request of the data value and a second write access request of the associated storage address in a first cryptographic circuit; and for each of the one or more data values, writing to the volatile memory (abstract, and paragraphs: 18, and 55, wherein it illustrates that the data writing request comprises with a write the data in the memory and the storage address of the memory); executing a verification operation, by the coupling and chaining bridge circuit, based on the reception, by the coupling and chaining bridge circuit, of an access request, from the processor, to read a verification value stored in the first cryptographic circuit (paragraphs: 15-16, and 19, wherein it describes that when the read request is received then the memory controller runs a verification operation by a verification value of crypto module); wherein the verification operation comprises: reading the verification value by the coupling and chaining bridge circuit; comparing the verification value with a reference value that is stored in the coupling and chaining bridge circuit (paragraphs: 17, and 52, wherein it discusses that the verification will be accomplished by comparing the MAC value to the prestored standard MAC value (reference value)); and authorizing access, only for reading, to the content of the volatile memory, based on the comparing (paragraphs: 62-66, wherein it confers that if the comparison result is positive then it will authorize to access the memory for reading the data).
14. As per claim 10, CHAO teaches the process, further comprising returning by the coupling and chaining bridge circuit a default value to the processor in response to the read access request of the verification value (paragraphs: 14-16).
15. As per claim 11, CHAO teaches the process, further comprising generating by the first cryptographic circuit the verification value by applying, to each received data value and to each storage address, one or more cryptographic operations, the one or more cryptographic operations being further performed based on a secret key (paragraphs: 8-9, and 12-13).
16. As per claim 12, CHAO teaches the process, wherein the one or more cryptographic operations are hashing operations and/or operations of a cryptographic algorithm of Advanced Encryption Standard-Galois/Counter Mode (AES-GCM) type or of Advanced Encryption Standard-Counter with cipher block chaining message authentication code (AES-CCM) type comprising the generation of said verification value (paragraphs: 41-43).
17. As per claim 13, CHAO teaches the process, further comprising transmitting by the processor the reference value to the coupling and chaining bridge circuit before transmitting the write access request (paragraphs: 39-40).
18. As per claim 14, CHAO teaches the process, further comprising suppressing content of the volatile memory, controlled by the coupling and chaining bridge circuit, when said comparing determines that the verification value does not correspond to the reference value (paragraphs: 17-19).
19. As per claim 15, CHAO teaches the process, further comprising, before the coupling operation, writing by the processor the reference value in a register of the coupling and chaining bridge circuit (paragraphs: 31, and 37-38).
Citation of References
20. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following references are cited but not been replied upon for this office action:
KIM et al (US pat. app. Pub. 20220262448): discusses a memory device includes a data storage circuit configured to store, when a write operation is performed, a first internal write data and a second internal write data in a memory cell array which is accessed by an internal address, and output, when a read operation is performed, data stored in a memory cell array which is accessed by the internal address, as internal read data; and a flag generation circuit configured to generate a flag for controlling generation of a data strobe signal, based on the internal read data.
LI et al (US pat. App. Pub. 20230317137): elaborates that a test platform, and the adjustment circuit includes a duty cycle adjuster (DCA) circuit. The method includes: receiving written data at a specified storage address based on a first read/write clock signal; and receiving read data from the specified storage address based on a second read/write clock signal, and generating a test result of the DCA circuit based on the written data and the read data; wherein the DCA circuit is configured to adjust a first initial read/write clock signal to generate the first read/write clock signal and/or adjust a second initial read/write clock signal to generate the second read/write clock signal, and a duty cycle of the first initial read/write clock signal and/or a duty cycle of the second initial read/write clock signal have/has a first deviation.
Conclusion
21. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD W REZA whose telephone number is (571)272-6590. The examiner can normally be reached on Monday-Friday 8:30-5:30 ET.
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/MOHAMMAD W REZA/Primary Examiner, Art Unit 2407