DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 8, 11, 13, 14, 17, 19, 37 and 39 are objected to because of the following informalities: all first instances of “ZVS” from a parent claim to its dependent claims should be changed to “zero voltage soft switching” as defined by [0035] of Applicant’s Specification. Appropriate correction is required.
Election/Restrictions
Upon further review, Examiner has determined that a restriction is not required for all claims other than claim 28, which teaches away from the isolation barrier required by the elected Species (Figure 11). Thus, all claims have been examined on the merits except for claim 28. Claim 28 is considered withdrawn.
Drawings
The drawings are not of sufficient quality to permit examination. Accordingly, replacement drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to this Office action. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action.
Applicant is given a shortened statutory period of TWO (2) MONTHS to submit new drawings in compliance with 37 CFR 1.81. Extensions of time may be obtained under the provisions of 37 CFR 1.136(a) but in no case can any extension carry the date for reply to this letter beyond the maximum period of SIX MONTHS set by statute (35 U.S.C. 133). Failure to timely submit replacement drawing sheets will result in ABANDONMENT of the application.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-46 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
All of the claims require “a pulse width modulated signal having a set logic state and a reset logic state” and “a switch driving signal having a logic state including a driving set logic state and a driving reset logic state”. Claim 2 states “reset the switch driving signal to the driving reset logic state”. Claim 4 states “set the switch driving signal at the driving set logic state”.
It is unclear whether “set” and “reset” as claimed necessitates the use of set-reset digital logic (e.g., use of a set-reset latch) or if this merely requires logic high/logic low signal states. For the purposes of examination, examiner will interpret these limitations to only require logic high and logic low states.
Where applicant acts as his or her own lexicographer to specifically define a term of a claim contrary to its ordinary meaning, the written description must clearly redefine the claim term and set forth the uncommon definition so as to put one reasonably skilled in the art on notice that the applicant intended to so redefine that claim term. Process Control Corp. v. HydReclaim Corp., 190 F.3d 1350, 1357, 52 USPQ2d 1029, 1033 (Fed. Cir. 1999). The terms “set” and “reset” as used in the claims are indefinite because the specification does not clearly redefine the term. Applicant’s Specification in [0023]-[0024] provides examples but does not explicitly provide a definition for said terms.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-7, 9-13, 15-27, 29-38 and 40-46 is/are rejected under 35 U.S.C. 103 as being unpatentable over Terashima (US 2018/0367023) in view of Kandah et al (EP 3223416 B1).
For claim 1, Terashima teaches a gate driving unit (all of Figure 2 except for 1i) comprising:
a first terminal (input to 31 which receives DSG) adapted to be configured as a control terminal to receive a pulse width modulated signal (DSG) having a set logic state (logic high) and a reset logic state (logic low); and
a third terminal (output of 31) adapted to be configured as an output terminal of the gate driving unit for providing a switch driving signal having a logic state including a driving set logic state and a driving reset logic state (as understood by examination of Figure 2);
wherein the gate driving unit is configured to detect or monitor a current signal flowing through the third terminal (via 18 and 32) and further configured to control the logic state of the switch driving signal based on the pulse width modulated signal and the current signal ([0028], [0030]).
Terashima fails to distinctly disclose:
a second terminal adapted to be configured as a reference ground terminal.
Terashima fails to teach the details of the gate driver circuit 31 but does teach said gate driver 31 drives an IGBT (1i) based on a PWM signal (DSG) and a protection signal (Spc) such that “while the protection factor continuation signal Sps is a high level, the gate control circuit 31 stops outputting the operation signal DSG to the gate of the IGBT 1i.” ([0030]).
Kandah teaches a gate driver (131, 133, 230, 233 and 235, Figure 3) having a first switch (301) for providing a logic high signal (VCCH1) to the gate of an IGBT (121), a second switch (303) for providing a logic low signal (Vneg) to the gate of the IGBT and a third switch (305) “to strongly keep IGBT 121 turned off when desired” ([0032]).
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to use Kandah’s gate driver to implement Terashima’s gate driver 31 since it merely relates to a specific-for-broad substitution, i.e., any person having ordinary skill in the art would have easily recognized that the generic box labeled "gate driver" in Terashima’s Fig. 2 suggests that any well-known level shifter circuitry can/should be used to implement this generic box.
Furthermore, the particular known technique was recognized as part of the ordinary capabilities of one skilled in the art.
The combination of Terashima and Kandah teaches a second terminal adapted to be configured as a reference terminal (Vneg) but fails to teach the reference terminal being ground.
However, it would have been obvious to one having ordinary skill in the art at the time of invention to use ground potential instead of a negative voltage since the reference potential used by the gate driver can be set to any value desired within a working range. Thus, creating the claimed relationships would only involve routine "design optimization", which has been held to be within the ordinary capabilities of a person having ordinary skill in the art. Applicant should note In re Aller, 105 USPQ 233 (1955) where it was held that optimizing particular values is obvious to a person of ordinary skill in the art (who would easily be able to set different values within the range of possible values in order to arrive at the best value by simple experimentation). Note also In re Bosch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980) where it was held that discovering an optimum value of a result effective variable involves only routine skill in the art.
For claim 2, the modified combination of Terashima and Kandah teaches the limitations of claim 1 and Terashima further teaches:
wherein the gate driving unit is further configured to reset the switch driving signal at the driving reset logic state in response to the pulse width modulated signal's changing from the set logic state to the reset logic state ([0030] and as understood by examination of Figure 2).
For claim 3, the modified combination of Terashima and Kandah teaches the limitations of claim 1 and Terashima further teaches:
the gate driving unit is further configured to determine whether a first detection event (no overcurrent detected) has been identified (via 32, [0036]) during a first detection time window (a window large enough to detect an overcurrent event, as understood by examination of Figure 2) based on the current signal (as understood by examination of Figure 2), and wherein the first detection time window has a first window width (inherent of all time windows) and is enabled during the switch driving signal is at the driving reset logic state (capable of, as understood by the combination of references as cited above).
For claim 4, the modified combination of Terashima and Kandah teaches the limitations of claim 3 and Terashima further teaches:
the gate driving unit is further configured to set the switch driving signal at the driving set logic state (logic high) on condition that the first detection event has been identified during the first detection time window and the pulse width modulated signal is at the set logic state (as understood by the combination of references as cited above).
For claim 5, the modified combination of Terashima and Kandah teaches the limitations of claim 3 and Terashima further teaches:
the gate driving unit is further configured to determine that the first detection event has been identified during the first detection time window if the current signal rises to or above a first predetermined threshold current value (a value higher than the current corresponding to Vth1) and then falls back to or below a second predetermined threshold current value (current corresponding to Vth1) during the first detection time window (detection during the period in which the current is below Vth1).
For claim 6, the modified combination of Terashima and Kandah teaches the limitations of claim 3 and Terashima further teaches:
the gate driving unit is further configured to enable or set the first detection time window when a first predetermined leading-edge blanking time (minimum time required for 1i to reach a normal operating current after 1i is off) has elapsed since a moment when the switch driving signal is reset from the driving set logic state to the driving reset logic state (as understood by examination of Figure 2).
For claim 7, the modified combination of Terashima and Kandah teaches the limitations of claim 3 and Terashima further teaches:
the gate driving unit is further configured to enable a maximum detection time period in response to the pulse width modulated signal's changing from the reset logic state to the set logic state (minimum time required for 1i to reach a normal operating current after 1i is off), and to force the switch driving signal to be set at the driving set logic state if the first detection event has not been identified until the maximum detection time period expires (capable of, as understood by the combination of references).
For claim 9, the modified combination of Terashima and Kandah teaches the limitations of claim 1 and Terashima further teaches:
a reporting terminal (ta), configured to provide a reporting signal (ALM, Figure 2)
For claim 10, the modified combination of Terashima and Kandah teaches the limitations of claim 9 and Terashima further teaches:
the gate driving unit is further configured to set the reporting signal to a first report status during normal operation ([0054]).
For claim 11, the modified combination of Terashima and Kandah teaches the limitations of claim 10 and Terashima further teaches:
the gate driving unit is further configured to set the reporting signal to a second report status (via 34) when a situation of substantially non-ZVS is identified (e.g., overheating, [0028]).
For claim 12, the modified combination of Terashima and Kandah teaches the limitations of claim 10 and Terashima further teaches:
the gate driving unit is further configured to set the reporting signal to a third report status when a short circuit event is detected ([0087]).
For claim 13, the modified combination of Terashima and Kandah teaches the limitations of claim 10 and Terashima further teaches:
the gate driving unit is further configured to set the reporting signal to a second report status when a situation of substantially non-ZVS is identified and to set the reporting signal to a third report status when a short circuit event is detected (as discussed in the rejection of claims 11-12 above), and wherein the first report status, the second report status and the third report status are different from each other (different pulse lengths based on 35a-c, as understood by examination of Figure 2).
For claim 15, the modified combination of Terashima and Kandah teaches the limitations of claim 12 and Terashima further teaches:
the gate driving unit is further configured to determine that the short circuit event is detected if the current signal is flowing into the third terminal for a predetermined short circuit detection time during the switch driving signal is at the driving set logic state (as understood by examination of Figure 2 and [0087]).
For claim 16, the modified combination of Terashima and Kandah teaches the limitations of claim 10 and Terashima further teaches:
a temperature sensing input terminal, adapted to be configured to detect a temperature reading signal (inverting input to CP3); and
wherein the gate driving unit is further configured to provide a temperature report signal having a pulse width modulated by the temperature reading signal (Soh); and wherein the gate driving unit is further configured to set the reporting signal to a first report status embodied as the temperature report signal during normal operation (as understood by examination of Figure 2).
For claim 17, the modified combination of Terashima and Kandah teaches the limitations of claim 12 and Terashima further teaches:
the gate driving unit is further configured to set the reporting signal to a second report status (via 33) when the gate driving unit has identified a situation of substantially non-ZVS (undervoltage, [0028]), the second report status being different from the first report status (different pulse widths via 35).
For claim 18, the modified combination of Terashima and Kandah teaches the limitations of claim 12 and Terashima further teaches:
the gate driving unit is further configured to set the reporting signal to a third report status when a short circuit event is detected ([0087]).
For claim 19, the modified combination of Terashima and Kandah teaches the limitations of claim 16 and Terashima further teaches:
the gate driving unit is further configured to set the reporting signal to a second report status when a situation of substantially non-ZVS is identified and to set the reporting signal to a third report status when a short circuit event is detected (as discussed in the rejection of claims 17-18 above), and wherein the first report status, the second report status and the third report status are different from each other (different pulse lengths based on 35a-c, as understood by examination of Figure 2).
For claim 20, the modified combination of Terashima and Kandah teaches the limitations of claim 16 and Terashima further teaches:
when the switch driving signal is at the driving set logic state, the gate driving unit is further configured to determine that a short circuit event is detected if the current signal is flowing into the third terminal for a predetermined short circuit detection time or if a voltage on the third terminal is higher than a first supply voltage on a fourth terminal of the gate driving unit (as understood by examination of Figure 2).
For claim 21, the modified combination of Terashima and Kandah teaches the limitations of claim 20 and Terashima further teaches:
the gate driving unit is further configured to reset the switch driving signal to the driving reset logic state when the short circuit event is detected (as understood by examination of Figure 2).
For claim 22, the modified combination of Terashima and Kandah teaches the limitations of claim 20 and Kandah further teaches:
the third terminal of the gate driving unit includes a non-inverting output terminal (output of 301) and an inverting output terminal (output of 303); and
wherein the non-inverting output terminal is adapted to be coupled to a common driving connection node (341) with or without a first resistive device (as understood by examination of Figure 3), and the inverting output terminal is adapted to be coupled to the common driving connection node with or without a second resistive device (as understood by examination of Figure 3); and
wherein the common driving connection node is configured to provide the switch driving signal (as understood by the combination of references); and
wherein the current signal flowing through the third terminal is detected or monitored on the inverting output terminal.
For claim 23, the modified combination of Terashima and Kandah teaches the limitations of claim 20 and Kandah further teaches:
the non-inverting output terminal is configured to set the switch driving signal at the driving set logic state when a signal of logic high is asserted at this non-inverting output terminal and is further configured to have a high impedance state when the switch driving signal is reset at the driving reset logic state (as understood by the combination of references); and
wherein the inverting output terminal is configured to reset the switch driving signal at the driving reset logic state when a signal of logic low is asserted at this inverting output terminal and is further configured to have a high impedance state when the switch driving signal is set at the driving set logic state (as understood by the combination of references).
For claim 24, the modified combination of Terashima and Kandah teaches the limitations of claim 1 and Kandah further teaches:
a fourth terminal (top terminal of 301), configured as a first power supply terminal of the gate driving unit adapted to be configured to provide a first supply voltage (as understood by the combination of references).
For claim 25, the modified combination of Terashima and Kandah teaches the limitations of claim 1 but fails to teach the isolation circuit as claimed.
However, Kandah teaches (Figures 2-3) a galvanic isolation barrier ([0010]) between a first circuit which transmits a PWM signal (PWM1) to a second circuit comprising a gate driver (111) for generating driving signals based on the PWM signal (as understood by examination of Figure 2).
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to implement the modified combination of Terashima and Kandah (as defined in the rejection of claim 1) within a driver module having galvanic isolation as taught by Kandah in order to transfer information between different voltage domains ([0002]).
Furthermore, all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill at the time of the invention.
The combination of Terashima and Kandah as cited above teaches:
an isolation circuit (214, 216, 218, 220), adapted to be configured to provide a galvanic isolation between a primary side (109) and a secondary side (111) of the gate driving unit; and
a fifth terminal (input to 213), disposed at the primary side and adapted to be configured to receive a gate control signal (PWM1); and
wherein the first terminal, the second terminal and the third terminal are disposed at the secondary side (as understood by the combination of references); and
wherein the isolation circuit includes a first signal isolation and transmission channel adapted to be configured to couple the fifth terminal to the first terminal so that the gate control signal can be transmitted to the secondary side as the pulse width modulated signal (as understood by the combination of references).
For claim 26, the modified combination of Terashima and Kandah teaches the limitations of claim 1 and Kandah further teaches:
a sixth terminal (connected to ground), disposed at the primary side and adapted to be configured as a primary side reference ground terminal for circuitries at the primary side of the gate driving unit (as understood by examination of Figure 2); and
a seventh terminal (connected to VCCL), disposed at the primary side and adapted to be configured as a primary side power supply terminal of the gate driving unit (as understood by examination of Figure 2).
For claim 27, the modified combination of Terashima and Kandah teaches the limitations of claim 1 and Kandah further teaches:
the fifth terminal includes a non-inverting input terminal (output terminal of 301) and an inverting input terminal (output terminal of 302), and wherein the non-inverting input terminal is adapted to be configured to receive a first gate control signal (GHS), and the inverting input terminal is adapted to be configured to receive a second gate control signal (GLS); and wherein the first gate control signal and the second gate control signal determine the gate control signal (as understood by examination of Figure 3).
For claim 29, the modified combination of Terashima and Kandah teaches the limitations of claim 25 and Kandah further teaches:
a reporting terminal (terminal which provides DATA to 215), disposed at the primary side and configured to provide a reporting signal (as understood by examination of Figure 2).
For claim 30, the modified combination of Terashima and Kandah teaches the limitations of claim 29 and Terashima further teaches:
a temperature sensing input terminal (inverting input to CP3), disposed at the secondary side (as understood by the combination of references as cited above) and adapted to be configured to detect a temperature reading signal (via a comparison, as understood by examination of Figure 2); and
wherein the gate driving unit is further configured to provide a temperature report signal (Soh) having a pulse width modulated by the temperature reading signal (as understood by examination of Figure 2); and
wherein the gate driving unit is further configured to set the reporting signal to a first report status embodied as the temperature report signal during normal operation (as understood by the combination of references).
For claim 31, the modified combination of Terashima and Kandah teaches the limitations of claim 29 and Terashima further teaches:
the third terminal is coupled to a control terminal of a switching device (1i), and wherein the current signal includes a miller current flowing through the control terminal of the switching device and indicative of a changing rate of a voltage-drop across the switching device (capable of, as understood by the combination of references).
For claim 32, Terashima teaches a gate driving unit (all of Figure 2 except for 1i) comprising:
a first terminal (input to 31 which receives DSG) adapted to be configured as a control terminal (as understood by examination of Figure 2);
a third terminal (output of 31) adapted to be configured as an output terminal of the gate driving unit (as understood by examination of Figure 2); and
wherein the gate driving unit is configured to provide a switch driving signal having a logic state including a driving set logic state (logic high) and a driving reset logic state (logic low) at the third terminal (as understood by examination of Figure 2), and further configured to identify an operation status of the gate driving unit based on a current signal flowing through the third terminal (via 18 and 32, [0028], [0030]).
Terashima fails to distinctly disclose:
a second terminal adapted to be configured as a reference ground terminal; and
a fourth terminal adapted to be configured as a power supply terminal of the gate driving unit;
Terashima fails to teach the details of the gate driver circuit 31 but does teach said gate driver 31 drives an IGBT (1i) based on a PWM signal (DSG) and a protection signal (Spc) such that “while the protection factor continuation signal Sps is a high level, the gate control circuit 31 stops outputting the operation signal DSG to the gate of the IGBT 1i.” ([0030]).
Kandah teaches a gate driver (131, 133, 230, 233 and 235, Figure 3) having a first switch (301) for providing a logic high signal (VCCH1) to the gate of an IGBT (121), a second switch (303) for providing a logic low signal (Vneg) to the gate of the IGBT and a third switch (305) “to strongly keep IGBT 121 turned off when desired” ([0032]).
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to use Kandah’s gate driver to implement Terashima’s gate driver 31 since it merely relates to a specific-for-broad substitution, i.e., any person having ordinary skill in the art would have easily recognized that the generic box labeled "gate driver" in Terashima’s Fig. 2 suggests that any well-known level shifter circuitry can/should be used to implement this generic box.
Furthermore, the particular known technique was recognized as part of the ordinary capabilities of one skilled in the art.
The combination of Terashima and Kandah teaches:
a fourth terminal adapted to be configured as a power supply terminal of the gate driving unit (via 301); and
a second terminal adapted to be configured as a reference terminal (Vneg) but fails to teach the reference terminal being ground.
However, it would have been obvious to one having ordinary skill in the art at the time of invention to use ground potential instead of a negative voltage since the reference potential used by the gate driver can be set to any value desired within a working range. Thus, creating the claimed relationships would only involve routine "design optimization", which has been held to be within the ordinary capabilities of a person having ordinary skill in the art. Applicant should note In re Aller, 105 USPQ 233 (1955) where it was held that optimizing particular values is obvious to a person of ordinary skill in the art (who would easily be able to set different values within the range of possible values in order to arrive at the best value by simple experimentation). Note also In re Bosch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980) where it was held that discovering an optimum value of a result effective variable involves only routine skill in the art.
For claim 33, the modified combination of Terashima and Kandah teaches the limitations of claim 32 and Terashima further teaches:
the gate driving unit is further configured to control the logic state of the switch driving signal based on a pulse width modulated signal received at the first terminal (DSG) and the current signal (as understood by examination of Figure 2).
For claim 34, the modified combination of Terashima and Kandah teaches the limitations of claim 32 and Terashima further teaches:
a reporting terminal (ta), configured to provide a reporting signal indicative of the operation status (ALM).
For claim 35, Terashima teaches a gate driving unit (all of Figure 2 except for 1i) comprising:
a first terminal (input to 31 which receives DSG) adapted to be configured as a control terminal to receive a pulse width modulated signal (DSG) having a set logic state (logic high) and a reset logic state (logic low);
a third terminal (output of 31) adapted to be configured as an output terminal of the gate driving unit (as understood by examination of Figure 2) for providing a switch driving signal having a logic state including a driving set logic state (logic high) and a driving reset logic state (logic low); and
a reporting terminal (ta), configured to provide a reporting signal (ALM);
wherein the gate driving unit is configured to detect or monitor a current signal flowing through the third terminal (via 18 and 32), and further configured to adjust the fault reporting signal based on the current signal ([0028], [0030]).
Terashima fails to teach:
a second terminal adapted to be configured as a reference ground terminal;
Terashima fails to teach the details of the gate driver circuit 31 but does teach said gate driver 31 drives an IGBT (1i) based on a PWM signal (DSG) and a protection signal (Spc) such that “while the protection factor continuation signal Sps is a high level, the gate control circuit 31 stops outputting the operation signal DSG to the gate of the IGBT 1i.” ([0030]).
Kandah teaches a gate driver (131, 133, 230, 233 and 235, Figure 3) having a first switch (301) for providing a logic high signal (VCCH1) to the gate of an IGBT (121), a second switch (303) for providing a logic low signal (Vneg) to the gate of the IGBT and a third switch (305) “to strongly keep IGBT 121 turned off when desired” ([0032]).
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to use Kandah’s gate driver to implement Terashima’s gate driver 31 since it merely relates to a specific-for-broad substitution, i.e., any person having ordinary skill in the art would have easily recognized that the generic box labeled "gate driver" in Terashima’s Fig. 2 suggests that any well-known level shifter circuitry can/should be used to implement this generic box.
Furthermore, the particular known technique was recognized as part of the ordinary capabilities of one skilled in the art.
The combination of Terashima and Kandah teaches a second terminal adapted to be configured as a reference terminal (Vneg) but fails to teach the reference terminal being ground.
However, it would have been obvious to one having ordinary skill in the art at the time of invention to use ground potential instead of a negative voltage since the reference potential used by the gate driver can be set to any value desired within a working range. Thus, creating the claimed relationships would only involve routine "design optimization", which has been held to be within the ordinary capabilities of a person having ordinary skill in the art. Applicant should note In re Aller, 105 USPQ 233 (1955) where it was held that optimizing particular values is obvious to a person of ordinary skill in the art (who would easily be able to set different values within the range of possible values in order to arrive at the best value by simple experimentation). Note also In re Bosch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980) where it was held that discovering an optimum value of a result effective variable involves only routine skill in the art.
For claim 36, the modified combination of Terashima and Kandah teaches the limitations of claim 35 and Terashima further teaches:
the gate driving unit is further configured to set the reporting signal to a first report status during normal operation ([0054]).
For claim 37, the modified combination of Terashima and Kandah teaches the limitations of claim 35 and Terashima further teaches:
the gate driving unit is further configured to set the reporting signal to a second report status (via 34) when a situation of substantially non-ZVS is identified (e.g., overheating, [0028]).
For claim 38, the modified combination of Terashima and Kandah teaches the limitations of claim 35 and Terashima further teaches:
the gate driving unit is further configured to set the reporting signal to a third report status when a short circuit event is detected ([0087]).
For claim 40, the modified combination of Terashima and Kandah teaches the limitations of claim 35 and Terashima further teaches:
the gate driving unit is further configured to determine that the short circuit event is detected if the current signal is flowing into the third terminal for a predetermined short circuit detection time during the switch driving signal is at the driving set logic state or if a voltage on the third terminal is higher than a first supply voltage on a fourth terminal of the gate driving unit during the switch driving signal is at the driving set logic state (0087]).
For claim 41, the modified combination of Terashima and Kandah teaches the limitations of claim 35 and Terashima further teaches:
the gate driving unit is further configured to control the logic state of the switch driving signal based on the pulse width modulated signal and the current signal (as understood by examination of Figure 2).
For claim 42, the modified combination of Terashima and Kandah teaches the limitations of claim 41 and Terashima further teaches:
the gate driving unit is further configured to reset the switch driving signal at the driving reset logic state when the pulse width modulated signal is changed from the set logic state to the reset logic state (as understood by examination of Figure 2).
For claim 43, the modified combination of Terashima and Kandah teaches the limitations of claim 41 and Terashima further teaches:
the gate driving unit is further configured to set the switch driving signal at the driving set logic state (logic high) if a first detection event indicative of the current signal flowing out of the third terminal (no overcurrent detected) and then falling substantially at zero has been identified during a first detection time window (a window large enough to detect an overcurrent event, as understood by examination of Figure 2) and the pulse width modulated signal is at the set logic state (as understood by examination of Figure 2), and wherein the first detection time window has a first window width (inherent of all time windows) and is enabled or set during the switch driving signal is at the driving reset logic state (capable of, as understood by the combination of references as cited above).
For claim 44, the modified combination of Terashima and Kandah teaches the limitations of claim 41 and Terashima further teaches:
the gate driving unit is further configured to force the switch driving signal to be set at the driving set logic state if a first detection event indicative of the current signal flowing out of the third terminal and then falling substantially at zero has neither been identified during a first detection time window nor been identified until a maximum detection time period expires (minimum time required for 1i to reach a normal operating current after 1i is off) since a moment when the pulse width modulated signal is changed from the reset logic state to the set logic state (capable of, as understood by the combination of references); and wherein the first detection time window has a first window width (inherent of all time windows) and is enabled or set during the switch driving signal is at the driving reset logic state (as understood by examination of Figure 2).
For claim 45, the modified combination of Terashima and Kandah teaches the limitations of claim 35 and Terashima further teaches:
a temperature sensing input terminal, adapted to be configured to detect a temperature reading signal (inverting input to CP3); and
wherein the gate driving unit is further configured to provide a temperature report signal having a pulse width modulated by the temperature reading signal (Soh); and wherein the gate driving unit is further configured to set the reporting signal to a first report status embodied as the temperature report signal during normal operation (as understood by examination of Figure 2).
For claim 46, the modified combination of Terashima and Kandah teaches the limitations of claim 35 and Terashima further teaches:
the gate driving unit is further configured to determine that the short circuit event is detected if the current signal is flowing into the third terminal for a predetermined short circuit detection time during the switch driving signal is at the driving set logic state (as understood by examination of Figure 2 and [0087]), or if a voltage on the third terminal goes higher than a first supply voltage on a fourth terminal of the gate driving unit during the switch driving signal is at the driving set logic state; and
wherein the gate driving unit is further configured to reset the switch driving signal at the driving reset logic state when the short circuit event is detected ([0087]).
Allowable Subject Matter
Claims 8, 14 and 39 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL CALRISSIAN PUENTES whose telephone number is (571)270-5070. The examiner can normally be reached M-F 9-6:30 (flex).
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/DANIEL C PUENTES/Primary Examiner, Art Unit 2849