DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 4/16/2026 have been fully considered but they are not persuasive. Applicant’s first argument is as follows:
“The Applicant respectfully seeks further guidance on any specific deficiencies that may be perceived as "not of sufficient quality." Should any specific aspects-such as resolution, scale, labeling, or other details-require additional adjustment, the Applicant would greatly appreciate your advice so that these can be promptly addressed.”
The resolution of the Drawings makes the text illegible, e.g., the subscripts in Figures 2 and 4-8.
Applicant’s second argument is as follows:
“…it should be obvious for those skilled in the art that "driving set logic state", "driving reset logic", "reset logic state" and "set logic state" would indicate requiring logic high and logic low state that could be used to turn on/off the switching device… it should be obvious for those skilled in the art that the first "reset" in Claim 2 state "reset the switch driving signal to the driving reset logic state" means an action to change the driving signal from the set logic state (e.g., logic high) to reset logic state (e.g., logic low), and the "driving reset logic state" means a logic state. And it is obvious for those skilled in the art that the first "set" in Claim 4 state "set the switch driving signal at the driving set logic state" means an action to change the driving signal from the reset logic state (e.g., logic low) to set logic state (e.g., logic high ), and the "driving set logic state" means a logic state.”
Applicant’s arguments are persuasive. The rejection under §112 has been withdrawn.
Applicant’s third argument is as follows:
“It should be obvious for those skilled in the art that Terashima's disclosure the current detected or monitored is the current flowing through IGBT 1i not the current flowing through the third terminal (output of 31). And thus, Terashima does not disclose the gate driving unit control the logic state of the switch driving signal based on the pulse width modulated signal and the current signal flowing through the third terminal. Terashima detects the current flowing through the IGBT from a collector to an emitter to monitor an overcurrent situation. While, claim 1 detects the current signal flowing through the third terminal, which is an output terminal of the gate driving unit for providing a switch driving signal, and further requires to control the logic state of the switch driving signal based on the current signal flowing through this third terminal configured as the output terminal of the gate driving unit . Claim 1 is completely different from Terashima's disclosure.”
Claim 1 requires the gate driving circuit to “detect or monitor a current signal flowing through the third terminal.” This does not require a direct connection to the third terminal. The output of current sensor 18 is based upon the current at the gate of 1i ([30]-[31]). If the control terminal to n-type IGBT 1i is a logic high, the current sensor 18 will detect a current. If the control terminal to n-type IGBT 1i is a logic low, the current sensor 18 will not detect a current. Therefore, current sensor 18 detects a current signal flowing through the third terminal.
Applicant’s fourth argument is as follows:
“For claim 3,…Terashima discloses the overcurrent detection circuit 32 detects an overcurrent state of the IGBT 1i ([0028]). Terashima detects the current all the time, there doesn't have a first detection time window that could be enabled, and Terashima does not teach should enable a detection time window to detect an event. And if "no overcurrent detected during IGBT is ON" in Terashima's disclosure deemed equivalent to "first detection event", the switch driving signal is at driving set logic state other than driving reset logic state. To sum up, Terashima does not teach a detection time window is enabled during the switch driving signal is at the driving reset logic state.”
During operation of Terashima’s invention, the detection time window is not required to be disabled, only that it is enabled when the switch driving window is at the driving reset logic state. Since an always-enabled first detection time window is inherent during operation of Terashima’s invention, a period of time must inherently exist that encompasses the first detection event. The window width of the always-enabled detection time window corresponds to the operational state (ON/OFF) of Terashima.
Applicant’s fifth argument is as follows:
“…Terashima just detects the current signal rises to or above a predetermined threshold current value or just detects the current falls back to or below a predetermined threshold current value to judge whether an overcurrent event accrues or not. Terashima does not teach compare the current with a first predetermined threshold current value and a second predetermined threshold current value and judge the trend of current changes whether the current signal rises to or above a first predetermined threshold current value and then falls back to or below a second predetermined threshold current value during the first detection time window.”
Judging the trend of current changes is not required by the claim. The “if” statement of claim 5 does not require a cause-and-effect relationship but rather, only that the first detection event is identified concurrently to the rise and fall of the predetermined threshold current value as claimed.
Applicant’s sixth argument is as follows:
“For claim 6, refer to the applicant's response to the examination opinions on claim 3, Terashima does not teach enable or set the first detection time window, Terashima also fails to teach a first predetermined leading-edge blanking time. Claim 6 is non- obvious compared with the combination of Terashima and Kandah.”
The term “first predetermined leading-edge blanking time” is not required by the disclosure to provide any particular structure of functionality. Blanking is not a known term of art within gate driving circuits. The claim does not cite what signal the “leading-edge” relates to. Applicant is encouraged to specify the meaning of this term as it pertains to their invention. For the purposes of examination, examiner will continue to interpret the broadest reasonable interpretation of the term as “a first predetermined time”.
Applicant’s seventh argument is as follows:
“For claim 7, Terashima discloses to the gate control circuit 31, a pulse-width modulation (PWM) signal is input from the outside of the driver circuits 3U to 3Z as an operation signal DSG and a protection factor continuation signal Spc output from the continuation signal generation unit 36 is input. While the protection factor continuation signal Spc is a low level, this gate control circuit 31 outputs the operation signal DSG to the gate of the IGBT 1i. While the protection factor continuation signal Sps is a high level, the gate control circuit 31 stops outputting the operation signal DSG to the gate of the IGBT 1i ([0030]). Terashima turn on the IGBT when Spc is a low level, has no association with time parameters. Terashima fails to teach enabling a maximum detection time period and fails to teach forcing the switch driving signal to be set at the driving set logic state if the first detection event has not been identified until the maximum detection time period expires. Claim 7 is non-obvious compared with the combination of Terashima and Kandah.”
Applicant’s arguments are considered persuasive. The rejection of claim 7 has been withdrawn.
Applicant’s eighth argument is as follows:
“For claim 11, the Applicant amended non-ZVS to non-zero voltage soft switching. Terashima fails to teach the gate driving unit is further configured to set the reporting signal to a second report status when a situation of substantially non- zero voltage soft switching is identified. It should be obvious for those skilled in the art the overheating event is different with non- zero voltage soft switching. Claim 11 is non-obvious compared with the combination of Terashima and Kandah.”
A “situation of substantial non-zero voltage soft switching is identified” does not require the identification of zero voltage soft switching.
Applicant’s ninth argument is as follows:
“For claim 15, Terashima fails to teach detect current flow into the third terminal, not to mention detect if the current signal is flowing into the third terminal for a predetermined short circuit detection time during the switch driving signal is at the driving set logic state. Terashima fails to teach detect the voltage on the third terminal, not to mention detect if a voltage on the third terminal is higher than a first supply voltage on a fourth terminal of the gate driving unit during the switch driving signal is at the driving set logic state. Claim 15 is non-obvious compared with the combination of Terashima and Kandah.”
Please see arguments regarding claims 1 and 3 above.
Applicant’s tenth argument is as follows:
“For claim 17 and 19, the Applicant amended non-ZVS to non-zero voltage soft switching. Terashima fails to teach identified a situation of substantially non-zero voltage soft switching. And Terashima fails to teach the gate driving unit is further configured to set the reporting signal to a second report status when the gate driving unit has identified a situation of substantially non- zero voltage soft switching. It should be obvious for those skilled in the art that under voltage event is different with non-zero voltage soft switching, under voltage indicates the voltage lower than a threshold value. Claim 17 and 19 are non-obvious compared with the combination of Terashima and Kandah.”
A “situation of substantial non-zero voltage soft switching is identified” does not require the identification of zero voltage soft switching.
Applicant’s eleventh argument is as follows:
“For claim 20, Terashima fails to teach detect current flow into the third terminal, not to mention detect if the current signal is flowing into the third terminal for a predetermined short circuit detection time during the switch driving signal is at the driving set logic state. Terashima fails to teach detect the voltage on the third terminal, not to mention detect if a voltage on the third terminal is higher than a first supply voltage on a fourth terminal of the gate driving unit during the switch driving signal is at the driving set logic state. Claim 20 is non-obvious compared with the combination of Terashima and Kandah.”
Please see arguments regarding claims 1 and 3 above.
Applicant’s twelfth argument is as follows:
“For claim 22, Terashima and Kandah both fail to teach detect the current flowing through the third terminal. Claim 22 is non-obvious compared with the combination of Terashima and Kandah.”
Please see arguments regarding claims 1 and 3 above.
Applicant’s thirteenth argument is as follows:
“For claim 31, Terashima fails to teach detect a current signal includes a miller current flowing through the control terminal of the switching device. Claim 31 is non-obvious compared with the combination of Terashima and Kandah.”
Miller current is based on the inherent parasitic gate to drain capacitance of IGBT switches such as Terashima’s 1i.
Applicant’s fourteenth argument is as follows:
“For claim 32, …Terashima discloses a current sensor 18 and an overcurrent detection circuit 32, the overcurrent detection circuit 32 monitors a current detected by the current sensor 18, the current sensor detects a current flowing between a collector and an emitter of an IGBT 1 i([0027], [0028], [0031]). It should be obvious for those skilled in the art that Terashima's disclosure the current detected or monitored is the current flowing through IGBT 1i not the current flowing through the third terminal (output of 31). And thus, Terashima does not disclose the gate driving unit identifies an operation status of the gate driving unit based on a current signal flowing through the third terminal.”
Please see arguments regarding claims 1 and 3 above.
Applicant’s fifteenth argument is as follows:
“For claim 35, Terashima at least does not teaches "the gate driving unit is configured to detect or monitor a current signal flowing through the third terminal, and further configured to adjust the fault reporting signal based on the current signal."
Please see arguments regarding claims 1 and 3 above.
Applicant’s sixteenth argument is as follows:
“For claim 37, the Applicant amended non-ZVS to non-zero voltage soft switching. Terashima fails to teach identified a situation of substantially non-zero voltage soft switching. And Terashima fails to teach the gate driving unit is further configured to set the reporting signal to a second report status when the gate driving unit has identified a situation of substantially non- zero voltage soft switching. Under voltage event is different with non-zero voltage soft switching, under voltage indicates the voltage lower than a threshold value. Claim 37 is non-obvious compared with the combination of Terashima and Kandah.”
A “situation of substantial non-zero voltage soft switching is identified” does not require the identification of zero voltage soft switching.
Applicant’s seventeenth argument is as follows:
“For claim 40 and 46, Terashima fails to teach detect current flow into the third terminal, not to mention detect if the current signal is flowing into the third terminal for a predetermined short circuit detection time during the switch driving signal is at the driving set logic state. Terashima fails to teach detect the voltage on the third terminal, not to mention detect if a voltage on the third terminal is higher than a first supply voltage on a fourth terminal of the gate driving unit during the switch driving signal is at the driving set logic state. Claim 40 and 46 are non-obvious compared with the combination of Terashima and Kandah.”
Please see arguments regarding claims 1 and 3 above.
Election/Restrictions
As stated in the prior office action, Examiner has determined that a restriction is not required for all claims other than claim 28, which teaches away from the isolation barrier required by the elected Species (Figure 11). Thus, all claims have been examined on the merits except for claim 28. Claim 28 is considered withdrawn.
Drawings
The drawings are not of sufficient quality to permit examination. Accordingly, replacement drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to this Office action. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action.
Applicant is given a shortened statutory period of TWO (2) MONTHS to submit new drawings in compliance with 37 CFR 1.81. Extensions of time may be obtained under the provisions of 37 CFR 1.136(a) but in no case can any extension carry the date for reply to this letter beyond the maximum period of SIX MONTHS set by statute (35 U.S.C. 133). Failure to timely submit replacement drawing sheets will result in ABANDONMENT of the application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-6, 9-13, 15-19, 27, 29-36, 38 and 40-46 is/are rejected under 35 U.S.C. 103 as being unpatentable over Terashima (US 2018/0367023) in view of Kandah et al (EP 3223416 B1).
For claim 1, Terashima teaches a gate driving unit (all of Figure 2 except for 1i) comprising:
a first terminal (input to 31 which receives DSG) adapted to be configured as a control terminal to receive a pulse width modulated signal (DSG) having a set logic state (logic high) and a reset logic state (logic low); and
a third terminal (output of 31) adapted to be configured as an output terminal of the gate driving unit for providing a switch driving signal having a logic state including a driving set logic state and a driving reset logic state (as understood by examination of Figure 2);
wherein the gate driving unit is configured to detect or monitor a current signal flowing through the third terminal (via 18 and 32) and further configured to control the logic state of the switch driving signal based on the pulse width modulated signal and the current signal ([0028], [0030]).
Terashima fails to distinctly disclose:
a second terminal adapted to be configured as a reference ground terminal.
Terashima fails to teach the details of the gate driver circuit 31 but does teach said gate driver 31 drives an IGBT (1i) based on a PWM signal (DSG) and a protection signal (Spc) such that “while the protection factor continuation signal Sps is a high level, the gate control circuit 31 stops outputting the operation signal DSG to the gate of the IGBT 1i.” ([0030]).
Kandah teaches a gate driver (131, 133, 230, 233 and 235, Figure 3) having a first switch (301) for providing a logic high signal (VCCH1) to the gate of an IGBT (121), a second switch (303) for providing a logic low signal (Vneg) to the gate of the IGBT and a third switch (305) “to strongly keep IGBT 121 turned off when desired” ([0032]).
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to use Kandah’s gate driver to implement Terashima’s gate driver 31 since it merely relates to a specific-for-broad substitution, i.e., any person having ordinary skill in the art would have easily recognized that the generic box labeled "gate driver" in Terashima’s Fig. 2 suggests that any well-known level shifter circuitry can/should be used to implement this generic box.
Furthermore, the particular known technique was recognized as part of the ordinary capabilities of one skilled in the art.
The combination of Terashima and Kandah teaches a second terminal adapted to be configured as a reference terminal (Vneg) but fails to teach the reference terminal being ground.
However, it would have been obvious to one having ordinary skill in the art at the time of invention to use ground potential instead of a negative voltage since the reference potential used by the gate driver can be set to any value desired within a working range. Thus, creating the claimed relationships would only involve routine "design optimization", which has been held to be within the ordinary capabilities of a person having ordinary skill in the art. Applicant should note In re Aller, 105 USPQ 233 (1955) where it was held that optimizing particular values is obvious to a person of ordinary skill in the art (who would easily be able to set different values within the range of possible values in order to arrive at the best value by simple experimentation). Note also In re Bosch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980) where it was held that discovering an optimum value of a result effective variable involves only routine skill in the art.
For claim 2, the modified combination of Terashima and Kandah teaches the limitations of claim 1 and Terashima further teaches:
wherein the gate driving unit is further configured to reset the switch driving signal at the driving reset logic state in response to the pulse width modulated signal's changing from the set logic state to the reset logic state ([0030] and as understood by examination of Figure 2).
For claim 3, the modified combination of Terashima and Kandah teaches the limitations of claim 1 and Terashima further teaches:
the gate driving unit is further configured to determine whether a first detection event (no overcurrent detected) has been identified (via 32, [0036]) during a first detection time window (a window large enough to detect an overcurrent event, as understood by examination of Figure 2) based on the current signal (as understood by examination of Figure 2), and wherein the first detection time window has a first window width (inherent of all time windows) and is enabled during the switch driving signal is at the driving reset logic state (capable of, as understood by the combination of references as cited above).
For claim 4, the modified combination of Terashima and Kandah teaches the limitations of claim 3 and Terashima further teaches:
the gate driving unit is further configured to set the switch driving signal at the driving set logic state (logic high) on condition that the first detection event has been identified during the first detection time window and the pulse width modulated signal is at the set logic state (as understood by the combination of references as cited above).
For claim 5, the modified combination of Terashima and Kandah teaches the limitations of claim 3 and Terashima further teaches:
the gate driving unit is further configured to determine that the first detection event has been identified during the first detection time window if the current signal rises to or above a first predetermined threshold current value (a value higher than the current corresponding to Vth1) and then falls back to or below a second predetermined threshold current value (current corresponding to Vth1) during the first detection time window (detection during the period in which the current is below Vth1).
For claim 6, the modified combination of Terashima and Kandah teaches the limitations of claim 3 and Terashima further teaches:
the gate driving unit is further configured to enable or set the first detection time window when a first predetermined leading-edge blanking time (minimum time required for 1i to reach a normal operating current after 1i is off) has elapsed since a moment when the switch driving signal is reset from the driving set logic state to the driving reset logic state (as understood by examination of Figure 2).
For claim 9, the modified combination of Terashima and Kandah teaches the limitations of claim 1 and Terashima further teaches:
a reporting terminal (ta), configured to provide a reporting signal (ALM, Figure 2)
For claim 10, the modified combination of Terashima and Kandah teaches the limitations of claim 9 and Terashima further teaches:
the gate driving unit is further configured to set the reporting signal to a first report status during normal operation ([0054]).
For claim 11, the modified combination of Terashima and Kandah teaches the limitations of claim 10 and Terashima further teaches:
the gate driving unit is further configured to set the reporting signal to a second report status (via 34) when a situation of substantially non-ZVS is identified (e.g., overheating, [0028]).
For claim 12, the modified combination of Terashima and Kandah teaches the limitations of claim 10 and Terashima further teaches:
the gate driving unit is further configured to set the reporting signal to a third report status when a short circuit event is detected ([0087]).
For claim 13, the modified combination of Terashima and Kandah teaches the limitations of claim 10 and Terashima further teaches:
the gate driving unit is further configured to set the reporting signal to a second report status when a situation of substantially non-ZVS is identified and to set the reporting signal to a third report status when a short circuit event is detected (as discussed in the rejection of claims 11-12 above), and wherein the first report status, the second report status and the third report status are different from each other (different pulse lengths based on 35a-c, as understood by examination of Figure 2).
For claim 15, the modified combination of Terashima and Kandah teaches the limitations of claim 12 and Terashima further teaches:
the gate driving unit is further configured to determine that the short circuit event is detected if the current signal is flowing into the third terminal for a predetermined short circuit detection time during the switch driving signal is at the driving set logic state (as understood by examination of Figure 2 and [0087]).
For claim 16, the modified combination of Terashima and Kandah teaches the limitations of claim 10 and Terashima further teaches:
a temperature sensing input terminal, adapted to be configured to detect a temperature reading signal (inverting input to CP3); and
wherein the gate driving unit is further configured to provide a temperature report signal having a pulse width modulated by the temperature reading signal (Soh); and wherein the gate driving unit is further configured to set the reporting signal to a first report status embodied as the temperature report signal during normal operation (as understood by examination of Figure 2).
For claim 17, the modified combination of Terashima and Kandah teaches the limitations of claim 12 and Terashima further teaches:
the gate driving unit is further configured to set the reporting signal to a second report status (via 33) when the gate driving unit has identified a situation of substantially non-ZVS (undervoltage, [0028]), the second report status being different from the first report status (different pulse widths via 35).
For claim 18, the modified combination of Terashima and Kandah teaches the limitations of claim 12 and Terashima further teaches:
the gate driving unit is further configured to set the reporting signal to a third report status when a short circuit event is detected ([0087]).
For claim 19, the modified combination of Terashima and Kandah teaches the limitations of claim 16 and Terashima further teaches:
the gate driving unit is further configured to set the reporting signal to a second report status when a situation of substantially non-ZVS is identified and to set the reporting signal to a third report status when a short circuit event is detected (as discussed in the rejection of claims 17-18 above), and wherein the first report status, the second report status and the third report status are different from each other (different pulse lengths based on 35a-c, as understood by examination of Figure 2).
For claim 20, the modified combination of Terashima and Kandah teaches the limitations of claim 16 and Terashima further teaches:
when the switch driving signal is at the driving set logic state, the gate driving unit is further configured to determine that a short circuit event is detected if the current signal is flowing into the third terminal for a predetermined short circuit detection time or if a voltage on the third terminal is higher than a first supply voltage on a fourth terminal of the gate driving unit (as understood by examination of Figure 2).
For claim 21, the modified combination of Terashima and Kandah teaches the limitations of claim 20 and Terashima further teaches:
the gate driving unit is further configured to reset the switch driving signal to the driving reset logic state when the short circuit event is detected (as understood by examination of Figure 2).
For claim 22, the modified combination of Terashima and Kandah teaches the limitations of claim 20 and Kandah further teaches:
the third terminal of the gate driving unit includes a non-inverting output terminal (output of 301) and an inverting output terminal (output of 303); and
wherein the non-inverting output terminal is adapted to be coupled to a common driving connection node (341) with or without a first resistive device (as understood by examination of Figure 3), and the inverting output terminal is adapted to be coupled to the common driving connection node with or without a second resistive device (as understood by examination of Figure 3); and
wherein the common driving connection node is configured to provide the switch driving signal (as understood by the combination of references); and
wherein the current signal flowing through the third terminal is detected or monitored on the inverting output terminal.
For claim 23, the modified combination of Terashima and Kandah teaches the limitations of claim 20 and Kandah further teaches:
the non-inverting output terminal is configured to set the switch driving signal at the driving set logic state when a signal of logic high is asserted at this non-inverting output terminal and is further configured to have a high impedance state when the switch driving signal is reset at the driving reset logic state (as understood by the combination of references); and
wherein the inverting output terminal is configured to reset the switch driving signal at the driving reset logic state when a signal of logic low is asserted at this inverting output terminal and is further configured to have a high impedance state when the switch driving signal is set at the driving set logic state (as understood by the combination of references).
For claim 24, the modified combination of Terashima and Kandah teaches the limitations of claim 1 and Kandah further teaches:
a fourth terminal (top terminal of 301), configured as a first power supply terminal of the gate driving unit adapted to be configured to provide a first supply voltage (as understood by the combination of references).
For claim 25, the modified combination of Terashima and Kandah teaches the limitations of claim 1 but fails to teach the isolation circuit as claimed.
However, Kandah teaches (Figures 2-3) a galvanic isolation barrier ([0010]) between a first circuit which transmits a PWM signal (PWM1) to a second circuit comprising a gate driver (111) for generating driving signals based on the PWM signal (as understood by examination of Figure 2).
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to implement the modified combination of Terashima and Kandah (as defined in the rejection of claim 1) within a driver module having galvanic isolation as taught by Kandah in order to transfer information between different voltage domains ([0002]).
Furthermore, all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill at the time of the invention.
The combination of Terashima and Kandah as cited above teaches:
an isolation circuit (214, 216, 218, 220), adapted to be configured to provide a galvanic isolation between a primary side (109) and a secondary side (111) of the gate driving unit; and
a fifth terminal (input to 213), disposed at the primary side and adapted to be configured to receive a gate control signal (PWM1); and
wherein the first terminal, the second terminal and the third terminal are disposed at the secondary side (as understood by the combination of references); and
wherein the isolation circuit includes a first signal isolation and transmission channel adapted to be configured to couple the fifth terminal to the first terminal so that the gate control signal can be transmitted to the secondary side as the pulse width modulated signal (as understood by the combination of references).
For claim 26, the modified combination of Terashima and Kandah teaches the limitations of claim 1 and Kandah further teaches:
a sixth terminal (connected to ground), disposed at the primary side and adapted to be configured as a primary side reference ground terminal for circuitries at the primary side of the gate driving unit (as understood by examination of Figure 2); and
a seventh terminal (connected to VCCL), disposed at the primary side and adapted to be configured as a primary side power supply terminal of the gate driving unit (as understood by examination of Figure 2).
For claim 27, the modified combination of Terashima and Kandah teaches the limitations of claim 1 and Kandah further teaches:
the fifth terminal includes a non-inverting input terminal (output terminal of 301) and an inverting input terminal (output terminal of 302), and wherein the non-inverting input terminal is adapted to be configured to receive a first gate control signal (GHS), and the inverting input terminal is adapted to be configured to receive a second gate control signal (GLS); and wherein the first gate control signal and the second gate control signal determine the gate control signal (as understood by examination of Figure 3).
For claim 29, the modified combination of Terashima and Kandah teaches the limitations of claim 25 and Kandah further teaches:
a reporting terminal (terminal which provides DATA to 215), disposed at the primary side and configured to provide a reporting signal (as understood by examination of Figure 2).
For claim 30, the modified combination of Terashima and Kandah teaches the limitations of claim 29 and Terashima further teaches:
a temperature sensing input terminal (inverting input to CP3), disposed at the secondary side (as understood by the combination of references as cited above) and adapted to be configured to detect a temperature reading signal (via a comparison, as understood by examination of Figure 2); and
wherein the gate driving unit is further configured to provide a temperature report signal (Soh) having a pulse width modulated by the temperature reading signal (as understood by examination of Figure 2); and
wherein the gate driving unit is further configured to set the reporting signal to a first report status embodied as the temperature report signal during normal operation (as understood by the combination of references).
For claim 31, the modified combination of Terashima and Kandah teaches the limitations of claim 29 and Terashima further teaches:
the third terminal is coupled to a control terminal of a switching device (1i), and wherein the current signal includes a miller current flowing through the control terminal of the switching device and indicative of a changing rate of a voltage-drop across the switching device (capable of, as understood by the combination of references).
For claim 32, Terashima teaches a gate driving unit (all of Figure 2 except for 1i) comprising:
a first terminal (input to 31 which receives DSG) adapted to be configured as a control terminal (as understood by examination of Figure 2);
a third terminal (output of 31) adapted to be configured as an output terminal of the gate driving unit (as understood by examination of Figure 2); and
wherein the gate driving unit is configured to provide a switch driving signal having a logic state including a driving set logic state (logic high) and a driving reset logic state (logic low) at the third terminal (as understood by examination of Figure 2), and further configured to identify an operation status of the gate driving unit based on a current signal flowing through the third terminal (via 18 and 32, [0028], [0030]).
Terashima fails to distinctly disclose:
a second terminal adapted to be configured as a reference ground terminal; and
a fourth terminal adapted to be configured as a power supply terminal of the gate driving unit;
Terashima fails to teach the details of the gate driver circuit 31 but does teach said gate driver 31 drives an IGBT (1i) based on a PWM signal (DSG) and a protection signal (Spc) such that “while the protection factor continuation signal Sps is a high level, the gate control circuit 31 stops outputting the operation signal DSG to the gate of the IGBT 1i.” ([0030]).
Kandah teaches a gate driver (131, 133, 230, 233 and 235, Figure 3) having a first switch (301) for providing a logic high signal (VCCH1) to the gate of an IGBT (121), a second switch (303) for providing a logic low signal (Vneg) to the gate of the IGBT and a third switch (305) “to strongly keep IGBT 121 turned off when desired” ([0032]).
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to use Kandah’s gate driver to implement Terashima’s gate driver 31 since it merely relates to a specific-for-broad substitution, i.e., any person having ordinary skill in the art would have easily recognized that the generic box labeled "gate driver" in Terashima’s Fig. 2 suggests that any well-known level shifter circuitry can/should be used to implement this generic box.
Furthermore, the particular known technique was recognized as part of the ordinary capabilities of one skilled in the art.
The combination of Terashima and Kandah teaches:
a fourth terminal adapted to be configured as a power supply terminal of the gate driving unit (via 301); and
a second terminal adapted to be configured as a reference terminal (Vneg) but fails to teach the reference terminal being ground.
However, it would have been obvious to one having ordinary skill in the art at the time of invention to use ground potential instead of a negative voltage since the reference potential used by the gate driver can be set to any value desired within a working range. Thus, creating the claimed relationships would only involve routine "design optimization", which has been held to be within the ordinary capabilities of a person having ordinary skill in the art. Applicant should note In re Aller, 105 USPQ 233 (1955) where it was held that optimizing particular values is obvious to a person of ordinary skill in the art (who would easily be able to set different values within the range of possible values in order to arrive at the best value by simple experimentation). Note also In re Bosch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980) where it was held that discovering an optimum value of a result effective variable involves only routine skill in the art.
For claim 33, the modified combination of Terashima and Kandah teaches the limitations of claim 32 and Terashima further teaches:
the gate driving unit is further configured to control the logic state of the switch driving signal based on a pulse width modulated signal received at the first terminal (DSG) and the current signal (as understood by examination of Figure 2).
For claim 34, the modified combination of Terashima and Kandah teaches the limitations of claim 32 and Terashima further teaches:
a reporting terminal (ta), configured to provide a reporting signal indicative of the operation status (ALM).
For claim 35, Terashima teaches a gate driving unit (all of Figure 2 except for 1i) comprising:
a first terminal (input to 31 which receives DSG) adapted to be configured as a control terminal to receive a pulse width modulated signal (DSG) having a set logic state (logic high) and a reset logic state (logic low);
a third terminal (output of 31) adapted to be configured as an output terminal of the gate driving unit (as understood by examination of Figure 2) for providing a switch driving signal having a logic state including a driving set logic state (logic high) and a driving reset logic state (logic low); and
a reporting terminal (ta), configured to provide a reporting signal (ALM);
wherein the gate driving unit is configured to detect or monitor a current signal flowing through the third terminal (via 18 and 32), and further configured to adjust the fault reporting signal based on the current signal ([0028], [0030]).
Terashima fails to teach:
a second terminal adapted to be configured as a reference ground terminal;
Terashima fails to teach the details of the gate driver circuit 31 but does teach said gate driver 31 drives an IGBT (1i) based on a PWM signal (DSG) and a protection signal (Spc) such that “while the protection factor continuation signal Sps is a high level, the gate control circuit 31 stops outputting the operation signal DSG to the gate of the IGBT 1i.” ([0030]).
Kandah teaches a gate driver (131, 133, 230, 233 and 235, Figure 3) having a first switch (301) for providing a logic high signal (VCCH1) to the gate of an IGBT (121), a second switch (303) for providing a logic low signal (Vneg) to the gate of the IGBT and a third switch (305) “to strongly keep IGBT 121 turned off when desired” ([0032]).
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to use Kandah’s gate driver to implement Terashima’s gate driver 31 since it merely relates to a specific-for-broad substitution, i.e., any person having ordinary skill in the art would have easily recognized that the generic box labeled "gate driver" in Terashima’s Fig. 2 suggests that any well-known level shifter circuitry can/should be used to implement this generic box.
Furthermore, the particular known technique was recognized as part of the ordinary capabilities of one skilled in the art.
The combination of Terashima and Kandah teaches a second terminal adapted to be configured as a reference terminal (Vneg) but fails to teach the reference terminal being ground.
However, it would have been obvious to one having ordinary skill in the art at the time of invention to use ground potential instead of a negative voltage since the reference potential used by the gate driver can be set to any value desired within a working range. Thus, creating the claimed relationships would only involve routine "design optimization", which has been held to be within the ordinary capabilities of a person having ordinary skill in the art. Applicant should note In re Aller, 105 USPQ 233 (1955) where it was held that optimizing particular values is obvious to a person of ordinary skill in the art (who would easily be able to set different values within the range of possible values in order to arrive at the best value by simple experimentation). Note also In re Bosch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980) where it was held that discovering an optimum value of a result effective variable involves only routine skill in the art.
For claim 36, the modified combination of Terashima and Kandah teaches the limitations of claim 35 and Terashima further teaches:
the gate driving unit is further configured to set the reporting signal to a first report status during normal operation ([0054]).
For claim 37, the modified combination of Terashima and Kandah teaches the limitations of claim 35 and Terashima further teaches:
the gate driving unit is further configured to set the reporting signal to a second report status (via 34) when a situation of substantially non-ZVS is identified (e.g., overheating, [0028]).
For claim 38, the modified combination of Terashima and Kandah teaches the limitations of claim 35 and Terashima further teaches:
the gate driving unit is further configured to set the reporting signal to a third report status when a short circuit event is detected ([0087]).
For claim 40, the modified combination of Terashima and Kandah teaches the limitations of claim 35 and Terashima further teaches:
the gate driving unit is further configured to determine that the short circuit event is detected if the current signal is flowing into the third terminal for a predetermined short circuit detection time during the switch driving signal is at the driving set logic state or if a voltage on the third terminal is higher than a first supply voltage on a fourth terminal of the gate driving unit during the switch driving signal is at the driving set logic state (0087]).
For claim 41, the modified combination of Terashima and Kandah teaches the limitations of claim 35 and Terashima further teaches:
the gate driving unit is further configured to control the logic state of the switch driving signal based on the pulse width modulated signal and the current signal (as understood by examination of Figure 2).
For claim 42, the modified combination of Terashima and Kandah teaches the limitations of claim 41 and Terashima further teaches:
the gate driving unit is further configured to reset the switch driving signal at the driving reset logic state when the pulse width modulated signal is changed from the set logic state to the reset logic state (as understood by examination of Figure 2).
For claim 43, the modified combination of Terashima and Kandah teaches the limitations of claim 41 and Terashima further teaches:
the gate driving unit is further configured to set the switch driving signal at the driving set logic state (logic high) if a first detection event indicative of the current signal flowing out of the third terminal (no overcurrent detected) and then falling substantially at zero has been identified during a first detection time window (a window large enough to detect an overcurrent event, as understood by examination of Figure 2) and the pulse width modulated signal is at the set logic state (as understood by examination of Figure 2), and wherein the first detection time window has a first window width (inherent of all time windows) and is enabled or set during the switch driving signal is at the driving reset logic state (capable of, as understood by the combination of references as cited above).
For claim 44, the modified combination of Terashima and Kandah teaches the limitations of claim 41 and Terashima further teaches:
the gate driving unit is further configured to force the switch driving signal to be set at the driving set logic state if a first detection event indicative of the current signal flowing out of the third terminal and then falling substantially at zero has neither been identified during a first detection time window nor been identified until a maximum detection time period expires (minimum time required for 1i to reach a normal operating current after 1i is off) since a moment when the pulse width modulated signal is changed from the reset logic state to the set logic state (capable of, as understood by the combination of references); and wherein the first detection time window has a first window width (inherent of all time windows) and is enabled or set during the switch driving signal is at the driving reset logic state (as understood by examination of Figure 2).
For claim 45, the modified combination of Terashima and Kandah teaches the limitations of claim 35 and Terashima further teaches:
a temperature sensing input terminal, adapted to be configured to detect a temperature reading signal (inverting input to CP3); and
wherein the gate driving unit is further configured to provide a temperature report signal having a pulse width modulated by the temperature reading signal (Soh); and wherein the gate driving unit is further configured to set the reporting signal to a first report status embodied as the temperature report signal during normal operation (as understood by examination of Figure 2).
For claim 46, the modified combination of Terashima and Kandah teaches the limitations of claim 35 and Terashima further teaches:
the gate driving unit is further configured to determine that the short circuit event is detected if the current signal is flowing into the third terminal for a predetermined short circuit detection time during the switch driving signal is at the driving set logic state (as understood by examination of Figure 2 and [0087]), or if a voltage on the third terminal goes higher than a first supply voltage on a fourth terminal of the gate driving unit during the switch driving signal is at the driving set logic state; and
wherein the gate driving unit is further configured to reset the switch driving signal at the driving reset logic state when the short circuit event is detected ([0087]).
Allowable Subject Matter
Claims 7-8, 14 and 39 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL CALRISSIAN PUENTES whose telephone number is (571)270-5070. The examiner can normally be reached M-F 9-6:30 (flex).
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/DANIEL C PUENTES/Primary Examiner, Art Unit 2836
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