CTNF 18/618,430 CTNF 73594 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restriction 18-18 REQUIREMENT FOR UNITY OF INVENTION As provided in 37 CFR 1.475(a), a national stage application shall relate to one invention only or to a group of inventions so linked as to form a single general inventive concept (“requirement of unity of invention”). Where a group of inventions is claimed in a national stage application, the requirement of unity of invention shall be fulfilled only when there is a technical relationship among those inventions involving one or more of the same or corresponding special technical features. The expression “special technical features” shall mean those technical features that define a contribution which each of the claimed inventions, considered as a whole, makes over the prior art. The determination whether a group of inventions is so linked as to form a single general inventive concept shall be made without regard to whether the inventions are claimed in separate claims or as alternatives within a single claim. See 37 CFR 1.475(e). When Claims Are Directed to Multiple Categories of Inventions: As provided in 37 CFR 1.475 (b), a national stage application containing claims to different categories of invention will be considered to have unity of invention if the claims are drawn only to one of the following combinations of categories: (1) A product and a process specially adapted for the manufacture of said product; or (2) A product and a process of use of said product; or (3) A product, a process specially adapted for the manufacture of the said product, and a use of the said product; or (4) A process and an apparatus or means specifically designed for carrying out the said process; or (5) A product, a process specially adapted for the manufacture of the said product, and an apparatus or means specifically designed for carrying out the said process. Otherwise, unity of invention might not be present. See 37 CFR 1.475 (c). 18-19 AIA Restriction is required under 35 U.S.C. 121 and 372. This application contains the following inventions or groups of inventions which are not so linked as to form a single general inventive concept under PCT Rule 13.1. In accordance with 37 CFR 1.499, applicant is required, in reply to this action, to elect a single invention to which the claims must be restricted. 18-06-01 AIA Group I , claim(s) 1-6 , drawn to an apparatus, comprising: an analog-to-digital converter circuit configured to: receive an input signal; perform an analysis of the stream of samples; change, based on a result of the analysis, a first resolution of the analog-to-digital converter circuit; and change, based on the result of the analysis, a second resolution of the filter circuit . Group II , claim(s) 7-20 , drawn to an apparatus, comprising: a receiver circuit including a front-end circuit configured to: receive an input signal; sample the input signal to generate a stream of samples that include corresponding pluralities of bits; and switch from a first operating mode to a second operating mode based on a result of the analysis, wherein a first power consumption of the front-end circuit operating in the first operating mode is less than a second power consumption of the front-end circuit operating in the second operating mode . 18-07 AIA The groups of inventions listed above do not relate to a single general inventive concept under PCT Rule 13.1 because, under PCT Rule 13.2, they lack the same or corresponding special technical features for the following reasons: Group I and II lack unity of invention because the groups do not share the same or corresponding technical feature. (i.e. switching mode for power consumption of the front-end) 08-23 AIA During a telephone conversation with Michael Runas on 4/17/2026 a provisional election was made without traverse to prosecute the invention of group II , claim s 7-20 . Affirmation of this election must be made by applicant in replying to this Office action. Claim s 1-6 withdrawn from further consideration by the examiner, 37 CFR 1.142(b), as being drawn to a non-elected invention. 08-23-02 AIA Applicant is reminded that upon the cancelation of claims to a non-elected invention, the inventorship must be corrected in compliance with 37 CFR 1.48(a) if one or more of the currently named inventors is no longer an inventor of at least one claim remaining in the application. A request to correct inventorship under 37 CFR 1.48(a) must be accompanied by an application data sheet in accordance with 37 CFR 1.76 that identifies each inventor by his or her legal name and by the processing fee required under 37 CFR 1.17(i). Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 7, 13,14 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dejanovic et al. (US 2006/0068853) in view of Rangachari et al. (US 2014/0098908) . Regarding claim 7, Dejanovic et al. discloses a method (fig. 7), comprising: receiving, by a front-end circuit (fig. 1 number 102 and P:0033) , an input signal (incoming signal)(P:0033) ; sampling, by the front-end circuit, the input signal to generate a sample (22 MHz) (i.e. incoming signal from an antenna 101 and mixes it down to an intermediate frequency (IF) which is sampled by an analog-to-digital converter (ADC) )(P:0033), each sample is a 3 bit/7 bit (P:0033 and P:0042); performing an analysis of the of sample (P:0033, P:0042 and P:0051-P:0055); and switching (turn off, sleep wake) (P:0055), by the front-end circuit (P:0051 and P:0055), from a first operating mode (sleep) to a second operating mode (wake) based on a result of the analysis (P:0051-P:0055), wherein a first power consumption of the front-end circuit operating in the first operating mode is less (i.e. sleep mode, inherent, to have less power) than a second power consumption of the front-end circuit operating in the second operating mode (wake up mode)(P:0055). Dejanovic et al. differs from claim 7 of the present invention in that it does not explicit disclose sampling, by the front-end circuit, the input signal to generate a stream of samples that include corresponding pluralities of bits. Rangachari et al. teaches a digital front-end of a digital receiver includes at least one input node positioned to receive a digital baseband signal. The digital baseband signal includes a plurality of samples at a plurality of sample instances. The plurality of samples includes at least a positive sample and a negative sample that are consecutive samples and each of the positive sample and the negative sample is represented by a first plurality of bits . (P:0006, fig. 1 number 110 and P:0018). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify Dejanovic et al. with sampling, by the front-end circuit, the input signal to generate a stream of samples that include corresponding pluralities of bits in order to analyze the input signal of the front end by the way of digital information in a continuous sequence of binary digits or bits for allowing the receiver to go into sleep mode or wake mode for optimizing its power consumption, as taught by Rangachari et al.. Regarding claims 13 and 20, Dejanovic et al. discloses the input signal includes a global navigation satellite system input signal (i.e. ephemeris download)(abstract and P:0010). Regarding claim 14, Dejanovic et al. discloses an apparatus (GPS receiver)(abstract and fig. 1) comprising: a processor circuit (receiver control block) (fig. 1 number 110 and P:0037); and a receiver circuit including a front-end circuit (fig. 1 number 102 and P:0033) configured to: receive an input signal (P:0033); sample the input signal to generate a stream of samples (each sample and/or 20 samples) that include corresponding pluralities of bits (3 bit and/or 7 bit) (P:0033, P:0042 and P:0050); send the stream of samples to the processor circuit (i.e. The output of amplifier 209 may be referred to as the analog baseband signal. ADC 210 is further coupled to receive one or more control signals from receiver control block 110 such that the sample rate of ADC 210 may be controlled)(P:0037-P:0038); performing an analysis of the stream of samples (i.e. 20 samples)(P:0033, P:0042 and P:0050); and switching (turn off, sleep wake) (P:0055), by the front-end circuit (P:0051 and P:0055), from a first operating mode (sleep) to a second operating mode (wake) based on a result of the analysis (P:0051-P:0055), wherein a first power consumption of the front-end circuit operating in the first operating mode is less (i.e. sleep mode, inherent, to have less power) than a second power consumption of the front-end circuit operating in the second operating mode (wake up mode)(P:0055) . 07-21-aia AIA Claim (s) 8 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dejanovic et al. (US 2006/0068853) in view of Rangachari et al. (US 2014/0098908) as applied to claim 7 above and in further view of Bougard (US 2009/0175381) . Regarding claim 8, the combination of Dejanovic et al. and Rangachari et al. differs from claim 8 of the present invention in that they do not explicit disclose detecting a signal blocker using the result of the analysis, and wherein switching from the first operating mode to the second operating mode includes switching from the first operating mode to the second operating mode in response to determining a signal blocker is present. Bougard teaches a digital receiver comprising a front end (abstract and P:0057-P:0058), where the sequence of operation occurring at the reception of a blocker signal (false trigger) is depicted in FIG. 8. Although an AGC_done signal is generated and the filter, buffer and synchronization processor are activated , no synchronization point is found and hence, the `sync` signal is not asserted. Filter, buffer and synchronization processor are forced back to sleep mode after a time-out occurs at time index 31025 ns. The state flow is again appended to FIG. 8 and the energy spent in the false trigger event is computed similarly, giving 300 nJ. The average power during the false trigger event is 15.2 mW. Therefore, in field operation where false trigger occurs with probability p, the consumption of the DFE (P:0095) . Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the combination of Dejanovic et al. and Rangachari et al. with detecting a signal blocker using the result of the analysis, and wherein switching from the first operating mode to the second operating mode includes switching from the first operating mode to the second operating mode in response to determining a signal blocker is present in order to prevent the receiver from falsely activating/deactivating the front-end by sampling a false input signal sent from the satellite which saves the receivers battery power, as taught Bougard. Regarding claim 10, the combination of Dejanovic et al. and Rangachari et al. differs from claim 10 of the present invention in that they do not explicit disclose switching from the second operating mode to the first operating mode in response to determining the blocker is no longer present. Bougard teaches a digital receiver comprising a front end (abstract and P:0057-P:0058), where the sequence of operation occurring at the reception of a blocker signal (false trigger) is depicted in FIG. 8. Although an AGC done signal is generated and the filter, buffer and synchronization processor are activated , no synchronization point is found and hence, the `sync` signal is not asserted. Filter, buffer and synchronization processor are forced back to sleep mode after a time-out occurs at time index 31025 ns. Bougard does not teach switching from the second operating mode to the first operating mode in response to determining the blocker is no longer present, however, one of ordinary skill in the art would switch from a sleep mode to an activation mode when there is no false signal and/or a good signal received. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the combination of Dejanovic et al. and Rangachari et al. with switching from the second operating mode to the first operating mode in response to determining the blocker is no longer present in order for the receiver to switch from sleep mode to activation mode when a good signal is received from the satellite, as taught by Bougard . 07-21-aia AIA Claim (s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dejanovic et al. (US 2006/0068853) in view of Rangachari et al. (US 2014/0098908) and Bougard (US 2009/0175381) as applied to claims 7,8 and 10 above and in further view of Tier (CN 102141626 A) . Regarding claim 11, the combination of Dejanovic et al., Rangachari et al. and Bougard differs from claim 11 of the present invention in that they do not explicit disclose decreasing a first resolution of the analog-to-digital converter circuit; and decreasing a second resolution of the filter circuit. Tier teaches for example, US 2008 /0M0315 describes a method and circuit for interference suppression. filter can be a part of the RF front end or a portion of baseband processing. digital filter of this type can be adaptive. i.e., can analyze the signal after sampling to determine whether interference exists, if there is interference, the measurement characteristic of the interference (e.g., frequency or power). Thus, the digital filter can automatically adapt, to optionally removing or attenuating interference. at the higher sampling rate (such as the output of the analog-to-digital converter) to filter, then the filtered signal samples is reduced to lower the frequency (or bit resolution , or both) after storage or processing thereof, may be particularly advantageous. if the sample is stored, so as to reduce the storage capacity and the memory interface of the throughput requirement. if the sample is immediately processed, reducing the sampling rate or resolution reduction can reduce the complexity of the power consumption and/or processing hardware . Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the Dejanovic et al., Rangachari et al. and Bougard with decreasing a first resolution of the analog-to-digital converter circuit; and decreasing a second resolution of the filter circuit in order to prevent the receiver from falsely activating/deactivating the front-end by sampling a false input signal which would reduce the complexity of the power consumption from the signal sent from the satellite which saves the receivers battery power, as taught by Tier . 07-21-aia AIA Claim (s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dejanovic et al. (US 2006/0068853) in view of Rangachari et al. (US 2014/0098908) and Bougard (US 2009/0175381) as applied to claims 7 and 8 above and in further view of Greenberger et al. (US 2021/0211981) . Regarding claim 9, the combination of Dejanovic et al., Rangachari et al. and Bougard differs from claim 9 of the present invention in that they do not explicit disclose increasing at least one of a first resolution of the analog-to-digital converter circuit or a second resolution of the filter circuit. Greenberger et al. teaches the UE may increase an effective number of bits that the ADC may use, corresponding to an increase of an effective resolution of the ADC (P:0175). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the combination of Dejanovic et al., Rangachari et al. and Bougard with increasing at least one of a first resolution of the analog-to-digital converter circuit or a second resolution of the filter circuit in order to reduce the power of head end by putting the analog-to-digital converter to sleep when detecting a false signal, as taught by Greenberger et al .. 07-21-aia AIA Claim (s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dejanovic et al. (US 2006/0068853) in view of Rangachari et al. (US 2014/0098908) and Bougard (US 2009/0175381) as applied to claims 7 and 8 above and in further view of Hosseini et al. (US 2025/0158867) . Regarding claim 12, the combination of Dejanovic et al., Rangachari et al. and Bougard differs from claim 12 of the present invention in that they do not explicit disclose monitoring a number of clipped samples within a particular period of time; and performing a comparison of the number of clipped samples to a threshold value. Hosseini et al. teaches applying a first phase ramp function to the set of multiple samples after the first transformation and performing a second transformation of the set of multiple samples from the frequency domain to the time domain , where each sample of the set of multiple samples may be shifted in the time domain based on applying the first phase ramp function, and where comparing the set of multiple samples to the clipping threshold may be based on the second transformation (P:0032) and one or more processors may individually or collectively operable to execute the code to cause the wireless communication device to sample a wireless communication signal in accordance with a sampling rate, compare a set of multiple samples to a clipping threshold , where the set of multiple samples are obtained in accordance with the sampling, generate, based on the comparing, a set of values including one or more first values and one or more second values, where each first value of the one or more first values is associated with an error margin between a respective sample of the set of multiple samples and the clipping threshold (P:0024). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the combination of Dejanovic et al., Rangachari et al. and Bougard with monitoring a number of clipped samples within a particular period of time; and performing a comparison of the number of clipped samples to a threshold value in order for the receiver to monitor the sample input clipped signal for a specific time period for errors to determine if there is a false signal before activating/deactivating the front-end from which would save the receivers battery power, as taught by Hosseini et al .. 07-21-aia AIA 4 . Claim (s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dejanovic et al. (US 2006/0068853) in view of Rangachari et al. (US 2014/0098908) as applied to claim 14 above and in further view of Hosseini et al. (US 2025/0158867) . Regarding claim 19, the combination of Dejanovic et al. and Rangachari et al. differs from claim 19 of the present invention in that they do not explicit disclose monitoring a number of clipped samples within a particular period of time; and performing a comparison of the number of clipped samples to a threshold value. Hosseini et al. teaches applying a first phase ramp function to the set of multiple samples after the first transformation and performing a second transformation of the set of multiple samples from the frequency domain to the time domain, where each sample of the set of multiple samples may be shifted in the time domain based on applying the first phase ramp function, and where comparing the set of multiple samples to the clipping threshold may be based on the second transformation (P:0032) and one or more processors may individually or collectively operable to execute the code to cause the wireless communication device to sample a wireless communication signal in accordance with a sampling rate, compare a set of multiple samples to a clipping threshold, where the set of multiple samples are obtained in accordance with the sampling, generate, based on the comparing, a set of values including one or more first values and one or more second values, where each first value of the one or more first values is associated with an error margin between a respective sample of the set of multiple samples and the clipping threshold (P:0024). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the combination of Dejanovic et al. and Rangachari et al. with monitoring a number of clipped samples within a particular period of time; and performing a comparison of the number of clipped samples to a threshold value in order for the receiver to monitor the sample input clipped signal for a specific time period for errors to determine if there is a false signal before activating/deactivating the front-end from which would save the receivers battery power, as taught by Hosseini et al .. Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 15-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding claim 15, the prior art of record fails to teach or suggest alone, or in combination to perform the analysis of the stream of samples, the receiver circuit is further configured to predict, at a particular point in time, a value of an overflow using a subset of the stream of samples received prior to the particular point in time, wherein the front-end circuit is further configured to detect a signal blocker using the result of the analysis, and wherein to switch from the first operating mode to the second operating mode, the front-end circuit is further configured to switch from the first operating mode to the second operating mode in response to a determination that a blocker is interfering with the input signal. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEITH FERGUSON whose telephone number is (571)272-7865. The examiner can normally be reached M-F 7 am -3 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wesley L Kim can be reached at (571) 272-7867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KEITH FERGUSON/Primary Examiner, Art Unit 2648 Application/Control Number: 18/618,430 Page 2 Art Unit: 2648 Application/Control Number: 18/618,430 Page 3 Art Unit: 2648 Application/Control Number: 18/618,430 Page 4 Art Unit: 2648 Application/Control Number: 18/618,430 Page 5 Art Unit: 2648 Application/Control Number: 18/618,430 Page 6 Art Unit: 2648 Application/Control Number: 18/618,430 Page 7 Art Unit: 2648 Application/Control Number: 18/618,430 Page 8 Art Unit: 2648 Application/Control Number: 18/618,430 Page 9 Art Unit: 2648 Application/Control Number: 18/618,430 Page 10 Art Unit: 2648 Application/Control Number: 18/618,430 Page 11 Art Unit: 2648 Application/Control Number: 18/618,430 Page 12 Art Unit: 2648
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