DETAILED ACTION
This communication is in response to the application filed on February 18, 2026 in which claims 1-16 and 21-24 are pending in the application. Claims 1, 11, and 21 are in independent form.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Final Office Action is in response to the applicant’s remarks and arguments filed on February 18, 2026.
Claims 17-20 were previously canceled. Claims 1, 6-8, 11 and 15-16 were amended.
Claims 21-24 were added.
Claims 1-16 and 21-24 remain pending in the application. Claims1-16 and 21-24 are being considered on the merits.
The objection to the drawings, previously set forth in the Non-Final Office Action mailed on November 5, 2025, has been withdrawn due the amendment to the specification filed February 18, 2026.
Response to Arguments
The applicant’s remarks and/or arguments, filed on February 18, 2026 have been fully considered with the following result(s).
The examiner is entitled to give claim limitations their broadest reasonable interpretation in light of the specification. See MPEP 2111 [R-1] Interpretation of Claims-Broadest Reasonable Interpretation. The applicant always has the opportunity to amend the claims during prosecution, and broad interpretation by the examiner reduces the possibility that the claim, once issued, will be interpreted more broadly than is justified. In re Prater, 162 USPQ 541,550-51 (CCPA 1969).
Applicant's arguments in the applicant’s remarks and amendments of independent claims 1-5 and 10-13, found on pages 10-12 and filed on 2/18/2026, have been fully considered and are persuasive. Therefore, the previous claim(s) rejection under 35 U.S.C 102 has been withdrawn.
However, upon further consideration, a new ground(s) of rejection is made in view of a newly found prior art: (US A1) issued to , and in view of the previously cited prior art(s) SUMBUL. Reference Chajdas discloses each of the hardware compute nodes comprising a hierarchy of compute elements configured to process data based on a dataflow through the hierarchy of compute elements [Para [0007]-[0009], [0015]-[0022], [0026], Each processor has a hierarchy of scheduling domains (e.g., scheduler circuits, workgroup processing elements), which process work graphs (dataflow)].
- For further details, please see below claims rejections under 35 USC 103.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 10-13, 21-22 and 24 is/are rejected under 35 U.S.C. 103 as being obvious over SUMBUL et al., US Patent Application Number 20200026498 (herein “SUMBUL”) and Chajdas et al. (US 20240111578 A1).
The applied reference has a common [assignee] with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
Regarding independent claim 1, SUMBUL discloses a system (FIG. 8, system 800) comprising:
one or more switches (FIG. 8, switches 872 in fabric 870); and
a plurality of hardware compute nodes (FIG. 8, nodes 830 with processors 832) connected via the one or more switches (FIG. 8, switches 872), each hardware compute node of the plurality of hardware compute nodes (FIG. 8, nodes 830, each node 830 may have Compute-in-Memory CIM 842 with memory 840, which is implemented as system 100 in FIG. 1) comprising:
an in-memory compute element configured to perform in-memory processing operations on data (FIG. 1, bottom Compute-Near-Memory CNM 120, with its MAC array 134 may be considered as an in-memory compute element for processing data in its own locality);
a near-memory compute element configured to perform near-memory processing operations on the data (FIG. 1, middle box Compute-Near-Memory CNM 120 may be considered as a near-memory compute element, which is away from the bottom CNM 120. [0038] “CNMs 120 include input buffer (In Buff) 124 for downstream communication and include output buffer (Out Buff) 126 for upstream communication. Downstream communication refers to communication from common node 110 to the CNM cores, or from a CNM core closer to common node 110 to a CNM core farther from common node 110.” E.g. “in-memory” or “near-memory” are defined based on relative distance of compute core from the data location); and
a far-memory compute element configured to perform far-memory processing operations on the data (FIG. 1, far memory 112 with controller 114 may be considered as far-memory compute element performs far-memory processing operations, such as moving data (X, Y)).
SUMBUL further discloses a compute near memory circuit more specifically refers to a CIM circuit where the memory is a near memory of a multilevel memory architecture [Para 0025].
SUMBUL discloses the invention as detailed above but does not specifically teach each of the hardware compute nodes comprising a hierarchy of compute elements configured to process data based on a dataflow through the hierarchy of compute elements as recited in the claim.
Chajdas discloses each of the hardware compute nodes comprising a hierarchy of compute elements configured to process data based on a dataflow through the hierarchy of compute elements [Para [0007]-[0009], [0015]-[0022], [0026], Each processor has a hierarchy of scheduling domains (e.g., scheduler circuits, workgroup processing elements), which process work graphs (dataflow)].
SUMBUL and Chajdas are in the same field of endeavor as they are both in the resource processing art and, therefore, are combinable/modifiable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the teachings of SUMBUL with the teachings of Chajdas in order to enable hardware compute nodes comprising a hierarchy of compute elements configured to process data based on a dataflow through the hierarchy of compute elements.
Modification would enable an improved scheduling of complex graphs so that the scheduling capacity of complex graphs scales with chip size while keeping data movement minimal as taught by Chajdas (Para 0008).
Regarding claim 2, SUMBUL discloses the system of claim 1, further comprising a circuit board having memory mounted to the circuit board, the circuit board comprising: the in-memory compute element; and one or more dynamic random-access memory banks (FIG. 1, [0046] “In one example, system 100 is integrated on a common die with the host processor, where CNM 120 and its associated memory and MAC units are part of a hardware acceleration circuit. Rather than being integrated on a host processor die, the array of CNM 120 can be integrated on a hardware accelerator die that is either incorporated on a common substrate or motherboard with the host processor, or is included in a system on a chip with the host processor.” [0043] “Near memory 130 includes an array of memory cells or bitcells. In one example, the array is based on a dynamic random access memory (DRAM) technology.”).
Regarding claim 3, SUMBUL discloses the system of claim 2, wherein the in-memory compute element comprises a processing-in-memory component (FIG. 1, bottom box CNM 120 as in-memory compute element include MAC array 134, [0046] “In one example, system 100 is integrated on a common die with the host processor, where CNM 120 and its associated memory and MAC units are part of a hardware acceleration circuit. Rather than being integrated on a host processor die, the array of CNM 120 can be integrated on a hardware accelerator die that is either incorporated on a common substrate or motherboard with the host processor, or is included in a system on a chip with the host processor.” E.g. multiply-accumulate (MAC) units, as compute elements are integrated with memory components, thus a processing-in-memory component).
Regarding claim 4, SUMBUL discloses the system of claim 3, further comprising a memory controller, the memory controller comprising the near-memory compute element (FIG. 1, middle box CNM 120 may be considered a memory controller with a near-memory compute element, as it can control and channel command and data in and out of memory 130, through 122, 124, 126, 128).
Regarding claim 5, SUMBUL discloses the system of claim 4, wherein the near-memory compute element comprises a near-memory processor (FIG. 1, middle box CNM 120 include a MAC array 134 which performs multiply-accumulate (MAC) operations, can be a near-memory processor), and
the memory controller further comprises a traffic manager configured to direct traffic towards the near-memory processor, the processing-in-memory component, or the one or more dynamic random-access memory banks (FIG. 1, middle box CNM 120 include CMD 122, IN BUFF 124, OUT BUFF 126, and MUX 128, which may be considered as a traffic manager to direct traffic toward middle box MAC array 134, or to bottom box CNM 120’s MAC array 134, or to far memory 112 which may be a DRAM, see [0043]).
Regarding claim 10, SUMBUL discloses the system of claim 1, wherein the data comprises graph data (This limitation recites intended use language, and does not alter the functions or structures recited in claim 1. Therefore, SUMBUL discloses all the functions and structures as recited in claim 10. Additionally, there is no special definition for “graph data” in the present application. Thus, SUMBUL discloses [0023] “GPU (graphics processing unit) hardware”, e.g. data being processed may be graphics data, graph data).
Regarding independent claim 11, the applicant is directed to the rejections to claim 1 set forth above, as they are rejected based on the same rationale.
Regarding claim 12, the applicant is directed to the rejections to claim 2 set forth above, as they are rejected based on the same rationale.
Regarding claim 13, the applicant is directed to the rejections to claim 3 set forth above, as they are rejected based on the same rationale.
Regarding independent claim 21, the applicant is directed to the rejections to claim 1 set forth above, as they are rejected based on the same rationale.
Regarding claim 22, Chajdas discloses the method of claim 21, wherein the in-memory compute element is included on a dynamic random-access memory module [Para 0047, CNM core 210 represents a CNM unit or CNM core in accordance with CNM 120 of FIG. 1. In one example, CNM 210 can be integrated with a larger memory, such as an SRAM (static random access memory), DRAM (dynamic random access memory), or other type of memory.]
Regarding claim 24, Chajdas discloses the method of claim 21, further comprising receiving directives specifying respective compute elements for performing operations on the data [Para 0008, FIGS. 1-4 describe systems and methods for hierarchical work scheduling that includes scheduler circuits executing graphs locally].
Claim(s) 23 is/are rejected under 35 U.S.C. 103 as being obvious over SUMBUL et al., US Patent Application Number 20200026498 (herein “SUMBUL”) and Chajdas et al. (US 20240111578 A1) and Windh et al. (US 11604650 B1).
As per claim 23, the combination of SUMBUL and Chajdas discloses the invention as detailed above for claim 21. The combination does not specifically teach the method of claim 21, wherein the near-memory compute element is included in a memory controller.
Windh teaches the near-memory compute element is included in a memory controller [Para 31, The CNM system 102 can include a global controller for the various nodes in the system, or a particular memory-compute node in the system can optionally serve as a host or controller to one or multiple other memory-compute nodes in the same system. The various nodes in the CNM system 102 can thus be similarly or differently configured.]
SUMBUL and Chajdas and Windh are in the same field of endeavor as they are both in the resource processing art and, therefore, are combinable/modifiable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the teachings of SUMBUL and Chajdas with the teachings of Windh in order to enable the near-memory compute element to be included in a memory controller.
Modification would enable topologies can be used to facilitate low-latency compute near, or inside of, memory or other data storage elements as taught by Windh (Para 17).
Allowable Subject Matter
Claims 6-9 and 14-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
None of the cited references discloses or suggests the unlined features of claim 6 below.
Claim 6: the system of claim 5, wherein the traffic manager comprises:
a data queue configured to queue the data;
a demand request queue configured to queue demand requests from the traffic;
a compute everywhere processing hierarchy (CEPH) request queue configured to queue CEPH requests from the traffic; and
a request arbitration logic configured to:
direct native commands associated with the demand requests towards the memory;
direct processing-in-memory commands associated the CEPH requests towards the processing-in-memory component to perform the in-memory processing operations on the data; and
direct near-memory processing commands associated with the CEPH requests towards the near-memory processor to perform the near-memory processing operations on the data.
Claim 14 recites similar allowable features as claim 6 above, as well as reciting additional features.
Claims 7-9 and 15-16 contain allowable features as dependent upon claims 6 and 14, as well as reciting additional features.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
CN 116257469 A (Mathew et al.) describes a DIMM with RAM and a near-memory processing (NMP) circuit, which executes commands from the host and accesses RAM ([Abstract], [Description], [Fig. 4], [Claims 1, 17]). There is a separation between host (far), NMP circuit (near) and RAM.
CN 118550697 A (Fan et al.) discloses a hierarchy of near-memory compute elements (DPE, RPE, BGPE) in buffer chip on DIMM, and a far-memory host CPU.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Examiner has cited particular columns/paragraphs/sections and line numbers in the references applied and not relied upon to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
When responding to the Office action, applicant is advised to clearly point out the patentable novelty the claims present in view of the state of the art disclosed by the reference(s) cited or the objections made. A showing of how the amendments avoid such references or objections must also be present. See 37 C.F.R. 1.111(c).
When responding to this Office action, applicant is advised to provide the line and page numbers in the application and/or reference(s) cited to assist in locating the appropriate paragraphs.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Pierre M. Vital whose telephone number is (571)272-4215. The examiner can normally be reached Mon-Fri, 8:00a-4:00p.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dede Zecher can be reached at (571) 272-7771. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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June 1, 2026
/PIERRE VITAL/Supervisory Patent Examiner, Art Unit 2198
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