DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species I in the reply filed on 7/14/2026 is acknowledged. The traversal is on the ground(s) that “no ‘serious’ is present in examining claims 11-16”. This is not found persuasive because there is a serious burden to examination of both Species I and Species II, since Species II includes mutually exclusive circuitry such as AC current source 210B and the circuitry of 232, 234, 236, 238, 240, 242, 246 and 244 of Fig. 8 which is note included within the circuitry of species I. Therefore, Species II requires a different field of search (e.g., searching different classes/subclasses or electronic resources, or employing different search strategies or search queries) and thus provides a serious burden on examination.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-6 and 9-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Melanson et al. (USPN 9,521,712).
With respect to claim 1, Melanson et al. discloses, in Fig. 4, a semiconductor integrated circuit (Fig. 4), comprising:
a set pin (410) connected to an external resistor (412) and an external capacitor (414), wherein the external resistor and the external capacitor are connected in parallel and disposed between the set pin and an external fixed voltage line (412 connected in parallel between 410 and the external ground connections); and
a parameter acquisition circuit (406 with 408), connected to the set pin and configured to acquire a first parameter (resistance of 412/maximum voltage on 410, e.g., Vref1, see Col. 8 lines 40-65 and Fig. 5) and a second parameter (resistance 414/timing of the increase of the voltage on 410 to a specified level, see Col. 9 line 2-28 and Fig. 5) defined by a resistive value of the external resistor and a capacitive value of the external capacitor (the above parameters are defined by the resistance and capacitance values of 412 and 414).
With respect to claim 2, the semiconductor integrated circuit of Claim 1, wherein the parameter acquisition circuit includes:
a current source (404), configured to supply a current to the set pin (Iref/Ir1, see Col. 8 lines 45-50 and Col. 9 lines 6-7);
a measurement circuit, configured to obtain the first parameter and the second parameter based on a waveform of a voltage generated at the set pin (406 with 408, see Col. 9 lines 10-14 and/or the comparators of Col. 8 liens 49-54 and Col. 9 lines 15-19).
With respect to claim 3, the semiconductor integrated circuit of Claim 2, wherein the current is a constant current in direct current (Iref at the Ir1 level is a constant DC current in order to properly charge the pin).
With respect to claim 4, the semiconductor integrated circuit of Claim 3, wherein the measurement circuit is configured to obtain the first parameter according to a peak level of the voltage generated at the set pin (peak/maximum voltage of Vref1 at the pin that causes triggering of the comparator/406).
With respect to claim 5, the semiconductor integrated circuit of Claim 3, wherein the measurement circuit is configured to obtain the second parameter based on a time (see Tref of Fig. 5) for the voltage generated at the set pin to reach a threshold value (0.63 times Vref1) obtained by multiplying a peak level (Vref1 which is the peak/maximum voltage that triggers the comparator/406) by a predetermined coefficient (0.63, see Col. 9 lines 2-27).
With respect to claim 6, the semiconductor integrated circuit of Claim 4, wherein the measurement circuit is configured to obtain the second parameter based on a time (see Tref of Fig. 5) for the voltage generated at the set pin to reach a threshold value (0.63 times Vref1) obtained by multiplying a peak level (Vref1 which is the peak/maximum voltage that triggers the comparator/406) by a predetermined coefficient (0.63, see Col. 9 lines 2-27).
With respect to claim 9, the semiconductor integrated circuit of Claim 3, wherein the measurement circuit includes:
an A/D converter (406); and
a digital processing circuit, configured to process an output of the A/D converter (408).
With respect to claim 10, the semiconductor integrated circuit of Claim 4, wherein the measurement circuit includes:
an A/D converter (406); and
a digital processing circuit, configured to process an output of the A/D converter (408).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Melanson et al. (USPN 9,521,712) in view of Rumreich (USPN 5,760,729)
With respect to claim 7, Melanson et al. discloses that the measurement circuit includes, among other things, an analog to digital converter (ADC) (406). Melanson et al. fails to disclose the specifics of how the ADC is constructed. Furthermore, Melanson et al. fails to disclose “wherein the measurement circuit includes:
a plurality of comparators, configured to compare the voltage generated at the set pin with different thresholds; and
a decoder circuit, configured to process outputs of the plurality of comparators.”
However, it is old and well-known to construct an ADC using a plurality of comparators that compare the input voltage of the ADC to a plurality of different threshold voltages and a decode to further process the outputs of the plurality of comparators.
Rumreich discloses, in Fig. 2, such an ADC comprising:
a plurality of comparators (C1-C26), configured to compare the voltage generated at the set pin (i.e., ANALOGE VOLTAGE at the input of the ADC) with different thresholds (thresholds set by 30, 80, 81 and each R2 of 50); and
a decoder circuit, configured to process outputs of the plurality of comparators (70).
The ADC of Fig. 2 has a decreased circuit size/area (see Col. 5 lines 1-14).
It would have been obvious to replace the generic ADC 406 of Melanson et al. with the specific ADC of Fig. 2 of Rumreich for the purpose of, among other things, having a specific ADC with a small/decreased circuit size.
With respect to claim 8, Melanson et al. discloses that the measurement circuit includes, among other things, an analog to digital converter (ADC) (406). Melanson et al. fails to disclose the specifics of how the ADC is constructed. Furthermore, Melanson et al. fails to disclose “wherein the measurement circuit includes:
a plurality of comparators, configured to compare the voltage generated at the set pin with different thresholds; and
a decoder circuit, configured to process outputs of the plurality of comparators.”
However, it is old and well-known to construct an ADC using a plurality of comparators that compare the input voltage of the ADC to a plurality of different threshold voltages and a decode to further process the outputs of the plurality of comparators.
Rumreich discloses, in Fig. 2, such an ADC comprising:
a plurality of comparators (C1-C26), configured to compare the voltage generated at the set pin (i.e., ANALOGE VOLTAGE at the input of the ADC) with different thresholds (thresholds set by 30, 80, 81 and each R2 of 50); and
a decoder circuit, configured to process outputs of the plurality of comparators (70).
The ADC of Fig. 2 has a decreased circuit size/area (see Col. 5 lines 1-14).
It would have been obvious to replace the generic ADC 406 of Melanson et al. with the specific ADC of Fig. 2 of Rumreich for the purpose of, among other things, having a specific ADC with a small/decreased circuit size.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thomas J. Hiltunen whose telephone number is (571)272-5525. The examiner can normally be reached 9:00AM-5:30PM EST M-F.
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/THOMAS J. HILTUNEN/ Primary Examiner, Art Unit 2836
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