CTNF 18/618,504 CTNF 86248 DETAILED ACTION This is the initial Office action based on the application filed March 27, 2024. Claims 1-20 are pending and have been examined. Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1-4, 12, 13, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Evans (US 2024/0020289) in view of Mody (US 2023/0385114) . Regarding claim 1, Evans discloses: responsive to receiving a request from a computing unit of a processor to export a payload, determining, by the processor, whether a bucket for sorting the payload is available based on a first key included in the request; and responsive to determining a bucket is available, […] comprising an indication of the bucket (see at least paragraph 52, hash table with a plurality of buckets with storage locations, selecting a bucket using the has value from the key data and hash function, data storage locations within the bucket are checked to determine the write-availability indicating it is available to be written to; figure 4; paragraph 70, receiver receives key data, process received data) However, Evans does not explicitly disclose, but Mody discloses: sending, by the processor, a response to the compute unit comprising an indication (see at least paragraph 48, notification of task completion, notifications data is ready; paragraph 24, exchanging notifications) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Evans by adapting the teachings of Mody to include sending notifications relating to task completion. The combination allows information associated with the task to be completed to be passed along as well as notifying other processes that the task is completed which allows for pipelined processing capabilities (Mody ¶24). Regarding claim 2, the rejection of claim 1 is incorporated, and Evans further discloses: wherein the indication comprises a virtual address associated with the bucket at which the compute unit is to write the payload (see at least paragraph 75, each of the buckets has as associated memory address, selecting a bucket within the hash table data structure to store received data, memory address of the selected bucket provided by h1) Regarding claim 3, the rejection of claim 1 is incorporated, and Evans further discloses: wherein the indication prompts the compute unit to store the payload in the bucket (see at least paragraph 54, data is written to selected data storage location; figure 4) Regarding claim 4, the rejection of claim 1 is incorporated, and Evans further discloses: […] indicating the compute unit has completed storing the payload in the bucket (see at least paragraph 83, write key data into data storage location) However, Evans does not explicitly disclose, but Mody discloses: receiving, by the processor, a notification from the compute unit (see at least paragraph 48, notification of task completion, notifications data is ready; paragraph 24, exchanging notifications) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Evans by adapting the teachings of Mody to include sending notifications relating to task completion. The combination allows information associated with the task to be completed to be passed along as well as notifying other processes that the task is completed which allows for pipelined processing capabilities (Mody ¶24). Regarding claim 12, Evans discloses: A processor (see at least paragraph 42, processor; paragraph 97, GPU) , comprising: and a sorting circuit configured to: responsive to a request received from a compute unit of the one or more compute units to export a payload, determine if a bucket for sorting the payload is available based on a first key included in the request; and responsive to a bucket being available, […] comprising an indication of the bucket (see at least paragraph 52, hash table with a plurality of buckets with storage locations, selecting a bucket using the has value from the key data and hash function, data storage locations within the bucket are checked to determine the write-availability indicating it is available to be written to; figure 4; paragraph 70, receiver receives key data, process received data) However, Evans does not explicitly disclose, but Mody discloses: a plurality of processing elements each comprising one or more compute units; (see at least figures 2 and 3) send a response to the compute unit (see at least paragraph 48, notification of task completion, notifications data is ready; paragraph 24, exchanging notifications) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Evans by adapting the teachings of Mody to include sending notifications relating to task completion as well as a plurality of processing elements. The combination allows information associated with the task to be completed to be passed along as well as notifying other processes that the task is completed which allows for pipelined processing capabilities (Mody ¶24). Regarding claim 20, Evans discloses: a processor; memory (see at least paragraph 42, processor and memory; paragraph 97, GPU) ; and a sorting circuit configured to: responsive to a request received from a compute unit of the plurality of compute units to export a payload, determine if a bucket for sorting the payload is available based on a first key included in the request; and responsive to a bucket being available, […] comprising an indication of the bucket (see at least paragraph 52, hash table with a plurality of buckets with storage locations, selecting a bucket using the has value from the key data and hash function, data storage locations within the bucket are checked to determine the write-availability indicating it is available to be written to; figure 4; paragraph 70, receiver receives key data, process received data) However, Evans does not explicitly disclose, but Mody discloses: a plurality of scheduling domains, each scheduling domain of the plurality of scheduling domains comprising at least one local scheduler circuit and one or more workgroup processing elements comprising a plurality of compute units (see at least figures 2 and 3; paragraph 30, configure the accelerators into any order) ; send a response to the compute unit (see at least paragraph 48, notification of task completion, notifications data is ready; paragraph 24, exchanging notifications) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Evans by adapting the teachings of Mody to include sending notifications relating to task completion as well as scheduler circuitry. The combination allows information associated with the task to be completed to be passed along as well as notifying other processes that the task is completed which allows for pipelined processing capabilities (Mody ¶24). Regarding claim 13, the scope of the instant claim does not differ substantially from that of claim 2 and is rejected for the same reasons . 07-21-aia AIA Claim s 5-8 and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Evans (US 2024/0020289), Mody (US 2023/0385114), and further in view of Wysoczanski (US 2019/0042146) . Regarding claim 5, the rejection of claim 4 is incorporated, and Evans further discloses: responsive to receiving the notification from the compute unit, determining, by the processor, the bucket is full; and (see at least paragraph 73, bucket is fully populated) However, Evans does not explicitly disclose, but Mody discloses: a scheduler circuit (see at least figure 2) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Evans by adapting the teachings of Mody to include a scheduler circuit. The combination allows for concurrently handling and processing data in a more efficient manner (¶Mody ¶8). However, Evans and Mody do not explicitly disclose, but Wysoczanski discloses: responsive to determining the bucket is full, notifying, by the processor, a […] circuit of the processor that payloads in the bucket are ready for scheduling (see at least paragraph 97, flush processing transfers a full bucket for processing) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Evans and Mody by adapting the teachings of Wysoczanski to include flush processing. The combination allows for processing of data which increases predictability and reliability/data integrity of the system. Regarding claim 6, the rejection of claim 5 is incorporated, and Evans further discloses: scheduling, by the scheduler circuit, the payloads for execution by one or more of compute units of a processing element of the processor (see at least paragraph 84, data retrieved and processed with predetermined operation) Regarding claim 7, the rejection of claim 5 is incorporated. However, Evans and Wysoczanski do not explicitly disclose, but Mody discloses: wherein notifying the scheduler circuit comprises: notifying a local scheduler circuit coupled to a plurality of processing elements of the processor (see at least figure 2, scheduler circuit 210 coupled to accelerators 260, 262, 264; paragraph 24, exchanging notifications; paragraph 30, configure the accelerators into any order) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Evans , Mody , and Wysoczanski for the reasons listed above. Regarding claim 8, the rejection of claim 5 is incorporated. However, Evans and Wysoczanski do not explicitly disclose, but Mody discloses: wherein notifying the scheduler circuit comprises: notifying at least one local scheduler circuit of a plurality of local scheduler circuits each coupled to a different processing element of the processor (see at least figure 2, schedulers 240, 242, 244 coupled to accelerators 260, 262, 264; paragraph 24, exchanging notifications; paragraph 30, configure the accelerators into any order) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Evans , Mody , and Wysoczanski for the reasons listed above. Regarding claim 14, the scope of the instant claim does not differ substantially from that of claims 4 and 5 and is rejected for the same reasons. Regarding claim 15, the scope of the instant claim does not differ substantially from that of claim 6 and is rejected for the same reasons. Regarding claim 16, the scope of the instant claim does not differ substantially from that of claims 7 and 8 and is rejected for the same reasons . 07-21-aia AIA Claim s 9-11 and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Evans (US 2024/0020289), Mody (US 2023/0385114), and further in view of Khorasani ( Stadium Hashing: Scalable and Flexible Hashing on GPUs ) . Regarding claim 9, the rejection of claim 1 is incorporated. However, Evans and Mody do not explicitly disclose, but Khorasani discloses: wherein determining if a bucket is available comprises: searching, by the processor, a data structure mapping key-slot pairs to a plurality of buckets; and responsive to searching the data structure, determining, by the processor, a bucket of the plurality of buckets is available based on a slot in the data structure comprising a second key matching the first key; or responsive to searching the data structure, determining, by the processor, the plurality of buckets is unavailable based on each slot in the data structure failing to be associated with a second key matching the first key (see at least page 65, section 3, paragraph 2, a ticket board that maintains a ticket for every bucket in the table which consists of an availability bit that indicates the occupancy status of the table bucket and info bits generated from the key, availability bit of 1 indicates the bucket is empty and an availability bit of 0 means it has already been reserved or occupied) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Evans and Mody by adapting the teachings of Khorasani to include hashing on a GPU including a separate ticket-board data structure. The combination allows for improved hashing performance in GPUs (Khorasani p64, ¶2). Regarding claim 10, the rejection of claim 9 is incorporated. However, Evans and Mody do not explicitly disclose, but Khorasani discloses: responsive to determining the plurality of buckets is unavailable, selecting a slot from the data structure currently unmapped to a bucket; and associating the selected slot with a second key matching the first key and further associating the selected slot with a virtual address associated with an available bucket, wherein sending the response to the compute unit is in response associating the selected slot with the second key and the virtual address (see at least page 65, right column, paragraph 2, otherwise [when the availability bit is 0] the bucket has already been in use and the thread must rehash the location of the ticket in the ticket-board is incremented recursively) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Evans , Mody , and Khorasani for the reasons listed above. Regarding claim 11, the rejection of claim 9 is incorporated. However, Evans does not explicitly disclose, but Mody discloses: notifying, by the processor, a scheduler circuit of the processor that payloads in the bucket are ready for scheduling (see at least paragraph 48, notification of task completion, notifications data is ready; paragraph 24, exchanging notifications) ; It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Evans by adapting the teachings of Mody to include sending notifications relating to task completion. The combination allows information associated with the task to be completed to be passed along as well as notifying other processes that the task is completed which allows for pipelined processing capabilities (Mody ¶24). However, Evans and Mody do not explicitly disclose, but Khorasani discloses: responsive to determining the plurality of buckets is unavailable, selecting a slot from the data structure currently mapped to a bucket of the plurality of buckets; clearing, by the processor, the selected slot; […] and associating the selected slot with a second key matching the first key and further associating the selected slot with a virtual address associated with an available bucket, wherein sending the response to the compute unit is in response associating the selected slot with the second key and the virtual address (see at least page 64, right column, paragraph 2, insertion and eviction of key-value pairs) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Evans , Mody , and Khorasani for the reasons listed above. Regarding claims 17-19, the scope of the instant claim does not differ substantially from that of claims 9-11 and are rejected for the same reasons, respectively . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Zhou discloses GPU acceleration of hash tables . Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIMBERLY L JORDAN whose telephone number is (571)270-5481. The examiner can normally be reached Monday, Tuesday, and Thursday 9am-3pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kevin Young can be reached on (571) 270-3180. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KIMBERLY L JORDAN/Examiner, Art Unit 2194 Application/Control Number: 18/618,504 Page 2 Art Unit: 2194 Application/Control Number: 18/618,504 Page 3 Art Unit: 2194 Application/Control Number: 18/618,504 Page 4 Art Unit: 2194 Application/Control Number: 18/618,504 Page 5 Art Unit: 2194 Application/Control Number: 18/618,504 Page 6 Art Unit: 2194 Application/Control Number: 18/618,504 Page 7 Art Unit: 2194 Application/Control Number: 18/618,504 Page 8 Art Unit: 2194 Application/Control Number: 18/618,504 Page 9 Art Unit: 2194 Application/Control Number: 18/618,504 Page 10 Art Unit: 2194 Application/Control Number: 18/618,504 Page 11 Art Unit: 2194
