DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant’s submission filed on 6/11/2026 has been entered.
Claims 45, 47-51, 54-56, 58-60 and 63-69 are presented for examination. Claims 45, 47-48, 55-56, 58 and 63 have been amended. Claims 68-69 have been added.
Examiner Notes
Examiner cites particular columns, paragraphs, figures and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirely as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 45, 47-51, 54-56, 58-60 and 63-67 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshimura et al. (JP 2013114366 A, hereafter Yoshimura-English translation provided by Google Patents) in view of Hahm et al. (US 20180121601 A1, hereafter Hahm).
Regarding to claim 45, Yoshimura discloses: A hybrid computing method comprising:
receiving a program to be executed in a hybrid computing system that includes a control system, the control system including a first classical processor and a second, distinct classical processor, the first classical processor comprising a central processing unit (CPU), the second classical processor comprising a microcontroller, and the microcontroller comprising hardware control logic, the program comprising: classical program instructions; and quantum program instructions expressed as hardware-independent instructions that are generic to particular quantum computing system architecture (see Fig. 2, [0026]-[0029]; “The room temperature unit 101 includes a main storage device 201, a CPU 202”, “Correspondingly, the application program 210 is configured as a composite of the classical program 211 and the quantum program 212. The classic program 211 is a program described in a programming language such as C language, for example, and describes processing to be performed by the CPU 202 in pre-processing and post-processing. The quantum program 212 describes a process to be performed by the low temperature unit 102 in this process. The quantum program 212 can be described in a programming language like the classical program 211, or may be expressed as a unitary matrix or a quantum circuit”. Also see [0001] and [0020]-[0021]; “a quantum computer system having a hybrid configuration of classical-quantum quantum algorithms”. For the claimed second, distinct classical processor, see Fig. 3, 18, [0025] and [0087]; “a micro control unit 301 which is a control device corresponding to a classical computer function unit as well as a quantum computer function unit” and “the micro control unit 301 is replaced with a CPU 1102”);
compiling the classical program instructions including generating first native instructions for the CPU of the control system (see Fig. 2 and [0026]-[0029]; “The classical compiler 221 is software for converting the classical program 211 into a classical object 231 that is a format executable on the CPU 202” and “the classic object 231 is a code that can be executed by the CPU 202 generated by the classic compiler 221”);
compiling the quantum program instructions including generating second native instructions for a quantum computing system architecture of the hybrid computing system (see Fig. 2, [0026]-[0029]; “The quantum compiler 222 is software for converting the quantum program 212 into quantum microcode 232 which is a format that can be executed on the low temperature unit 102”. Also see [0025]; “the quantum computer function unit corresponds to the low temperature unit 102”);
executing, by operation of the CPU, the first native instructions for the CPU in coordination with execution of the second native instructions for the quantum computing system architecture; executing, by operation of a quantum processor of the hybrid computing system, the second native instructions for the quantum computing system architecture in coordination with execution of the first native instructions for the CPU (see [0057]; “it is possible to easily generate a program that executes a series of sequences using not only the room temperature part 101 but also all the elements of the quantum part 310 of the low temperature part 102. The execution result finally obtained by executing the quantum algorithm in the quantum computer function unit in the low temperature part is output as observation data to the room temperature part”. Also see Figs. 2-3, 9-10, [0030]-[0032], [0048]-[0056]; “The quantum unit 310 is a core part of the quantum computer function unit, and has a resource for executing processing described in the quantum microcode 321”, “In the preprocessing phase S410, the quantum object is preprocessed by executing the classic object 231 … intermediate data 234 is obtained as a processing result”, “The quantum microcode 321 transferred to the low-temperature unit 102 in the processing preparation phase S420 is executed in the quantum unit execution S501” and “ In the post-processing phase S510, the quantum object is post-processed by executing the classical object 231 as in the pre-processing phase S410. In the post-processing, the execution result of this processing execution phase S500, that is, the observation data 235 transferred in the room temperature portion transfer S502 is used”. Note: according to [0026]-[0029], the instructions executed by CPU 202 of the room temperature part 101 are “a classical object 231 that a format executable on the CPU 202”, i.e., claimed native instructions for the classical processor, and the instructions executed by low temperature part 102 are “quantum microcode 232 which is a format that can be executed on the low temperature unit 102”, i.e., claimed native instructions for the quantum computing system architecture, and thus even if [0057] does not explicitly describe it is executing the compiled results, i.e., claimed native instructions for classical processor and quantum processor, [0057] is still about the classical processor executes the native instructions for the classical processor and the quantum processor executes the native instructions for the quantum processor),
wherein the hardware control logic compiles and delivers a control sequence to the quantum processor according to the second native instructions for the quantum computing system architecture, and compiling and delivering the control sequence comprises, by operation of the hardware control logic: accessing control signal information according to the second native instructions for quantum computing system architecture, generating, for respective qubits of the quantum processor, a time-delimited schedule of control signals, and delivering control signals to the receptive qubits of the quantum processor according to the time-delimited schedule (see Figs. 3, 18, [0025], [0032], [0035], [0038]-[0040], [0087]; “In response to an instruction from the micro control unit 301, the control gate performs a designated operation on a designated qubit in the quantum register 312”, “The micro control unit 301 reads the quantum microcode 321 from the instruction buffer 320 and controls the control gate 311 and the read gate 313 based on the sequence described in the quantum microcode 321. The quantum microcode 321 is an operation sequence in which commands for controlling the control gate 311 and the read gate 313 are shown in time series. As an instruction, an operation instruction for driving the control gate 311 to operate on a qubit designated in the quantum register 312 and an observation by controlling the read gate 313 are performed, and the observation result is stored in the observation register 302. There is an observation order. The operation command and the observation command are described on the same time series, and the order relationship is maintained between the commands … The operation command includes an operation that operates on a single qubit and an operation that operates on a plurality of qubits”. Note: it is understood that in order to achieve the order relationship between the commands, the control signals for the respective qubits should be generated and delivered according to a time-delimited schedule in a relative time sequence. Also see Fig. 7 and [0045]-[0047]; “The operation on the qubit 410 is performed by applying voltage pulses to the control gates 420, 421, 422, 430, 431, and 432, respectively. The operations that can be realized differ depending on the voltage pulse pattern (amplitude, time, phase relationship with other pulses) applied to each control gate. In the voltage pulse pattern example (Vpa, Vpb, Vpc, Vpd, Vpe, Vpf) of FIG. 7, a pulse acting in the direction of lowering the barrier potential height is applied to the control gates 420, 430” and “various types of operations can be performed by applying voltage pulses to the control gate”. The description from [0045] also can be used to support the control signals for the respective qubits should be generated and delivered according to a time-delimited schedule);
providing an output of the program based on the execution of the first native instructions for the CPU and the execution of the second native instructions for the quantum computing system architecture (see [0057]; “it is possible to easily generate a program that executes a series of sequences using not only the room temperature part 101 but also all the elements of the quantum part 310 of the low temperature part 102. The execution result finally obtained by executing the quantum algorithm in the quantum computer function unit in the low temperature part is output as observation data to the room temperature part”. Also see Figs. 2-3, 9-10, [0030]-[0032], [0048]-[0056]).
Yoshimura does not disclose:
the control system including an integrated package that includes the first classical processor and the second classical processor, the first and second classical processors being integrated on a single chip in the integrated package, the second classical processor comprising a field-reprogrammable gate array (FPGA), and the FPGA comprising FPGA control logic,
However, Hahm discloses: a control system including an integrated package that includes a first classical processor and a second, distinct classical processor, the first and second classical processors being integrated on a single chip in the integrated package, the first classical processor comprising a central processing unit (CPU), and the second classical processor comprising a field-programmable gate array (FPGA) (see [0548]-[0549]; “FPGA and CPU cores may be fabricated on a single die, see FIG. 35, using a system-on-a-chip (SOC) methodology”), and the FPGA comprising FPGA control logic, wherein the FPGA control logic performs customized functions (see [0548] and [0553]; “custom logic, e.g., 17, may be instantiated inside the FPGA 7” and “a whole operational function may be substantially or entirely implemented in custom FPGA logic”. Also see Fig. 6, [0307]; “a high-level view of various functional blocks within an exemplary HMM engine 13 within a hardware accelerator 8, on the FPGA or ASIC 7 … various other components 17, HMM control logic 15”).
It would have been obvious to one with ordinary skill, in the art before the effective filling date of the claim invention, to modify the control system having multiple classical processors in a hybrid environment from Yoshimura by including a control system having different types classical processors that are integrated into one single chip from Hahm, and thus the combination of Yoshimura and Hahm would disclose the missing limitations from Yoshimura, since it is well-known and understood that integrating multiple processing units within one single chip not only provides multiple processing resources but also reduces the sizes and numbers of circuits to be used in a system.
Regarding to Claim 47, the rejection of Claim 45 is incorporated and further the combination of Yoshimura and Hahm discloses:
by operation of the control system, identifying a set of events to execute the program based on the first and second native instructions; and by operation of the control system, generating an event schedule comprising resource schedules for the respective qubits of the quantum processor (see [0048]-[0056] from Yoshimura; “In the preprocessing phase S410, the quantum object is preprocessed by executing the classic object 231 … intermediate data 234 is obtained as a processing result”, “The quantum microcode 321 transferred to the low-temperature unit 102 in the processing preparation phase S420 is executed in the quantum unit execution S501” and “ In the post-processing phase S510, the quantum object is post-processed by executing the classical object 231 as in the pre-processing phase S410. In the post-processing, the execution result of this processing execution phase S500, that is, the observation data 235 transferred in the room temperature portion transfer S502 is used”. Also see [0038]-[0040] and [0045]-[0047] from Yoshimura; “The micro control unit 301 reads the quantum microcode 321 from the instruction buffer 320 and controls the control gate 311 and the read gate 313 based on the sequence described in the quantum microcode 321. The quantum microcode 321 is an operation sequence in which commands for controlling the control gate 311 and the read gate 313 are shown in time series” and “The operation on the qubit 410 is performed by applying voltage pulses to the control gates 420, 421, 422, 430, 431, and 432, respectively. The operations that can be realized differ depending on the voltage pulse pattern (amplitude, time, phase relationship with other pulses) applied to each control gate”).
Regarding to Claim 48, the rejection of Claim 47 is incorporated and further the combination of Yoshimura and Hahm discloses: wherein the event schedule comprises resource schedules for: the respective qubits; and other respective computational resources of the hybrid computing system (see the rejection of claim 47 above. Also see Figs. 1, 2, [0025]- [0029] from Yoshimura; “the quantum computer function unit corresponds to the low temperature unit 102”, “The quantum compiler 222 is software for converting the quantum program 212 into quantum microcode 232 which is a format that can be executed on the low temperature unit 102”. The executions of the program having classical program instruction part and quantum program instructions part would require at least the event of using a quantum compiler 222 located at the normal temperature unit 101 to perform corresponding functionality before using the low temperature unit 102 or quantum computing system to perform corresponding quantum microcode, and thus it would require at least an event schedule to using the respective classical resources like CPU 202 and main storage device 201 to perform the functionalities of quantum compiler 222 before the event of using the quantum resources from the low temperature unit 102).
Regarding to Claim 49, the rejection of Claim 48 is incorporated and further the combination of Yoshimura and Hahm discloses: wherein the other respective computational resources include the CPU and a classical memory (see the rejection of claim 48 above. As explained at the rejection of claim 48 above, at the combination system, the executions of the program having classical program instruction part and quantum program instructions part would require at least the event of using a quantum compiler 222 located at the normal temperature unit 101 to perform corresponding functionality before using the low temperature unit 102 or quantum computing system to perform corresponding quantum microcode, and thus it would require at least an event schedule to using the respective classical resources like CPU 202 and main storage device 201 to perform the functionalities of quantum compiler 222 before the event of using the quantum resources from the low temperature unit 102).
Regarding to Claim 50, the rejection of Claim 47 is incorporated and further the combination of Yoshimura and Hahm discloses: wherein the set of events comprises at least one of: application of a quantum logic gate to one or more of the qubits Also (see [0038]-[0040] and [0045]-[0047] from Yoshimura; “The micro control unit 301 reads the quantum microcode 321 from the instruction buffer 320 and controls the control gate 311 and the read gate 313 based on the sequence described in the quantum microcode 321. The quantum microcode 321 is an operation sequence in which commands for controlling the control gate 311 and the read gate 313 are shown in time series” and “The operation on the qubit 410 is performed by applying voltage pulses to the control gates 420, 421, 422, 430, 431, and 432, respectively. The operations that can be realized differ depending on the voltage pulse pattern (amplitude, time, phase relationship with other pulses) applied to each control gate”; measurement of a quantum state of one or more of the qubits (see Figs. 6-8, [0035] and [0043]-[0047] from Yoshimura; “the quantum register 312 is an N qubit quantum register having N qubits. This N qubit quantum register has the ability to express a superposition of 2 N states from 000... 000 (N is 0) to 111... 111 (N is 1) … At this time, the qubit to be observed is designated by the micro controller 301. With the observation, the observed qubit state converges to either 0 or 1 from the superposition of 0 and 1”, “an example of a state held by the qubit 410”, “FIG. 7 shows an example of a control gate control method for performing Hadamard transform”); and storing a quantum state measurement into a classical memory in the hybrid computing system (see [0055]-[0056] from Yoshimura; “The quantum microcode 321 transferred to the low-temperature unit 102 in the processing preparation phase S420 is executed in the quantum unit execution S501, and the processing result is obtained in the observation register 302 … In the post-processing, the execution result of this processing execution phase S500, that is, the observation data 235 transferred in the room temperature portion transfer S502 is used. Therefore, post-processing execution S511 executes the classic object 231 using the observation data 235 as input data”. Also see Fig. 2, [0026], [0029] from Yoshimura; “The main storage device 201 holds an application program 210, system software 220, and line time information 230”, “The runtime information 230 … observation data 235”).
Regarding to Claim 51, the rejection of Claim 47 is incorporated and further the combination of Yoshimura and Hahm discloses: wherein: the hybrid computing system comprises:
classical computing resources that include the CPU and one or more classical memories (see Fig. 2, [0026] from Yoshimura; “The hardware configuration of the room temperature unit 101 is basically the same as the hardware configuration of a classic computer that is generally used at present. The room temperature unit 101 includes a main storage device 201, a CPU 202”); and
quantum computing resources that include the quantum processor (see [0032] from Yoshimura; “The quantum unit 310 is a core part of the quantum computer function unit, and has a resource for executing processing described in the quantum microcode 321”); and
the set of events comprises events to be executed using the respective quantum computing resources and events to be executed using the respective classical computing resources (see [0048]-[0056] from Yoshimura; “In the preprocessing phase S410, the quantum object is preprocessed by executing the classic object 231 … intermediate data 234 is obtained as a processing result”, “ In the post-processing phase S510, the quantum object is post-processed by executing the classical object 231 as in the pre-processing phase S410. In the post-processing, the execution result of this processing execution phase S500, that is, the observation data 235 transferred in the room temperature portion transfer S502 is used”. In addition, see rejection of claim 48).
Regarding to Claim 54, the rejection of Claim 45 is incorporated and further the combination of Yoshimura and Hahm discloses: wherein the control system comprises memory and the memory comprises a dynamic random-access memory (DRAM), FPGA registers, or a state memory of a processor (see [0548]-[0549] from Hahm; “FPGA and CPU cores may be fabricated on a single die, see FIG. 35, using a system-on-a-chip (SOC) methodology”. It is understood that the circuit of FPGA itself would include certain FPGA registers as memory to store data or information. Such as, see “the memory associated with the chip, e.g., FPGA … Specifically, the hardware may include an array of registers 8a” from [0189] of Hahm and “pipelining the FPGA or ASIC heavily with registers” from [0328] of Hahm. In addition, see “the CPU may build the data structure, store it in an associated memory, such as a DRAM, which memory may then be accessed by the processing engines running on the FPGA” from [0523] of Hahm, “a loose integration between the CPU 1000 and FPGA 7 may require each device to have its own dedicated external memory, such as DRAMs 1014,14. As depicted in FIG. 33A, the CPU(s) 1000 has its own DRAM 1014 on the system motherboard, such as DDR3 or DDR4 DIMMs, while the FPGA 7 has its own dedicated DRAMs 14” from [0526] of Hahm).
Regarding to Claim 55, the rejection of Claim 45 is incorporated and further the combination of Yoshimura and Hahm discloses:
the control system comprises a classical memory, the CPU, and a program processor implemented using the FPGA (see Figs. 2-3, 18 [0026], [0028], [0057] and [0087] from Yoshimura; “The hardware configuration of the room temperature unit 101 is basically the same as the hardware configuration of a classic computer that is generally used at present. The room temperature unit 101 includes a main storage device 201, a CPU 202” and “the quantum computer function unit (low temperature unit 102) includes a quantum unit 310, a classical storage device (commands). A buffer 320) and a controller (microcontroller 301) capable of accessing the classical storage device and the quantum unit 310”. Also see [0548]-[0549] from Hahm. At the combination system, certain functionalities (like quantum compiler 222 and quantum logic gate controlling) performed by CPU 202 and microcontroller 301 (or CPU 1102 at Fig. 18 of Yoshimura) are modified to be performed by a FPGA implemented processor); and
the method comprises:
by operation of the program processor, generating the second native instructions for the quantum computing system architecture (see [0027] from Yoshimura; “The quantum compiler 222 is software for converting the quantum program 212 into quantum microcode 232 which is a format that can be executed on the low temperature unit 102”. Also see [0088] from Yoshimura; “The CPU 1102 executes the quantum compiler 1133, and generates the quantum microcode 1134”); and
storing the second native instructions for the quantum computing system architecture in the classical memory of the control system (see [0057] from Yoshimura; “The classical memory device stores quantum microcode 321 which is a sequence of operation instructions for the control gate or read gate” and “the quantum compiler 222 that generates the quantum microcode 321”).
Regarding to Claim 56, Claim 56 is a system claim corresponds to method Claim 45 and is rejected for the same reason set forth in the rejection of Claim 45 above.
Regarding to Claim 58, Claim 58 is a system claim corresponds to method Claim 47 and is rejected for the same reason set forth in the rejection of Claim 47 above.
Regarding to Claim 59, Claim 59 is a system claim corresponds to method Claim 50 and is rejected for the same reason set forth in the rejection of Claim 50 above.
Regarding to Claim 60, Claim 60 is a system claim corresponds to method Claim 51 and is rejected for the same reason set forth in the rejection of Claim 51 above.
Regarding to Claim 63, Claim 63 is a system claim corresponds to method Claim 55 and is rejected for the same reason set forth in the rejection of Claim 55 above.
Regarding to Claim 64, the rejection of Claim 45 is incorporated and further the combination of Yoshimura and Hahm discloses: wherein the control system includes a circuit board, the integrated package is supported on the circuit board, and the circuit board includes a dynamic random-access memory (DRAM) (see Fig. 34B, [0548]-[0549] from Hahm; “The tightly-integrated CPU/FPGA platform becomes compatible with standard motherboards … If each FPGA resides in the same chip package as a CPU (either MCP or SOC)”. Also see Fig. 34B for the circuit board having FPGA and CPU being integrated into a single chip of an integrated package also include a DRAM).
Regarding to Claim 65, Claim 65 is a system claim corresponds to method Claim 64 and is rejected for the same reason set forth in the rejection of Claim 64 above.
Regarding to Claim 66, the rejection of Claim 45 is incorporated and further the combination of Yoshimura and Hahm discloses: wherein the FPGA comprises FPGA registers (see [0189] from Hahm; “write input data into the memory associated with the chip, e.g., FPGA … the hardware may be configured to queue the data in a manner so that it is red into the memory in a strategic manner, such as set forth in FIG. 1F. Specifically, the hardware may include an array of registers 8 a into which the cycle files may be dispersed and re-organized into individual read data”) and a communication link connecting the FPGA registers and the FPGA control logic (see Fig. 1G and [0188]-[0189] from Hahm; “This generated column organized data may then be queued and/or streamed, e.g., in flight, into the hardware where dedicated processing engines will queue up the column organized data and transpose that data from a column by column, cycle order configuration, to a row by row …. an array of registers 8 a into which the cycle files may be dispersed and re-organized into individual read data, such as by writing one base from a column into registers that are organized into rows. More specifically, as can be seen with respect to FIG. 1G”. Note: Fig. 1G clearly shows there is a communication link connecting the registers and the transposition processing engine), and providing the output comprises:
providing the output from the quantum processor to the FPGA control logic (see [0035], [0057] from Yoshimura; “The read gate 313 is a gate for observing and reading the value of one or a plurality of qubits in the quantum register 312. In response to an instruction from the micro control unit 301, the read gate 313 observes the value of the quantum register 312 and stores the observation result in the observation register 302”. Also see [0548]-[0549] from Hahm. At the combination system, certain functionalities performed by CPU 202 and microcontroller 301 (or CPU 1102 at Fig. 18 of Yoshimura) are modified to be performed by a FPGA implemented processor); and
placing the output in the FPGA registers from the FPGA control logic through the communication link (see Fig. 1G and [0188]-[0189] from Hahm and related explanation for claimed FPGA registers and FPGA control logic above. Also see [0037] from Yoshimura; “The observation register 302 is a register that holds the observation result of the quantum register 312 as described above, and this observation register holds a storage element of the classical computer function unit, that is, a binary value of 0 or 1”. At the combination system, certain functionalities performed by CPU 202 and microcontroller 301 (or CPU 1102 at Fig. 18 of Yoshimura) are modified to be performed by a FPGA implemented processor, and thus the observation register 302 at the combination system is implemented as FPGA register).
Regarding to Claim 65, Claim 65 is a system claim corresponds to method Claim 64 and is rejected for the same reason set forth in the rejection of Claim 64 above.
Regarding to Claim 65, the rejection of Claim 45 is incorporated, the combination of Yoshimura and Hahm discloses: wherein accessing the control signal information according to the second native instructions comprises accessing pulse profiles based on the second native instructions (Also see Fig. 7 and [0045]-[0047] from Yoshimura; “The operation on the qubit 410 is performed by applying voltage pulses to the control gates 420, 421, 422, 430, 431, and 432, respectively. The operations that can be realized differ depending on the voltage pulse pattern (amplitude, time, phase relationship with other pulses) applied to each control gate. In the voltage pulse pattern example (Vpa, Vpb, Vpc, Vpd, Vpe, Vpf) of FIG. 7, a pulse acting in the direction of lowering the barrier potential height is applied to the control gates 420, 430” and “various types of operations can be performed by applying voltage pulses to the control gate”).
Regarding to Claim 69, Claim 69 is a system claim corresponds to method Claim 68 and is rejected for the same reason set forth in the rejection of Claim 68 above.
Response to Arguments
Applicant’s arguments, filed 6/11/2026, with respect to rejections of claims 45, 47-51, 54-56, 58-60 and 63-67 under 35 U.S.C. 103 have been full considered and new grounds of rejections were made based on the amended limitations from the independent claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Versluis et al. (US 20210279134 A1) discloses: the profile of a flux pulse to tune the transition frequency of a qubit to the interaction frequency (see [0020] and [0061]).
Xiong et al. (CN 105281886 A-publication date: 1/27/2016. English translation provided by Google Patents) discloses: In a typical setup for studying quantum computing with atoms (ions), users need to perform operations on qubits. These operations ultimately boil down to creating a series of laser or microwave pulses of specific amplitude, phase, frequency and duration (see [0006]).
Babbush et al. (US 20170351967 A1) discloses: In equation (1), Xi, Yi, Zi are Pauli operators and ai(t), bi(t), ci(t) and gij(t) are time-dependent profiles generated by microwave pulses that are sent through wires in the hardware. In order to execute a quantum circuit an experimentalist may be required to first calibrate all the quantum gates included in the quantum circuit by sending specific pulses through the wires in the hardware (see [0034]).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHI CHEN whose telephone number is (571)272-0805. The examiner can normally be reached on M-F from 9:30AM to 5:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, April Y Blair can be reached on 571-270-1014. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Zhi Chen/
Patent Examiner, AU2196
/APRIL Y BLAIR/Supervisory Patent Examiner, Art Unit 2196
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