DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to Applicant’s Amendment filed on 12/23/2025.
Claims 45, 47-51, 54-56, 58-60 and 63-67 are presented for examination. Claims 45 and 56 have been amended; Claims 66-67 have been added.
Examiner Notes
Examiner cites particular columns, paragraphs, figures and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirely as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 45, 47-51, 54-56, 58-60 and 63-67 are rejected under 35 U.S.C. 103 as being unpatentable over Johnson et al. (US 20170223143 A1- recorded at IDS filled by 3/27/2024, hereafter Johnson) in view of Yoshimura et al. (JP 2013114366 A, hereafter Yoshimura-English translation provided by Google Patents), Allen et al. (US 20110238378 A1- recorded at IDS filled by 3/27/2024, hereafter Allen) and Hahm et al. (US 20180121601 A1, hereafter Hahm).
Yoshimura was cited on PTO-892 form of the previous office action.
Regarding to claim 45, Johnson discloses: A hybrid computing method comprising:
receiving a program to be executed in a hybrid computing system that including a control system, the control system including a first classical processor, the first classical processor comprising a central processing unit (CPU), the program comprising: classical program instructions; and quantum program instructions (see Figs. 1, 2 and [0036]-[0038]; “solve this computational task is to partition the task into smaller sub-problems, some of which are solved on quantum processing devices and some of which are solved on classical distributed computers”, and “loads this problem 120 into a big data compute framework 130”. Note: it is understood that the tasks/operations to be performed on the computing devices (no matter the classical computing devices or quantum computing devices) are expressed in the corresponding instructions format and the classical distributed computers would include at least a control system having a classical processor. Also see [0014] and [0019]; “Existing frameworks typically rely on classical (non-quantum) processing devices, such as CPUs and GPUs”. Thereby, it is understood and reasonable that the classical distributed computers discussed at [0036]-[0038] would include a CPU as execution resources of such classical distributed computers);
executing, by operation of the CPU, the [native] instructions for the CPU in coordination with execution of the [native] instructions for the quantum computing system architecture; executing, by operation of a quantum processor of the hybrid computing system, the [native] instructions for the quantum computing system architecture in coordination with execution of the [native] instructions for the CPU (see Figs. 1,2 and [0036]-[0038]; “distributes pieces of the problem (for instance, solving the delivery scheduling problem for particular cities rather than an entire state) to the quantum processing devices 190A-N as well as to classical distributed computers 150 available to the end user”. Distributing corresponding events or operations or sub-tasks suitable classical processor or suitable quantum processor for execution, and thus the execution of each of the corresponding classical operations/instructions and quantum operations/instructions by corresponding classical processors or quantum processor is performed in coordination with execution of another. Note: without further clarification, the claimed “in coordination” according to [0033] from Application’s specification can be “a hybrid computing system … in a coordinated manner. For example, … execute a program that leverages classical computing resources and quantum computing resources”, i.e., distributing corresponding instructions to suitable classical computing resource or quantum computing resources); and
providing an output of the program based on the execution of the [native] instructions for the CPU and the execution of the [native] instructions for the quantum computing system architecture (see [0037]; “allowing seamless execution of the problem in a heterogeneous environment involving both classical distributed computers 150 as well as quantum processing devices 190. The end result is a solution to the entire delivery scheduling problem, presented in a desired format 183 to the end user”. Also see [0055]; “aggregate computation results from all the worker machines in the system”).
Johnson does not disclose:
the control system including an integrated package that includes the first classical processor and a second, distinct classical processor, the first and second classical processors being integrated on a single chip in the integrated package, the second classical processor comprising a field-reprogrammable gate array (FPGA), and the FPGA comprising FPGA control logic,
the quantum program instructions expressed as hardware-independent instructions that are generic to particular quantum computing system architecture (note: Johnson does disclose the existence of the claimed quantum program instructions. However. Johnson does not specify such quantum program instructions are expressed as claimed “hardware-independent instructions that are generic to particular quantum computing system architecture” as required by the claim);
compiling the classical program instructions including generating native instructions for the CPU of the control system;
compiling the quantum program instructions including generating native instructions for a quantum computing system architecture of the hybrid computing system;
executing the instructions for the CPU is executing the native instructions for the CPU; executing the instructions for the quantum computing system architecture is executing the native instructions for the quantum computing system architecture, wherein the FPGA control logic compiles and delivers a control sequence to the quantum processor according to the native instructions for the quantum computing system architecture;
the output is provided based on the execution of the native instructions for the CPU and the execution of the native instructions for the quantum computing system architecture.
However, Yoshimura discloses: A hybrid computing method comprising:
receiving a program to be executed in a hybrid computing system that includes a control system, the control system including a first classical processor, the first classical processor comprising a central processing unit (CPU), the program comprising: classical program instructions; and quantum program instructions expressed as hardware-independent instructions that are generic to particular quantum computing system architecture (see Fig. 2, [0026]-[0029]; “The room temperature unit 101 includes a main storage device 201, a CPU 202”, “Correspondingly, the application program 210 is configured as a composite of the classical program 211 and the quantum program 212. The classic program 211 is a program described in a programming language such as C language, for example, and describes processing to be performed by the CPU 202 in pre-processing and post-processing. The quantum program 212 describes a process to be performed by the low temperature unit 102 in this process. The quantum program 212 can be described in a programming language like the classical program 211, or may be expressed as a unitary matrix or a quantum circuit”);
compiling the classical program instructions including generating native instructions for the CPU of the control system (see Fig. 2 and [0026]-[0029]; “The classical compiler 221 is software for converting the classical program 211 into a classical object 231 that is a format executable on the CPU 202”);
compiling the quantum program instructions including generating native instructions for a quantum computing system architecture of the hybrid computing system (see Fig. 2, [0026]-[0029]; “The quantum compiler 222 is software for converting the quantum program 212 into quantum microcode 232 which is a format that can be executed on the low temperature unit 102”. Also see [0025]; “the quantum computer function unit corresponds to the low temperature unit 102”);
executing, by operation of the CPU, the native instructions for the CPU; executing, by operation of a quantum processor of the hybrid computing system, the native instructions for the quantum computing system architecture and providing an output of the quantum program based on the execution of the native instructions for the CPU and the execution of the native instructions for the quantum computing system architecture (see [0057]; “it is possible to easily generate a program that executes a series of sequences using not only the room temperature part 101 but also all the elements of the quantum part 310 of the low temperature part 102. The execution result finally obtained by executing the quantum algorithm in the quantum computer function unit in the low temperature part is output as observation data to the room temperature part”. Note: according to [0026]-[0029], the instructions executed by CPU 202 of the room temperature part 101 are “a classical object 231 that a format executable on the CPU 202”, i.e., claimed native instructions for the classical processor, and the instructions executed by low temperature part 102 are “quantum microcode 232 which is a format that can be executed on the low temperature unit 102”, i.e., claimed native instructions for the quantum computing system architecture, and thus even if [0057] does not explicitly describe it is executing the compiled results, i.e., claimed native instructions for classical processor and quantum processor, [0057] is still about the classical processor executes the native instructions for the classical processor and the quantum processor executes the native instructions for the quantum processor).
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claim invention, to modify the executions of a task/program having both of classical parts and quantum parts at a hybrid computing system having both of classical computer system and quantum computing system at a high level of generality without the details of low level from Johnson by including a hybrid computing system executes both of classical program part and quantum program part to include both of classical compiler to convert classical program part to machine instructions for the classical resources and quantum compiler to convert quantum program part to machine instructions for the quantum resources from Yoshimura, since it is well-known and understood at the computing fields to use corresponding compiler to convert the program instructions written at a high level programming language into machine instructions that are suitable by corresponding execution units (see [0028] from Yoshimura).
In addition, Allen discloses: a hybrid computing method comprising:
a hybrid computing system that includes a control system, the control system including an integrated sub-system includes a first classical processor and a second, distinct classical processor, the first and second classical processors being integrated in the integrated sub-system, the second classical processor comprising processing hardware, and the processing hardware comprising processing hardware control logic (see Fig. 1A, abstract, [0025] and [0041]; “A hybrid classical-quantum processing system”, “Preprocessor 110 and classical problem solver 112 can be implemented using any suitable digital processor with hardware, firmware, and/or software components capable of executing logic instructions, receiving input signals, and providing output signals to components in system 100” and “QS compiler 114 and results interpreter 116 can be implemented using any suitable digital processor with hardware, firmware, and/or software components capable of executing logic instructions, receiving input signals, and providing output signals to components in system 100”. The hybrid computing system 100 include a control system including a first classical processor 112 and a second classical processor 114. Also see [0023]; “The preprocessor 110 can also determine that a problem can be split into a computable functional that can be tested on classical problem solver 112 and a non-computable functional that can be tested on quantum processing system 108”),
wherein the processing hardware control logic compiles and delivers a control sequence to the quantum processor according to the [native] instructions for the quantum computing system architecture (see [0032] and [0041]; “Quantum system compiler 114 can provide the non-computable functional and quantum allegory (e.g., a QUBO problem) to control computer 106. Control computer 106 can be used to queue jobs for quantum processing system 108” and “QS compiler 114 and results interpreter 116 can be implemented using any suitable digital processor with hardware, firmware, and/or software components capable of executing logic instructions, receiving input signals, and providing output signals to components in system 100”. Also see [0031]; “Compiler 134 receives a source code representation of the cybernetic system being tested and generates a compact information set in the form of a thermodynamical allegory that is suited for processing in quantum processing system 108”).
It would have been obvious to one with ordinary skill, in the art before the effective filling date of the claim invention, to modify the single processor implementation of classical system at a hybrid computing system from the combination of Johnson and Yoshimura by including multiple processors implementation that different processors for performing different functions from Allen, since it is well-known and understood to incorporate multiple processors to perform different functions over one single processor to reduce workload of the one single processor.
In addition, Hahm discloses: a control system including an integrated package that includes a first classical processor and a second, distinct classical processor, the first and second classical processors being integrated on a single chip in the integrated package, the first classical processor comprising a central processing unit (CPU), and the second classical processor comprising a field-programmable gate array (FPGA) (see [0548]-[0549]; “FPGA and CPU cores may be fabricated on a single die, see FIG. 35, using a system-on-a-chip (SOC) methodology”), and the FPGA comprising FPGA control logic, wherein the FPGA control logic performs customized functions (see [0548] and [0553]; “custom logic, e.g., 17, may be instantiated inside the FPGA 7” and “a whole operational function may be substantially or entirely implemented in custom FPGA logic”. Also see Fig. 6, [0307]; “a high-level view of various functional blocks within an exemplary HMM engine 13 within a hardware accelerator 8, on the FPGA or ASIC 7 … various other components 17, HMM control logic 15”).
It would have been obvious to one with ordinary skill, in the art before the effective filling date of the claim invention, to modify the control system having multiple classical processors in a hybrid environment from the combination of Johnson, Yoshimura and Allen by including a control system having different types classical processors that are integrated into one single chip from Hahm, and thus the combination of Johnson, Yoshimura, Allen and Hahm would disclose the missing limitations from Johnson, since it is well-known and understood that integrating multiple processing units within one single chip not only provides multiple processing resources but also reduces the sizes and numbers of circuits to be used in a system.
Regarding to Claim 47, the rejection of Claim 45 is incorporated and further the combination of Johnson, Yoshimura, Allen and Hahm discloses:
by operation of the control system, identifying a set of events to execute the program (see Figs. 1-2, [0036]-[0037] from Johnson; “to partition the task into smaller sub-problems, some of which are solved on quantum processing devices and some of which are solved on classical distributed computers”. Identifying a set of events/operations/sub-tasks of the computational task/program to be solved to be performed by either one of quantum computing resources or classical computing resources that suitable for certain events/operations/sub-tasks. Also see [0039] from Johnson; “converting the task to a quantum data model, such that the task may be readily solved on a variety of quantum processing devices and architectures 190”. Note: the claimed events at current claimed invention are described as “a set of events to execute the program”, see claim 47. Such language of “a set of events to execution the program” is too broad, it does not exclude the interpretation of such events being events of preparing execution of the program, i.e., the two claimed compiling steps/action/events from claim 45 can also be considered as ones from claimed “a set of events to execute the program”); and
by operation of the control system, generating an event schedule comprising resource schedules for qubits of the quantum processor (see [0043] and Claim 7 from Johnson; “an internal task scheduler 240 that is tuned for the many distinguishing characteristics of quantum computing devices” and “a module that schedules computational tasks to be computed by the quantum processing device”. Note: the quantum computing devices 190A-N are gate-mobile type quantum resources that defines qubits, then the scheduling of tasks to be computed by the quantum computing devices 190A-N would include resource schedules for the respective qubits forming the quantum computing resources. Also see “Quantum processing devices commonly use so-called qubits, or quantum bits” from [0016] of Johnson).
Regarding to Claim 48, the rejection of Claim 47 is incorporated and further the combination of Johnson, Yoshimura, Allen and Hahm discloses: wherein the event schedule comprises resource schedules for: the qubits; and other respective computational resources of the hybrid computing system (see the rejection of claim 47 above. Also see Figs. 1, 2, [0025]- [0029] from Yoshimura; “the quantum computer function unit corresponds to the low temperature unit 102”, “The quantum compiler 222 is software for converting the quantum program 212 into quantum microcode 232 which is a format that can be executed on the low temperature unit 102”. The executions of the program having classical program instruction part and quantum program instructions part would require at least the event of using a quantum compiler 222 located at the normal temperature unit 101 to perform corresponding functionality before using the low temperature unit 102 or quantum computing system to perform corresponding quantum microcode, and thus it would require at least an event schedule to using the respective classical resources like CPU 202 and main storage device 201 to perform the functionalities of quantum compiler 222 before the event of using the quantum resources from the low temperature unit 102).
Regarding to Claim 49, the rejection of Claim 48 is incorporated and further the combination of Johnson, Yoshimura, Allen and Hahm discloses: wherein the other respective computational resources include the CPU and a classical memory (see the rejection of claim 48 above. As explained at the rejection of claim 48 above, at the combination system, the executions of the program having classical program instruction part and quantum program instructions part would require at least the event of using a quantum compiler 222 located at the normal temperature unit 101 to perform corresponding functionality before using the low temperature unit 102 or quantum computing system to perform corresponding quantum microcode, and thus it would require at least an event schedule to using the respective classical resources like CPU 202 and main storage device 201 to perform the functionalities of quantum compiler 222 before the event of using the quantum resources from the low temperature unit 102).
Regarding to Claim 50, the rejection of Claim 47 is incorporated and further the combination of Johnson, Yoshimura, Allen and Hahm discloses: wherein the set of events comprises at least one of: application of a quantum logic gate to one or more of the qubits; measurement of a quantum state of one or more of the qubits; and storing a quantum state measurement into a classical memory in the hybrid computing system (see Fig. 1, [0016], [0018], [0037] and [0046] from Johnson; based on [0016], [0018] and [0046], it is understood that the quantum processing devices 190A-N of Fig. 1 at least comprising a gate-model quantum processor that defines qubits, and thus the execution of the quantum related tasks would require to include at least certain events like application of quantum logic gates to qubits. Also see [0017] from Yoshimura; “To give an example of an embodiment of the present invention, a quantum computer system observes a state of a quantum register composed of at least one qubit, a control gate for operating the quantum register”. Furthermore, see Fig. 1, [0016] and [0037] from Johnson; “Solutions 187 from the quantum processing devices 190 are returned through the API in an appropriate form 183 for the big data compute framework 130”. Thereby, the events, operations or sub-tasks that should be distributed to quantum computing devices 190A-N would require at least certain events like measurement of a quantum state of qubits to obtain solutions 187).
Regarding to Claim 51, the rejection of Claim 47 is incorporated and further the combination of Johnson, Yoshimura, Allen and Hahm discloses: wherein: the hybrid computing system comprises:
classical computing resources that include the CPU and one or more classical memories (see Fig. 1, [0037] from Johnson, Fig. 2, [0026] from Yoshimura; “classical distributed computers 150 available to the end user”, “The hardware configuration of the room temperature unit 101 is basically the same as the hardware configuration of a classic computer that is generally used at present. The room temperature unit 101 includes a main storage device 201, a CPU 202”); and
quantum computing resources that include the quantum processor (see Fig. 1, [0018] and [0037] from Johnson. It is understood that the quantum processing devices 190A-N of Fig. 1 at least comprising a quantum processor. Also see [0032] from Yoshimura; “The quantum unit 310 is a core part of the quantum computer function unit, and has a resource for executing processing described in the quantum microcode 321”); and
the set of events comprises events to be executed using the respective quantum computing resources and events to be executed using the respective classical computing resources (see Figs. 1-2, [0036]-[0037] from Johnson; “to partition the task into smaller sub-problems, some of which are solved on quantum processing devices and some of which are solved on classical distributed computers”. Identifying a set of events/operations/sub-tasks of the computational task/program to be solved to be performed by either one of quantum computing resources or classical computing resources that suitable for certain events/operations/sub-tasks. Also see [0039] from Johnson; “converting the task to a quantum data model, such that the task may be readily solved on a variety of quantum processing devices and architectures 190”. In addition, see rejection of claim 48).
Regarding to Claim 54, the rejection of Claim 45 is incorporated and further the combination of Johnson, Yoshimura, Allen and Hahm discloses: wherein the control system comprises memory and the memory comprises a dynamic random-access memory (DRAM), FPGA registers, or a state memory of a processor (see [0548]-[0549] from Hahm; “FPGA and CPU cores may be fabricated on a single die, see FIG. 35, using a system-on-a-chip (SOC) methodology”. It is understood that the circuit of FPGA itself would include certain FPGA registers as memory to store data or information. Such as, see “the memory associated with the chip, e.g., FPGA … Specifically, the hardware may include an array of registers 8a” from [0189] of Hahm and “pipelining the FPGA or ASIC heavily with registers” from [0328] of Hahm. In addition, see “the CPU may build the data structure, store it in an associated memory, such as a DRAM, which memory may then be accessed by the processing engines running on the FPGA” from [0523] of Hahm, “a loose integration between the CPU 1000 and FPGA 7 may require each device to have its own dedicated external memory, such as DRAMs 1014,14. As depicted in FIG. 33A, the CPU(s) 1000 has its own DRAM 1014 on the system motherboard, such as DDR3 or DDR4 DIMMs, while the FPGA 7 has its own dedicated DRAMs 14” from [0526] of Hahm).
Regarding to Claim 55, the rejection of Claim 45 is incorporated and further the combination of Johnson, Yoshimura, Allen and Hahm discloses:
the control system comprises a classical memory, the CPU, and a program processor implemented using the FPGA (see Figs. 2-3, [0026], [0028] and [0057] from Yoshimura; “The hardware configuration of the room temperature unit 101 is basically the same as the hardware configuration of a classic computer that is generally used at present. The room temperature unit 101 includes a main storage device 201, a CPU 202” and “the quantum computer function unit (low temperature unit 102) includes a quantum unit 310, a classical storage device (commands). A buffer 320) and a controller (microcontroller 301) capable of accessing the classical storage device and the quantum unit 310”. Also see Fig. 1A, [0015], [0025] [0041] from Allen and [0548]-[0549] from Hahm. At the combination system, the classical problem solver 112 from Allen used to perform the non-quantum program/problem is claimed CPU as implemented for claimed first classical processor, and the QS compiler 114 from Allen used to generate certain quantum program instructions as claimed program processor to be implemented by FPGA that integrated with CPU within same chip after combining the feature from Hahm); and
the method comprises:
by operation of the program processor, generating the native instructions for the quantum computing system architecture (see [0027] from Yoshimura; “The system software 220 is a software group for causing the CPU 202 to perform control and operation necessary for operating the application program 210 on the CPU 220 and the low temperature unit 102. The system software 220 includes … a quantum compiler 222 … The quantum compiler 222 is software for converting the quantum program 212 into quantum microcode 232 which is a format that can be executed on the low temperature unit 102”. Also see [0088] from Yoshimura; “The CPU 1102 executes the quantum compiler 1133, and generates the quantum microcode 1134”. Also see [0032] from Allen; “Quantum system compiler 114 can provide the non-computable functional and quantum allegory (e.g., a QUBO problem) to control computer 106”); and
storing the native instructions for the quantum computing system architecture in the classical memory of the control system (see [0057] from Yoshimura; “The classical memory device stores quantum microcode 321 which is a sequence of operation instructions for the control gate or read gate” and “the quantum compiler 222 that generates the quantum microcode 321”).
Regarding to Claim 56, Claim 56 is a system claim corresponds to method Claim 45 and is rejected for the same reason set forth in the rejection of Claim 45 above.
Regarding to Claim 58, the rejection of Claim 56 is incorporated and further Claim 58 is a system claim corresponds to method Claim 47 and is rejected for the same reason set forth in the rejection of Claim 47 above.
Regarding to Claim 59, the rejection of Claim 58 is incorporated and further Claim 59 is a system claim corresponds to method Claim 50 and is rejected for the same reason set forth in the rejection of Claim 50 above.
Regarding to Claim 60, the rejection of Claim 58 is incorporated and further Claim 60 is a system claim corresponds to method Claim 51 and is rejected for the same reason set forth in the rejection of Claim 51 above.
Regarding to Claim 63, the rejection of Claim 56 is incorporated and further Claim 63 is a system claim corresponds to method Claim 55 and is rejected for the same reason set forth in the rejection of Claim 55 above.
Regarding to Claim 64, the rejection of Claim 45 is incorporated and further the combination of Johnson, Yoshimura, Allen and Hahm discloses: wherein the control system includes a circuit board, the integrated package is supported on the circuit board, and the circuit board includes a dynamic random-access memory (DRAM) (see Fig. 34B, [0548]-[0549] from Hahm; “The tightly-integrated CPU/FPGA platform becomes compatible with standard motherboards … If each FPGA resides in the same chip package as a CPU (either MCP or SOC)”. Also see Fig. 34B for the circuit board having FPGA and CPU being integrated into a single chip of an integrated package also include a DRAM).
Regarding to Claim 65, the rejection of Claim 56 is incorporated and further Claim 65 is a system claim corresponds to method Claim 64 and is rejected for the same reason set forth in the rejection of Claim 64 above.
Regarding to Claim 66, the rejection of Claim 45 is incorporated and further the combination of Johnson, Yoshimura, Allen and Hahm discloses: wherein the FPGA comprises FPGA registers (see [0189] from Hahm; “write input data into the memory associated with the chip, e.g., FPGA … the hardware may be configured to queue the data in a manner so that it is red into the memory in a strategic manner, such as set forth in FIG. 1F. Specifically, the hardware may include an array of registers 8 a into which the cycle files may be dispersed and re-organized into individual read data”) and a communication link connecting the FPGA registers and the FPGA control logic (see Fig. 1G and [0188]-[0189] from Hahm; “This generated column organized data may then be queued and/or streamed, e.g., in flight, into the hardware where dedicated processing engines will queue up the column organized data and transpose that data from a column by column, cycle order configuration, to a row by row …. an array of registers 8 a into which the cycle files may be dispersed and re-organized into individual read data, such as by writing one base from a column into registers that are organized into rows. More specifically, as can be seen with respect to FIG. 1G”. Note: Fig. 1G clearly shows there is a communication link connecting the registers and the transposition processing engine), and providing the output comprises:
providing the output from the quantum processor to the FPGA control logic (see [0057] from Yoshimura; “The execution result finally obtained by executing the quantum algorithm in the quantum computer function unit in the low temperature part is output as observation data to the room temperature part”. Also see [0032] and [0039] from Allen; “supply the results of the processing in control computer 106 and quantum processing system 108 to results interpreter 116” and “an embodiment of a results interpreter 116 is shown in FIG. 1C including decision engine 140 and error locator 142. Decision engine 140 receives the results from control computer 106 and evaluates the results to determine whether a fault occurred”. Furthermore, see [0041] from Allen and [0548]-[0549] from Hahm; “QS compiler 114 and results interpreter 116 can be implemented using any suitable digital processor with hardware, firmware, and/or software components capable of executing logic instructions, receiving input signals”. Note: at the combination system, QS compiler 114 and results interpreter 116 from Allen are considered as together to be modified as FPGA for implementation, and thus the operation/function logic from results interpreter 116 can be considered as part of the claimed FPGA control logic to receive the results from the quantum sub-system or quantum processor to perform its customized functions); and
placing the output in the FPGA registers from the FPGA control logic through the communication link (see Fig. 1G and [0188]-[0189] from Hahm and related explanation for claimed FPGA registers and FPGA control logic above. Also see [0039] from Allen; “Decision engine 140 receives the results from control computer 106 and evaluates the results to determine whether a fault occurred”. It is understood that the process of evaluation of the result to determine whether a fault occurred discussed at [0039] from Allen would require to place the result data into certain registers or memory, and thus it is required at the combination system to placing the output in the FPGA registers from the FPGA control logic through the communication link as discussed at [0188]-[0189] of Hahm. Also see [0042] from Allen; “The output of results interpreter 116, such as whether there is a fault in a particular CPS, the interim states where the fault occurred, and other relevant information, can be stored in repository 118. User/Program interface 102 can access the information as needed. Repository 118 can be implemented using any suitable computer storage medium such as a disk drive, memory stick”. According to the description discussed at [0188]-[0189] from Hahm, the process of storing the result or output related to quantum operation at repository 118 at the combination system is also required placing such result or output in the FPGA registers from the FPGA control logical through the communication link).
Regarding to Claim 65, the rejection of Claim 56 is incorporated and further Claim 65 is a system claim corresponds to method Claim 64 and is rejected for the same reason set forth in the rejection of Claim 64 above.
Response to Arguments
Applicant’s arguments, filed 12/23/2025, with respect to rejections of claims 45, 47-51, 54-56, 58-60 and 63-67 under 35 U.S.C. 103 have been full considered but they are not persuasive.
Applicant’s arguments at pages 7-8 are summarized as the following:
For the independent claims 45 and 56, each claim was amended with new limitations of “the FPGA comprising FGPA control logic” and “wherein the FGPA control logic compiles and delivers a control sequence to the quantum processor” (see last two paragraphs of page 7 and last second paragraph of page 8 from the Remarks). “The Office action admits Johnson, Yoshimura, and Allen are silent regarding the second classical processor being a field programmable gate array (FPGA). The rejection of claim 45 relies on Hahm as allegedly disclosing an FPGA, but Hahm contains no mention of FPGA control logic that compiles and delivers a control sequence to a quantum processor” as amended (see first paragraph of page 8 from the Remarks). Applicant further explained that “the FPGA” from Hahm “includes data processing engines that process genomic datasets, e.g., analyze DNA sequences. Hahm has no quantum processor to control, no quantum program instruction to compile, and no teaching of control logic functionality.” “Therefore, Hahm has not been shown to disclose or suggest that the FGPA includes FPGA control logic that compiles and delivers a control sequence to a quantum processor. None of the other three references has been shown to teach or suggest using an FPGA in a quantum computing system, let alone FPGA control logic that compiles and delivers control sequences” (see 2nd paragraph of page 8 from the Remarks).
The examiner respectively disagrees.
First of all, the related claimed limitation or even claims 45 and 56 were and are rejected under the combination of references instead of individual reference alone. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Secondly, no matter the previous non-Final Office Action mailed by 10/1/2025 or this current Final Office Action, the usage or combining reference Hahm is not about linking FPGA type of processor to a quantum system or hybrid quantum system. The usage or combining reference Hahm is about modifying the integrated subsystem having multiple classical processors including CPU type of processor and any/generic type of processor to one single integrated chip having multiple classical processors including CPU type of processor and FPGA type of processor. Before reference Hahm, reference Allen already discloses features of second classical processor comprising processing hardware control logic and such processing hardware control logic compiles and delivers a control sequence to the quantum processor (see Figs. 1A, [0025], [0031]-[0032] and [0041]. Also see the 103 rejection of claim 46 above). Thereby, the actual missing components/limitations before combining reference Hahm is about whether a genic or any type of classical processor within an integrated subsystem can be a FPGA type of processor within an integrated chip instead of linking such FPGA type of processor to a quantum system. In addition, it is understood that a FPGA is required to include certain control logic to perform the configurable or programmable functions/services, and thus the FPGA from reference Hahm by itself alone does include FPGA control logic to perform its configurable or programmable functions/services. Thereby, when combining feature of such FPGA implemented classical processor within an integrated chip from Hahm into the combination of Johnson, Yoshimura and Allen, it is also reasonable to implement the functions performed by the original classical processor control logic from reference Allen (i.e., compiling and delivering a control sequence to the quantum processor) via a FPGA control logic within an integrated chip at the new combination system.
Furthermore, Applicant is suggested to review reference Rigetti (WO 2015178992 A2-IDS recorded) and Ofek et al. (US 20190049495 A1-IDS recorded). Rigetti discloses: FPGA 2362 can control the DAC 2364 to produce a pulse or other signal having one or more frequency components targeted to one or more qubit devices or readout device and The FPGA may receive the instructions from the DLC 2820 and induce the DAC and ADC within the channel controller to produce or process signals that allow the system to perform quantum computation operations realizing those instructions (see Fig. 23B, [0315] and [0375]). Ofek et al. discloses: a field programmable gate array (FPGA) 3940 operates both the quantum-control pulse sequences and the data acquisition process (see [0400]).
Therefore, Claims 45, 47-51, 54-56, 58-60 and 63-67 are rejected.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Nordholt et al. (US 20130083925 A1) discloses: the processor/FPGA 120 controls operations associated with recording the quantum state and sending basis per pulse for the QC, transmitting the recorded sending bases, to, and otherwise processing conventional QC protocol elements (see [0032]).
Versluis et al. (US 20210279134 A1) discloses: a control computer or an FPGA or another control system will control timing and execution of the flux control pulses for each unit cell according to FIG. 12 when the qubit frequency layout is equal to the one shown in FIG. 10. (see [0081]).
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/Zhi Chen/
Patent Examiner, AU2196
/APRIL Y BLAIR/Supervisory Patent Examiner, Art Unit 2196
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