DETAILED ACTION
Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner Notes
Examiner cites particular columns and line numbers in the references as applied to the claims below for convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references cited in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: "work queues configured to" and “circuitry configured to” in claim 1.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
For clarity of the record, the Examiner would like to point to claim 1 which discloses the work queues and circuitry is executed by a classical computer.
Claim 1 recites “one or more work queues configured to store an assigned kernel”. Since the function of storing an assigned kernel as recited in claim 1 is not coextensive with a general purpose classical computer, paragraph [0019] of the specification is read upon to disclose an algorithm for storing an assigned kernel, in which a kernel is a command indicating to launch a kernel and is stored in work queues using system memory provided by memory devices. Thus, the Examiner’s interpretation of the “work queues configured to store an assigned kernel” as recited in claim 1 is any classical computer that stores commands to launch a kernel in a queue.
Claim 1 further recites “circuitry configured to: receive a first command to remove a first kernel from a first work queue […]; and assign the first command to a second execution pipe […]”. Since the function of receiving and assigning commands as recited in claim 1 is not coextensive with a general purpose classical computer, paragraphs [0031]-[0032] are read upon to disclose an algorithm for receiving and assigning commands, in which the circuitry supports communication protocols and queues for storing requests and responses and the circuity is a semiconductor die or “chiplet”. Thus, the Examiner’s interpretation of the “circuitry configured to receive a first command to remove a first kernel from a first work queue […]; and assign the first command to a second execution pipe […]” as recited in claim 1 is any classical computer that receives and assigns commands by a semiconductor die.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-2 , 4-9, 11-16, and 18-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (abstract idea) without significantly more.
Step 1:
Claim 1 is directed to An apparatus comprising: a series of parts, and is therefore directed to a machine, which is one of the four statutory categories.
Step 2A, Prong One:
Claim 1 recites the limitations:
assigning the first command to a second execution pipe of the plurality of execution pipes;
responding to an indication that the second execution pipe is idle
all of which can be performed in the human mind through observation, evaluation, judgement and opinion, with the aid of pen and paper, and are therefore reciting a mental process.
Accordingly, claim 1 recites a judicial exception (i.e., an abstract idea).
Examiner notes that the interpretation of the recited system as a “mental process” is reasonable, because the broadest reasonable interpretation of the claim language recites an embodiment with one compute operation, one component, and one compute instance— a human can mentally replicate this embodiment since no functions specific to computer technology are recited.
Step 2A, Prong Two:
The additional elements recited in claim 1 include:
(i) a plurality of execution pipes, each comprising one or more work queues configured to store an assigned kernel
(ii) circuitry
(iii) receiving a first command to remove a first kernel from a first work queue of a first execution pipe
Regarding the additional elements (i) and (ii), the limitations recited are mere instructions to implement the limitations which can be performed in the human mind, i.e., the judicial exception, on a computer, which is not indicative of integration into a practical application. See MPEP 2106.04(d) and 2106.05(f).
Regarding the additional element (iii), the limitation recited amounts to insignificant extra solution activity of mere data gathering, as it is merely gathering the data for the judicial exception, which is not indicative of integration into a practical application. See MPEP 2106.04(d) and 2106.05(g).
Furthermore, the combination of additional elements results in mere instructions to implement the exception on a computer and gathering the data for the exception, which is insignificant extra-solution activity. This combination of additional elements fails to integrate the judicial exception into a practical application. See MPEP 2106.04(d).
Step 2B:
Regarding the additional elements (i) and (ii), the limitations are reciting generic computing components to perform the steps which can be performed in the human mind, which is mere instructions to apply the exception. The courts have found adding mere instructions to apply the exception is not enough to amount to significantly more than the recited judicial exception. See MPEP 2106.05(b) and 2106.05(g).
Regarding the additional element (iii), the limitation recited is insignificant extra-solution activity which amounts to mere data gathering. Further, the additional element (iii) is retrieving information in memory, which has been identified by the courts as well-understood, routine, and conventional activity. See MPEP 2106.05(d). The courts have found adding insignificant extra-solution activity and well-understood, routine, and conventional activity is not enough to amount to significantly more than the recited judicial exception. See MPEP 2106.05(a) and 2106.05(g).
The combination of these additional elements amounts to a machine comprising parts which can be performed mentally implemented by generic computing components, and comprising a step of insignificant extra-solution and well-understood, routine and conventional activity. Therefore, the additional elements, when considered individually and in combination, fail to add an inventive concept to the claim.
Consequently, claim 1 as a whole does not amount to significantly more than the recited judicial exceptions and the claim is not eligible.
Claim 2 is dependent on claim 1, and therefore inherits the same judicial exception recited in claim 1. Further, claim 2 recites generating the indication responsive to […] which can be performed in the human mind through observation, evaluation, judgement and opinion, with the aid of pen and paper, and are therefore reciting a mental process.
Claim 2 recites the additional element receiving a status specifying each of the one or more work queues of the second execution pipe is unassigned which amounts to mere data gathering, and is therefore insignificant extra-solution activity. This additional element of insignificant extra-solution activity is not indicative of integration into a practical application. Even when considered in combination with the additional elements of claim 1, the additional elements comprise mere instructions to apply the exception and insignificant extra-solution activity, which are not indicative of integration into a practical application.
This additional element of insignificant extra-solution activity is further considered to be the well-understood, routine and conventional activity identified by the court of retrieving information in memory. See MPEP 2106.05(d). This additional element is not enough to amount to significantly more than the recited judicial exceptions. Even when considered in combination with the additional elements of claim 1, the additional elements do not provide an inventive concept and do not amount to significantly more than the recited judicial exceptions. Thus, claim 2 is not eligible.
Claim 4 is dependent on claim 1, and therefore inherits the same judicial exception recited in claim 1. Claim 4 does not recite any additional judicial exceptions beyond those recited in claim 1.
Claim 4 recites the additional element continuing executing a second kernel on a second work queue as the second execution pipe executes the first command which amounts to mere instructions to apply the exception, and is therefore insignificant extra-solution activity. This additional element of insignificant extra-solution activity is not indicative of integration into a practical application. Even when considered in combination with the additional elements of claim 1, the additional elements comprise mere instructions to apply the exception and insignificant extra-solution activity, which are not indicative of integration into a practical application.
This additional element of insignificant extra-solution activity is further considered to be mere instructions to apply an exception. See MPEP 2106.05(f). This additional element is not enough to amount to significantly more than the recited judicial exceptions. . Even when considered in combination with the additional elements of claim 1, the additional elements do not provide an inventive concept and do not amount to significantly more than the recited judicial exceptions. Thus, claim 4 is not eligible.
Claim 5 is dependent on claim 4, and therefore inherits the same judicial exceptions recited in claim 1. Claim 5 recites the limitation responding to one or more of an interrupt and read operation from the second execution pipe which can be performed in the human mind through observation, evaluation, judgement and opinion, with the aid of pen and paper, and are therefore reciting a mental process.
Claim 5 recites the additional element retrieving context state information of the first kernel from the first work queue of the first execution pipe which amounts to mere data gathering, and is therefore insignificant extra-solution activity. This additional element of insignificant extra-solution activity is not indicative of integration into a practical application. Even when considered in combination with the additional elements of claims 1 and 4, the additional elements comprise mere instructions to apply the exception and insignificant extra-solution activity, which are not indicative of integration into a practical application.
This additional element of insignificant extra-solution activity is further considered to be the well-understood, routine and conventional activity identified by the courts of storing and retrieving information in memory. See MPEP 2106.05A(d). This additional element is not enough to amount to significantly more than the recited judicial exceptions. Even when considered in combination with the additional elements of claims 1 and 4, the additional elements do not provide an inventive concept and do not amount to significantly more than the recited judicial exceptions. Thus, claim 5 is not eligible.
Claim 6 is dependent on claim 4, and therefore inherits the same judicial exceptions recited in claim 1. Further, claim 6 recites assigning the mapping operation to a third execution pipe of the plurality of execution pipes in place of a scheduler which can be performed in the human mind through observation, evaluation, judgement and opinion, with the aid of pen and paper, and are therefore reciting a mental process.
Claim 6 recites the additional element receiving an indication of a mapping operation for a third kernel which amounts to mere data gathering, and is therefore insignificant extra-solution activity. This additional element of insignificant extra-solution activity is not indicative of integration into a practical application. Even when considered in combination with the additional elements of claims 1 and 4, the additional elements comprise mere instructions to apply the exception and insignificant extra-solution activity, which are not indicative of integration into a practical application.
This additional element of insignificant extra-solution activity is further considered to be the well-understood, routine and conventional activity identified by the courts of storing and retrieving information in memory. See MPEP 2106.05A(d). This additional element is not enough to amount to significantly more than the recited judicial exceptions. Even when considered in combination with the additional elements of claims 1 and 4, the additional elements do not provide an inventive concept and do not amount to significantly more than the recited judicial exceptions. Thus, claim 6 is not eligible.
Claim 7 is dependent on claim 6, and therefore inherits the same judicial exceptions recited in claims 1 and 6. Further, claim 7 recites responsive to the third execution pipe has completed mapping the third kernel to a work queue of the third execution pipe which can be performed in the human mind through observation, evaluation, judgement and opinion, with the aid of pen and paper, and are therefore reciting a mental process.
Claim 7 recites the additional element sending an indication of completion to the scheduler which amounts to mere data gathering and outputting, and is therefore insignificant extra-solution activity. This additional element of insignificant extra-solution activity is not indicative of integration into a practical application. Even when considered in combination with the additional elements of claims 1 and 6, the additional elements comprise mere instructions to apply the exception and insignificant extra-solution activity, which are not indicative of integration into a practical application.
This additional element of insignificant extra-solution activity is further considered to be the well-understood, routine and conventional activity identified by the courts of receiving or transmitting data over a network. See MPEP 2106.05A(d). This additional element is not enough to amount to significantly more than the recited judicial exceptions. Even when considered in combination with the additional elements of claims 1 and 6, the additional elements do not provide an inventive concept and do not amount to significantly more than the recited judicial exceptions. Thus, claim 7 is not eligible.
Claim 8 recites A method comprising: […] by circuitry of a vector processing circuit: the steps of the apparatus of claim 1. Thus, for the same reasons presented with respect to claim 1, claim 8 is rejected because the claimed invention is directed to an abstract idea without significantly more.
For clarity of the record, the additional elements recited above amount to mere instructions to apply the exception, which is neither indicative of integration into a practical application nor amounts to significantly more than the recited judicial exceptions.
Claims 9 and 11-14 recite substantially the same limitations recited in claims 2 and 4-7, respectively, applied to the method of claim 8. Thus, for the same reasons presented with respect to claims 2 and 4-7, claims 9 and 11-14 are directed to an abstract idea without significantly more and are not eligible.
Claim 15 recites A computing system comprising: a memory configured to store a plurality of kernels; and a vector processing circuit comprising: the steps of the apparatus of claim 1. Thus, for the same reasons presented with respect to claim 1, claim 15 is rejected because the claimed invention is directed to an abstract idea without significantly more.
For clarity of the record, the additional elements recited above amount to mere instructions to apply the exception, which is neither indicative of integration into a practical application nor amounts to significantly more than the recited judicial exceptions.
Claims 16 and 18-20 recite substantially the same limitations recited in claims 2 and 4-6, respectively, applied to the computer program product of claim 15. Thus, for the same reasons presented with respect to claims 2 and 4-6, claims 16 and 18-20 are directed to an abstract idea without significantly more and are not eligible.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
.
Claims 1-4, 6, 8-11, 13, 15-18, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gabor et al. (U.S. Pub. No. 2007/0124736 A1), hereinafter Gabor.
Regarding claim 1, Gabor teaches An apparatus comprising:
a plurality of execution pipes, ([0020] – “FIG. 1 illustrates selected features of an SMT multi-sequencer multithreading processing core 10, where each sequencer is a logical processor that may execute a thread concurrently”; [0019] – “a thread unit, also interchangeably referred to herein as a “sequencer”, is a distinct thread execution resource”) each comprising one or more work queues ([0044] – “system 410 may include […] an acceleration thread task queue 406. […] task queue 406 may be utilized in substantially the same manner […] for alternative systems that include multiple single- or multi-threaded cores”) configured to store an assigned kernel ([0071] – “it is determined whether any additional acceleration threads remain pending in the AT task queue 406”); and
circuitry configured to: receive a first command to remove a first kernel from a first work queue of a first execution pipe of the plurality of execution pipes ([0056] – “triggering of the acceleration thread is again performed by the acceleration unit 404 and may, in particular, be performed in response to an instruction that indicates a thread unit could use an acceleration thread”; [0057] – “the acceleration unit 404 may consult a task queue 406 to determine if any acceleration threads are pending. […] The acceleration unit 404 may pop the entry from the task queue”); and
assign the first command to a second execution pipe of the plurality of execution pipes ([0056] – “triggering of the acceleration thread is again performed by the acceleration unit 404 and may, in particular, be performed in response to an instruction that indicates a thread unit could use an acceleration thread”; [0057] – “acceleration unit 404 may pop the entry from the task queue and provide this IP to the idle sequencer's next-instruction-pointer and fetch logic 120”), responsive to an indication that the second execution pipe is idle ([0040] – “during idle time 208 illustrated in FIG. 2, thread unit 2 may be utilized to perform other work”; [0044] – “a system 410 to detect and utilize idle OS-managed processors to execute acceleration threads”; [0045] – “the method 500 detects when an OS-managed sequencer becomes idle”).
Regarding claim 2, Gabor teaches The apparatus as recited in claim 1. Gabor further teaches wherein the circuitry is further configured to
generate the indication responsive to receiving a status specifying each of the one or more work queues of the second execution pipe is unassigned ([0049] – “may issue a halt or monitor/mwait instruction pair to a sequencer if it determines that it has no available work to schedule on the sequencer”).
Regarding claim 3, Gabor teaches The apparatus as recited in claim 2. Gabor further teaches wherein the circuitry is further configured to
generate one or more of an interrupt operation ([0039] – “issuance of an interrupt or by writing to a location being monitored in response to a previous monitor instruction”) and read operation ([0060] – “the context of the OS-visible thread is restored from the private context save area 402”) to access configuration registers of the second execution pipe ([0051] – “Such context save operation 506 may be performed by the acceleration unit 404. During the context save operation at block 506, all or some of the context information for the idle OS-managed thread is saved”).
Regarding claim 4, Gabor teaches The apparatus as recited in claim 1. Gabor further teaches wherein the first execution pipe continues executing a second kernel on a second work queue as the second execution pipe executes the first command ([0026] – “system 150 illustrated in FIG.1 may include two or more separate physical processors [...] each capable of executing a different thread such that execution of at least portions of the different threads may be ongoing at the same time”; [0029] – “the code portions 202, 204 represent OS-managed threads that may be executed concurrently”; [0030] – “The thread units 1 and 2 illustrated in FIG. 2 are each capable of concurrently executing a thread associated with its respective application code 202, 204"”;).
Regarding claim 6, Gabor teaches The apparatus as recited in claim 4. Gabor further teaches wherein responsive to receiving an indication of a mapping operation for a third kernel ([0031] – “a plurality of threads that are managed by an operating system”)
the circuitry is further configured to assign the mapping operation to a third execution pipe of the plurality of execution pipes in place of a scheduler ([0045] – “method 500 detects when an OS-managed sequencer becomes idle, schedules an acceleration thread to run on the sequencer while it is idle […] the method 500 provides for acceleration threads without intervention of an operating system scheduler”).
Regarding claim 8, Gabor teaches A method, comprising:
receiving, by circuitry of a vector processing circuit ([0026] – “A first multi-core multithreading system 150 illustrated in FIG. 1”), a first command specifying removing a first kernel from a first work queue of a first execution pipe of a plurality of execution pipes ([0020] – “FIG. 1 illustrates selected features of an SMT multi-sequencer multithreading processing core 10, where each sequencer is a logical processor that may execute a thread concurrently”; [0019] – “a thread unit, also interchangeably referred to herein as a “sequencer”, is a distinct thread execution resource”; [0056] – “triggering of the acceleration thread is again performed by the acceleration unit 404 and may, in particular, be performed in response to an instruction that indicates a thread unit could use an acceleration thread”; [0057] – “the acceleration unit 404 may consult a task queue 406 to determine if any acceleration threads are pending. […] The acceleration unit 404 may pop the entry from the task queue”), each comprising one or more work queues ([0044] – “system 410 may include […] an acceleration thread task queue 406. […] task queue 406 may be utilized in substantially the same manner […] for alternative systems that include multiple single- or multi-threaded cores”) configured to store an assigned kernel ([0071] – “it is determined whether any additional acceleration threads remain pending in the AT task queue 406”); and
assigning, by the circuitry, the first command to a second execution pipe of the plurality of execution pipes ([0056] – “triggering of the acceleration thread is again performed by the acceleration unit 404 and may, in particular, be performed in response to an instruction that indicates a thread unit could use an acceleration thread”; [0057] – “acceleration unit 404 may pop the entry from the task queue and provide this IP to the idle sequencer's next-instruction-pointer and fetch logic 120”), responsive to an indication that the second execution pipe is idle ([0040] – “during idle time 208 illustrated in FIG. 2, thread unit 2 may be utilized to perform other work”; [0044] – “a system 410 to detect and utilize idle OS-managed processors to execute acceleration threads”; [0045] – “the method 500 detects when an OS-managed sequencer becomes idle”).
Regarding claim 15, Gabor teaches A computing system (computing system 800) comprising:
a memory configured to store a plurality of kernels (memory system 840); and
a vector processing circuit (processor core 804) comprising:
a plurality of execution pipes ([0020] – “FIG. 1 illustrates selected features of an SMT multi-sequencer multithreading processing core 10, where each sequencer is a logical processor that may execute a thread concurrently”; [0019] – “a thread unit, also interchangeably referred to herein as a “sequencer”, is a distinct thread execution resource”) , each comprising one or more work queues ([0044] – “system 410 may include […] an acceleration thread task queue 406. […] task queue 406 may be utilized in substantially the same manner […] for alternative systems that include multiple single- or multi-threaded cores”) configured to store an assigned kernel of the plurality of kernels ([0071] – “it is determined whether any additional acceleration threads remain pending in the AT task queue 406”); and
circuitry; and wherein the circuitry is configured to:
receive a first command specifying removing a first kernel of the plurality of kernels from a first work queue of a first execution pipe of the plurality of execution pipes ([0056] – “triggering of the acceleration thread is again performed by the acceleration unit 404 and may, in particular, be performed in response to an instruction that indicates a thread unit could use an acceleration thread”; [0057] – “the acceleration unit 404 may consult a task queue 406 to determine if any acceleration threads are pending. […] The acceleration unit 404 may pop the entry from the task queue”);
assign the first command to a second execution pipe of the plurality of execution pipes ([0056] – “triggering of the acceleration thread is again performed by the acceleration unit 404 and may, in particular, be performed in response to an instruction that indicates a thread unit could use an acceleration thread”; [0057] – “acceleration unit 404 may pop the entry from the task queue and provide this IP to the idle sequencer's next-instruction-pointer and fetch logic 120”), responsive to an indication that the second execution pipe is idle ([0040] – “during idle time 208 illustrated in FIG. 2, thread unit 2 may be utilized to perform other work”; [0044] – “a system 410 to detect and utilize idle OS-managed processors to execute acceleration threads”; [0045] – “the method 500 detects when an OS-managed sequencer becomes idle”).
Claims 9-11, 13, 16-18, and 20 recite substantially the same limitations as those in claims 1-4 and 6 respectively. As such, claims 9-11, 13, 16-18, and 20 are rejected as being anticipated by Gabor for the same reasons presented with respect to claims 1-4 and 6.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 5, 12 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Gabor (U.S. Pub. No. 2007/0124736 A1) in view of Huang et al. (U.S. Pub. No. 2007/0103476 A1), hereinafter Huang.
Regarding claim 5, Gabor teaches The apparatus as recited in claim 4. Gabor further teaches wherein the circuitry is further configured to retrieve context state information of the first kernel from the first work queue of the first execution pipe ([0051] – “Such context save operation 506 may be performed by the acceleration unit 404. During the context save operation at block 506, all or some of the context information for the idle OS-managed thread is saved”),
Gabor fails to expressly teach responsive to one or more of an interrupt and read operations from the second execution pipe.
However, Huang teaches responsive to one or more of an interrupt and read operations from the second execution pipe ([0012] – “GPU is configured to receive an interrupt command while the GPU is processing a first context […] GPU saves the first context to memory”; [0013] – “The GPU includes one or more processors configured to communicate receipt of interrupt commands or internal interrupt events to a processing pipeline. […] The processing pipeline includes a number of components that communicate a state of the first context when interrupted to the one or more processors, which stores the states for future reference”).
Gabor and Huang are considered to be analogous art to the claimed invention because they are in the same field of invention of processor context saving and restoring. Therefore, it would have been obvious to one of ordinary skill in the art to have modified the methods of Gabor to incorporate the interrupt and read operations of Huang such that the processors communicate commands as taught by Huang. Incorporating the methods of Huang may reduce bottlenecking and create a more efficient sharing of resources: reducing idle time (see Huang: [0005] and [0013]).
Claims 12 and 19 recite substantially the same limitations as those recited in claim 5. As such, claims 12 and 19 are rejected as being unpatentable over Gabor in view of Huang for the same reasons presented with respect to claim 5.
Claims 7 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Gabor (U.S. Pub. No. 2007/0124736 A1) in view of Vembu et al. (U.S. Pub. No. 2017/0256019 A1), hereinafter Vembu.
Regarding claim 7, Gabor teaches The apparatus as recited in in claim 6. Gabor further teaches wherein the circuitry is further configured to […] responsive to the third execution pipe has completed mapping the third kernel to a work queue of the third execution pipe ([0045] – “the method 500 detects when an OS-managed sequencer becomes idle, schedules an acceleration thread to run on the sequencer while it is idle […] provides for acceleration threads without intervention of an operating system scheduler”; [0057] – “The triggering logic of the acceleration unit 404 may consult a task queue 406 to determine if any acceleration threads are pending [...] The acceleration unit 404 may pop the entry from the task queue and provide this IP to the idle sequencer's next-instruction-pointer and fetch logic”).
Gabor fails to expressly teach send an indication of completion to the scheduler.
However, Vembu teaches send an indication of completion to the scheduler ([0115] – “When a graphics engine completes a set of work items, an interrupt is triggered to indicate that the work items are complete”; [0124] – “The scheduler 1402 can prepare the submission queue 1411 and write to the control register 1412 when the elements on the execution queue 1421 are complete”).
Gabor and Vembu are considered to be analogous art to the claimed invention because they are in the same field of invention of processor workload scheduling. Therefore, it would have been obvious to one of ordinary skill in the art to have modified the methods of Gabor to incorporate the indication of completion of Vembu such that the scheduler can receive the completion status as taught by Vembu. Incorporating the methods of Vembu may create a more efficient submission of workloads to a high performance graphics sub-system (see Vembu: [0025]).
Claim 14 recites substantially the same limitations as those recited in claim 7. As such, claim 14 is rejected as being unpatentable over Gabor in view of Vembu for the same reasons presented with respect to claim 7.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Dash et al. (U.S. Pub. No. 2020/0043123 A1) teaches a GPU-style processor that can run graphics work and compute work at the same time on the same processing unit or using greedy modes (see Abstract, [0008], [0014])
Huang et al. (U.S. Pub. No. 2024/0419482 A1) teaches a method for context switching using preemption requests and SDMA/DMA circuitry (see Abstract, [0012])
Sander et al. (U.S. Pub. No. 2012/0192201 A1) teaches a method for balancing a workload by sharing work between heterogenous processors (see [0008], [0011], [0037])
Lin et al. (U.S. Pub. No. 2009/0172683 A1) teaches a method for managing tasks between an MPU and DSP using idle processing units (see Abstract, [0022], [0046])
Soe et al. (U.S. Pub. No. 2020/0159680 A1) teaches an integrated circuit that offloads work to multiple compute units without constantly polling to see which one is free (see [0007], [0017], [0050], [0084])
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/JULIANNE CATHERINE LAPOINTE/Examiner, Art Unit 2194 /KEVIN L YOUNG/Supervisory Patent Examiner, Art Unit 2194
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