Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Response to Amendment
The Amendment filed March 13, 2026 has been entered.
Amendments and arguments presented therein overcome the previous objection(s) and “Second” rejection under 35 U.S.C. 112(b) in this application.
Claims 15, 28, and 32-33 are rejected over the previously applied reference(s).
Claim Objections
Claims 23-27 and 36 are objected to because of the following informalities: “a first output of the frequency adjuster circuitry” in claim 23 should be changed to “the first output of the frequency adjuster circuitry”. Dependent claims are objected for at least the reasons of including the above discussed deficiencies by the way of their claim dependency.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 15-20 and 23-36 are rejected under 35 U.S.C. 112(b):
First
As being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are: the connection between the frequency adjuster circuitry and the clock buffer circuitry (claim 28); and the connection between the feedback amplifier and the frequency adjuster circuitry (e.g., claims 15, 23, and 28) so that the feedback amplifier has feedback as described (e.g., may be corrected by reciting “the output of the feedback amplifier coupled to another input of the frequency adjuster circuitry” in each independent claim).
Dependent claims of claims 15, 23, and 28 are rejected for the above-discussed reasons.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 15, 28, and 32-33 are rejected under 35 U.S.C. 103 as being unpatentable over US 11,159,152 to Ayya et al. (“Ayya”).
With respect to claim 15, insofar as understood, Ayya discloses in Fig. 1 an apparatus comprising:
a clock buffer circuitry (e.g., 120) including:
a first input coupled to the first output of the frequency adjuster circuitry and a second input (e.g., outputs of 110) coupled to the second output of the frequency adjuster circuitry;
a first clock buffer output (e.g., outp) and a second clock buffer output (e.g., outn);
a first resistor (e.g., 412A) having a first terminal (e.g., terminal of 412A coupled to outp via 140A) and a second terminal (e.g., 430), the first terminal (e.g., terminal of 412A coupled to outn indirectly via 140B) coupled to the first clock buffer output (e.g., outn); and
a second resistor (e.g., 412B) having a first terminal (e.g., terminal of 412B coupled to outn via 140B) and a second terminal (e.g., 430), the first terminal (e.g., terminal of 412B coupled to outn indirectly via 140B) of the second resistor (e.g., 412B) coupled to the second clock buffer output (e.g., outn) and the second terminal (e.g., 430) of the second resistor (e.g., 412B) coupled to the second terminal (e.g., 430) of the first resistor (e.g., 412A); and
a feedback amplifier (e.g., 158) having a first input, a second input, and an output, the first input (e.g., the inverting input) of the feedback amplifier (e.g., 158) coupled to the second terminal (e.g., 430) of the first resistor (e.g., 412A) and the second terminal (e.g., 430) of the second resistor (e.g., 412B). Ayya fails to disclose that clkp and clkn are generated by an oscillator having an output and a frequency adjuster having an input, a first output, and a second output, the input of the frequency adjuster circuitry coupled to the output of the oscillator. However, it was notoriously well known to a person of ordinary skill in the art before the effective filing date of the claimed invention that differential clock signals may be generated using an oscillator and a frequency adjuster coupled to the output of the oscillator to produce the differential clock signals. The foregoing common knowledge or well-known in the art statement is taken to be admitted prior art because applicant failed to timely traverse the examiner’s assertion of official notice. See MPEP 2144.03(C). Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to produce clkp and clkn in Fig. 1 pf Ayya using the notoriously well-known method of producing differential clock signals by using an oscillator and a frequency adjuster coupled to the output of the oscillator because the production of clkp and clkn in Fig. 1 pf Ayya requires a specific implementation in fabrication and the notoriously well-known method provides such a specific implementation.
With respect to claim 28, insofar as understood, the above discussion for claim 15 similarly applies. Further, the first and second outputs of the clock buffer circuitry in claim 28 respectively correspond to the first and second clock buffer outputs in claim 15.
With respect to claim 32, the third clock signal is an inverse of the first clock signal (e.g., clkp is an inverse of clkn).
With respect to claim 33, the feedback amplifier circuitry (e.g., 158) is configurable to generate an output voltage (e.g., output of 158) based on a comparison of a common mode voltage of the clock buffer circuitry to a reference voltage (e.g., 158 is a common mode amplifier circuit (e.g., Col. 3 ll. 38-40) comparing the common mode voltage at the inverting input to a reference at the noninverting input).
Response to Arguments
Applicant's arguments filed March 13, 2026 have not been found persuasive. For example, Applicant argues that Ayya as modified above for claim 15 fails to disclose newly added features of claim 15. However, as stated above in the main body of the rejection, the features are disclosed in Ayya as modified above for claim 15.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Allowable Subject Matter
Claims 16-20, 23-27, 29-31, and 34-36 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112, set forth in this Office action, and to include all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jung KIM whose telephone number is (571)270-7964. The examiner can normally be reached on M-F from 9AM to 5:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Regis BETSCH, can be reached at (571)270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JUNG KIM/
Primary Examiner, Art Unit 2842