DETAILED ACTION
This office action is in response to the reply filed on 02/24/2026.
Claims 21-40 are pending in the application and have been examined.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 21-23, 25-30, 32-37, and 39-40 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Howes (U.S. Publication 2014/0157287).
Regarding claims 21, 28, and 35 Howes discloses an apparatus comprising: a plurality of parallel lanes of execution, each comprising circuitry configured to execute instructions of applications [Fig. 5; paragraphs 0022, 0065-0067; the system executes threads on multi-lane hardware]; and circuitry configured to: cause execution of a first plurality of instructions of a first application on the plurality of parallel lanes of execution [paragraph 0046; the system executes a thread on the lanes of the processor]; and cause execution of a second plurality of instructions of code different from the first application on the plurality of parallel lanes of execution, responsive to an interrupt detected during execution of the first plurality of instructions [paragraphs 0047-0056; a signal is received that indicates that a context switch will occur, causing a different thread to execute on the lanes of the processor]; and wherein during execution of the second plurality of instructions, each of one or more of the plurality of parallel lanes of execution is configured to store corresponding first context state of execution of the first application [paragraphs 0047-0063, 0075; every time a thread yields the processor, the associated context is stored in a memory].
Regarding claims 22, 29, and 36, Howes discloses the apparatus as recited in claim 21, wherein the first context state comprises execution state specific to each of the one or more of the plurality of parallel lanes of execution [paragraphs 0047-0063, 0075; the system stores data from lanes of execution].
Regarding claims 23, 30, and 37, Howes discloses the apparatus as recited in claim 21, wherein fewer than all of the plurality of parallel lanes of execution store the first context state during execution of the second plurality of instructions [paragraphs 0047-0063, 0075; context state is stored; it should be noted that this limitation is very broad because “the first context state” can simply refer to the specific state stored for a given lane].
Regarding claim 25, Howes discloses the apparatus as recited in claim 21, wherein one or more of the plurality of parallel lanes of execution are configured to detect a condition that generates an indication of the interrupt [paragraphs 0047-0056; a signal is received that indicates that a context switch will occur, causing a different thread to execute on the lanes of the processor].
Regarding claims 26, 33, and 40, Howes discloses the apparatus as recited in claim 1, wherein the circuitry is further configured to access a memory mapped input/output (MMIO) storage location in a local memory of the apparatus to check for the indication of the interrupt [paragraph 0049; a register that is accessible in memory is accessed to determine whether an interrupt has occurred].
Regarding claims 27 and 34, Howes discloses the apparatus as recited in claim 1, wherein each of the one or more of the plurality of parallel lanes of execution is further configured to read third context state of a fourth plurality of instructions of a second application different from the first application and the code [paragraphs 0021, 0047-0063, 0075; the system executes multiple processes each of which includes multiple threads for which context is saved and restored as described above; alternatively, the system executes multiple workgroups or kernels].
Regarding claims 32 and 39, Howes discloses the method of claim 28, wherein detecting the interrupt comprises detecting an asynchronous interrupt generated by one or more of the plurality of parallel lanes of execution [paragraphs 0047-0056; a signal is received that indicates that a context switch will occur, causing a different thread to execute on the lanes of the processor].
Allowable Subject Matter
Claims 24, 31, and 38 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed 02/24/2026 have been fully considered but they are not persuasive.
Applicant first argues that the yield instruction of Howes is not the same as an interrupt. The examiner’s position is that a yield instruction that interrupts execution of the executing thread constitutes an interrupt, and the argument is therefore not persuasive.
Applicant next argues that Howes does not disclose that the storage of state of the first application does not occur during execution of the second application. Applicant’s argument appears to rely on the idea that the data is not moved to the storage during execution of the second application. However, the concept of “storing” data includes not just moving data to a storage, but also the step of actually holding that data in the storage. In Howes, the data of the first application is clearly held in the storage during execution of a second application. The argument is therefore not persuasive.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/COREY S FAHERTY/Primary Examiner, Art Unit 2183
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