DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-5 and 7-21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4-5, 7-11, 14-17 and 20-21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yanamadala (US 2019/0278311).
For claim 1, Yanamadala teaches a device (Figure 5) comprising:
one or more input power networks (signal line directly connected to the top terminal of 540);
one or more gated output power networks (signal line directly connected to the top terminal of 530); and
a plurality of field effect transistors (switch group 520, [52] and as further explained below) located in parallel to one another (as understood by examination of Figure 5C) and configured to receive power supplied by the one or more input power networks (output of 540, [29]) and a common pulse width modulated control signal (control signal provided to switch group 520) received by the plurality of field effect transistors (as explained below), wherein the plurality of field effect transistors is configured to gate the supplied power in response to receiving the common pulse width modulated control signal and convey the gated power to the one or more gated output power networks (as explained below).
It is noted that Applicant has, in [52] of the Specification, defined “power network” to include implementations such as a wire.
Yanamadala teaches that for Figure 1B [27]:
at time TA1, only one switch (521) is closed [27];
at time TA2, two or more switches are closed, switch group 520 remains open [28];
At time TA3, all switches are closed [29];
Thus, since each switch within switch group 520 are controlled identically for every power requirement in Figure 1B, it can be understood that the plurality of switches within 520 receive a common PWM control signal.
For claim 4, Yanamadala further teaches:
a pulse width modulation control circuit (200, Figure 2A) supplying the pulse width modulated control signal to the plurality of field effect transistors ([22]), wherein the pulse width modulation control circuit is configured to cause the pulse width modulated control signal to exhibit a period having a duration less than a characteristic response time of the one or more gated output power networks and a configurable duty cycle (as understood by [22]-[25] and Figure 1B).
For claim 5, Yanamadala further teaches:
the device corresponds to one or more semiconductor layers and/or one or more die of a semiconductor device ([2]-[3] and [65]) and wherein the common pulse width modulated control signal provides a continuous conductance profile (parameters associated with activity level, Abstract).
For claim 7, Yanamadala further teaches:
the pulse width modulation control circuit is located at least one of:
on a semiconductor device package (e.g., a SoC or IC) including the semiconductor device ([2]-[3] and [65]).
For claim 8, Yanamadala further teaches:
the device corresponds to one or more semiconductor layers and at least one of the one or more semiconductor layers corresponds to a package substrate of a semiconductor device package (e.g., a SoC or IC, [2]-[3] and [65]).
For claim 9, Yanamadala further teaches:
the pulse width modulation control circuit is located at least one of:
on the package substrate (e.g., a SoC or IC, [2]-[3] and [65]);
on the semiconductor device package including the package substrate; or
off of the semiconductor device package including the package substrate ([2]-[3] and [65]).
For claim 10, Yanamadala teaches a semiconductor device package (e.g., a SoC or IC, [2]-[3] and [65]) comprising:
a package substrate (within the SoC or IC);
one or more die located on the package substrate (within the SoC or IC); and
a plurality of field effect transistors (switch group 520, [52] and as further explained below) located in parallel to one another (as understood by examination of Figure 5C) and configured to receive power supplied by the one or more input power networks (output of 540, [29]) of the semiconductor device package and a common pulse width modulated control signal (control signal provided to switch group 520, as explained below), wherein the plurality of field effect transistors is configured to gate the supplied power in response to the common pulse width modulated control signal and convey the gated power to one or more gated output power networks of the semiconductor device package (signal line directly connected to the top terminal of 530, as explained below).
It is noted that Applicant has, in [52] of the Specification, defined “power network” to include implementations such as a wire.
Yanamadala teaches that for Figure 1B [27]:
at time TA1, only one switch (521) is closed [27];
at time TA2, two or more switches are closed, switch group 520 remains open [28];
At time TA3, all switches are closed [29];
Thus, since each switch within switch group 520 are controlled identically for every power requirement in Figure 1B, it can be understood that the plurality of switches within 520 receive a common PWM control signal.
For claim 11, Yanamadala further teaches:
the plurality of field effect transistors is located in at least one of: the package substrate; or the one or more die ([2]-[3] and [65]).
For claim 14, Yanamadala further teaches:
a pulse width modulation control circuit (200, Figure 2A) supplying the common pulse width modulated control signal to the plurality of field effect transistors ([22]) and wherein the pulse width modulation control circuit provides a continuous conductance profile (parameters associated with activity level, Abstract).
For claim 15, Yanamadala further teaches:
the pulse width modulation control circuit is configured to cause the pulse width modulated control signal to exhibit a period having a duration less than a characteristic response time of the one or more gated output power networks and a configurable duty cycle (as understood by [22]-[25] and Figure 1B).
For claim 16, Yanamadala further teaches:
the pulse width modulation control circuit is located at least one of: on the one or more die; on the package substrate; on the semiconductor device package including the package substrate; or off of the semiconductor device package including the package substrate ([2]-[3] and [65]).
For claim 17, Yanamadala teaches a method (Figure 5) comprising:
configuring one or more input power networks (signal line directly connected to the top terminal of 540) to supply power to a plurality of field effect transistors (switch group 520, [52] and as further explained below) located in parallel to one another (as understood by examination of Figure 5C);
configuring one or more gated output power networks (signal line directly connected to the top terminal of 530) to receive gated power from the plurality of field effect transistors (as explained below); and
configuring the plurality of field effect transistors to receive a common pulse width modulated control signal (control signal provided to switch group 520) and to gate the supplied power in response to the pulse width modulated control signal received by all field effect transistors of the plurality of field effect transistors (as explained below).
It is noted that Applicant has, in [52] of the Specification, defined “power network” to include implementations such as a wire.
Yanamadala teaches that for Figure 1B [27]:
at time TA1, only one switch (521) is closed [27];
at time TA2, two or more switches are closed, switch group 520 remains open [28];
At time TA3, all switches are closed [29];
Thus, since each switch within switch group 520 are controlled identically for every power requirement in Figure 1B, it can be understood that the plurality of switches within 520 receive a common PWM control signal.
For claim 20, Yanamadala further teaches:
configuring a pulse width modulation control circuit (200, Figure 2A) to supply the pulse width modulated control signal to the plurality of field effect transistors ([22]), wherein the pulse width modulation control circuit is configured to cause the pulse width modulated control signal to exhibit a period having a duration less than a characteristic response time of the one or more gated output power networks and a configurable duty cycle (as understood by [22]-[25] and Figure 1B).
For claim 21, Yanamadala further teaches:
all field effect transistors of the plurality of field effect transistors are configured to turn on or off simultaneously in response to the pulse width modulation (as discussed in the rejection of claim 1 above).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2-3, 12-13 and 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yanamadala.
For claims 2, 12 and 18, Yanamadala teaches the limitations of claim 1, 10 and 17 as cited above but fails to teach the transistor strengths as claimed.
It is noted that Yanamadala teaches “in any of the charge storage units described herein, the switches may be implemented by transistors. Any suitable transistor known in the art can be used, e.g., a bipolar junction transistor, a metal oxide semiconductor field effect transistor (MOSFET), or a combination thereof. Each MOSFET used can either be a p-type MOSFET (PMOS) or an n-type MOSFET (NMOS)” [52].
Thus, one having ordinary skill in the art would understand how to modify the drive strengths as need to any values desired based on design constraints without departing from the scope of Yanamadala’s invention.
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to set the transistor strengths of the plurality of transistors within 520 to be equal since the selection of identical drive strengths as claimed would only involve routine design optimization which as been held to be within the ordinary capabilities of a person having ordinary skill in the art. Note In re Aller, 105 USPQ 233 (1955) where it was held that optimizing particular values is obvious to a person of ordinary skill in the art who would easily be able to set different values within the range of possible values in order to arrive at the best value by simple experimentation. See also In re Boesch, 617, 272 205 USPQ 215 (CCPA 1980) where it was held that discovering an optimum value of a result effective variable involves only routine skill in the art.
For claim 3, 13 and 19, Yanamadala teaches the limitations of claims 1, 10 and 17 as cited above but fails to teach:
wherein the common pulse width modulated control causes all field effect transistors of the plurality of field effect transistors to wear evenly over time.
It is noted that Yanamadala teaches “in any of the charge storage units described herein, the switches may be implemented by transistors. Any suitable transistor known in the art can be used, e.g., a bipolar junction transistor, a metal oxide semiconductor field effect transistor (MOSFET), or a combination thereof. Each MOSFET used can either be a p-type MOSFET (PMOS) or an n-type MOSFET (NMOS)” [52].
Thus, one having ordinary skill in the art would understand that the component values used to implement each transistor within 520 can be selected such that even wear over time occurs since it has been held that discovering a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Liu et al (US 11,271,557) teaches an adaptive gate driver having parallel transistors (Figure 6) but fails to teach the common pulse width modulated signal as claimed.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL CALRISSIAN PUENTES whose telephone number is (571)270-5070. The examiner can normally be reached M-F 9-6:30 (flex).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Taelor Kim can be reached at (571) 270-7166. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL C PUENTES/Primary Examiner, Art Unit 2836
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