Prosecution Insights
Last updated: April 19, 2026
Application No. 18/618,985

DISPLAY PANEL, DRIVING METHOD THEREOF, AND DISPLAY APPARATUS

Non-Final OA §103§112
Filed
Mar 27, 2024
Examiner
LU, WILLIAM
Art Unit
2624
Tech Center
2600 — Communications
Assignee
BOE TECHNOLOGY GROUP CO., LTD.
OA Round
1 (Non-Final)
71%
Grant Probability
Favorable
1-2
OA Rounds
2y 8m
To Grant
78%
With Interview

Examiner Intelligence

Grants 71% — above average
71%
Career Allow Rate
425 granted / 595 resolved
+9.4% vs TC avg
Moderate +6% lift
Without
With
+6.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
31 currently pending
Career history
626
Total Applications
across all art units

Statute-Specific Performance

§101
5.2%
-34.8% vs TC avg
§103
68.4%
+28.4% vs TC avg
§102
9.8%
-30.2% vs TC avg
§112
11.4%
-28.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 595 resolved cases

Office Action

§103 §112
DETAILED ACTION Claims 1-20 filed March 27th 2024 are pending in the current action. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 9, 10, 19 and 20 recites the limitation "the corresponding second multiplexer" in reference to a second multiplexer. There is insufficient antecedent basis for this limitation in the claim in the claims they depend from. The dependencies for these claims should be corrected appropriately. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1, 2, 4, 11, 12 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cassidy et al. (US2008/0303749) in view of Sato (US2011/0285756) Consider claim 1, where Cassidy teaches a display panel, comprising a display region and a non-display region surrounding the display region, (See Cassidy Fig. 1 where a display device comprises a display 6 and driving circuitry located in the periphery of the display) wherein the display region has a plurality of first region groups arranged in a first direction, the first region groups extend in a second direction, (See Cassidy ¶67-69 where the display comprises a column driver circuit that supplies data in the column direction and extends in a row direction in order to form a matrix) each of the first region groups have at least one region disposed in the second direction, the first direction intersects with the second direction, each of the first region groups internally comprises a plurality of first signal lines arranged in the first direction, (See Cassidy Fig. 4 and ¶67-69, 144 where the display comprises a column driver circuit that supplies data in the column direction through a plurality of column signal lines. Thus, the data lines form a plurality of first signal lines arranged in the first direction) and a plurality of pixels arranged in an array, and each pixel of the plurality of pixels comprises a plurality of pixel sub-electrodes, (See Cassidy ¶26-27 where each multiplexer element may comprise a sub-element for multiplexing data in a first range and a sub-element for multiplexing data in the second range) an electrophoretic display; (See Cassidy ¶157 where the active matrix configuration may be used to drive an electrophoretic display device) the non-display region comprises: a plurality of second signal lines corresponding to the second direction; (See Cassidy Fig. 4 and ¶66-70 where Vdata extends in the row direction in order to connect to the multiplexer circuits 50) and a plurality of first multiplexers in one-to-one correspondence with the plurality of first region groups, wherein the plurality of first multiplexers share the plurality of second signal lines, output ends of the first multiplexers are connected to the first signal lines in the corresponding first region groups one to one, and the first signal lines are electrically connected to the pixel sub-electrodes in the pixels arranged in the second direction; (See Cassidy Fig. 4 and ¶65-68, 144 where each multiplexer element 50 is associated with an individual column, thus a one to one mapping. The columns intersect with the row address signal in order to drive the pixels. Each of the columns can control a sub-element of a pixel such that each of the sub elements R, G, and B together form a pixel) and the plurality of first multiplexers, under control of a first gating signal, transmit signals on the plurality of second signal lines to the pixel sub-electrodes in the pixels electrically connected to the first signal lines in the corresponding first region groups in a time-sharing manner, (See Cassidy Fig. 4 and ¶65-68 where each multiplexer element 50 is associated with an individual column, thus a one to one mapping. The columns intersect with the row address signal in order to drive the pixels. Thus, the data can be loaded in the columns while being addressed using the row address signal line) so that all the pixel sub-electrodes corresponding to each row of pixels in the corresponding first region groups are simultaneously loaded with corresponding voltages, or all the pixel sub-electrodes corresponding to one scanning line in the display region are simultaneously loaded with corresponding voltages. (See Cassidy ¶150-153 where the pins are simultaneously loaded according to their cycle. For instance, one cycle will drive all odd pins and a separate cycle will drive all even pins.) Cassidy teaches wherein the active matrix may be used to drive an electrophoretic display, (See Cassidy ¶157) however Cassidy does not explicitly teach an electrophoretic liquid layer, and a common electrode sequentially stacked on a base substrate. However, in the field of electrophoretic display devices Sato teaches an electrophoretic liquid layer, and a common electrode sequentially stacked on a base substrate. (See Sato Fig. 8 and ¶4, 100, 154 where electrophoretic displays operate by applying a common potential to a counter electrode 37 to displace particles in a liquid dispersion medium 32 and that these structures are placed on top of a base substrate 30) Therefore, it would have been obvious for one of ordinary skill in the art that the electrophoretic display being driven by Cassidy would comprise known components within an electrophoretic display as taught by Sato. Thus, using known components within a known device to yield predictable results. Consider claim 2, where Cassidy in view of Sato teaches the display panel according to claim 1, wherein each of the first multiplexers comprises: a plurality of first thin film transistors in one-to-one correspondence with the plurality of first signal lines; (See Cassidy Figs. 3, 4 and ¶63-70 where each of the multiplexer elements 50 comprises a multiplexer transistor 30 such that each element controls a column data line) and each of the first thin film transistors comprises a first control electrode, a first electrode and a second electrode, and each second electrode is connected to one of the first signal lines in the corresponding first region group. (See Cassidy Figs. 3, 4 and ¶63-70 where the multiplexer transistor comprises a gate control electrode and a first electrode connected to Vdata and a second electrode connected to the column data line) Consider claim 4, where Cassidy in view of Sato teaches the display panel according to claim 2, wherein the first control electrode in the first multiplexer are connected to different first control lines respectively, all the first electrodes in the first multiplexer are connected to one second signal line, (See Cassidy Fig. 4 and ¶66-70 where Vdata extends in the row direction in order to connect to the multiplexer circuits 50) and the first control electrodes of the first thin film transistors located at the same relative position in the plurality of first multiplexers are connected to one first control line; and the non-display region comprises the first control line. (See Cassidy ¶66-70 where it will be apparent to those skilled in the art that each block of three multiplexer elements can share the three select lines. Thus, each column1 may provide be connected to the select1 signal of each respective block) Consider claim 11, where Cassidy in view of The display panel according to claim 1, wherein each of the pixels further comprises: a plurality of third thin film transistors in one-to-one correspondence with the plurality of pixel sub-electrodes; each of the third thin film transistors comprises a third control electrode, a fifth electrode and a sixth electrode, and each sixth electrode is connected to the corresponding pixel sub-electrode; in a case that the first region group has one region and the first signal lines are the scanning lines, the third control electrodes of the plurality of third thin film transistors are electrically connected to different first signal lines, and the fifth electrodes of the plurality of third thin film transistors are connected to one data line; in a case that the first region group has one region and the first signal lines are the data lines, the third control electrodes of the plurality of third thin film transistors are electrically connected to one scanning line, and the fifth electrodes of the plurality of third thin film transistors are connected to different first signal lines; and in a case that the first region group has a plurality of regions, the third control electrodes of the third thin film transistors are electrically connected to the scanning lines, and the fifth electrodes of the third thin film transistors are connected to the data lines. (See Sato Fig. 5 and ¶124-131 where each pixel 40 comprises transistors TR1/TR2 that are connected to scanning lines and data lines and the pixel sub-electrodes) Therefore, it would have been obvious for one of ordinary skill in the art that the electrophoretic display being driven by Cassidy would comprise known components within an electrophoretic display as taught by Sato. Thus, using known components within a known device to yield predictable results. Consider claim 12, where Cassidy in view of Sato teaches the display panel according to claim 1, wherein the pixels further comprise a plurality of charged particles, and the plurality of charged particles comprise: a plurality of first color charged particles, and a plurality of second color charged particles electrically opposite to the first color charged particles. (See Sato Figs. 3A-D and ¶108-111 where there are black and white particles that are oppositely charged) Therefore, it would have been obvious for one of ordinary skill in the art that the electrophoretic display being driven by Cassidy would comprise known components within an electrophoretic display as taught by Sato. Thus, using known components within a known device to yield predictable results. Consider claim 16, where Cassidy in view of Sato teaches a display apparatus, comprising the display panel according to claim 1. (See Cassidy ¶152 where there is a display device comprising the display array) Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cassidy in view of Sato as applied to claim 1 above, in further view of Iisaka et al. (US2008/0055197) Consider claim 3, where Cassidy in view of Sato teaches the display panel according to claim 2, however, they do not explicitly teach wherein the first control electrodes of all the first thin film transistors in the first multiplexer are connected to one first control line, the first electrodes of all the first thin film transistors in the first multiplexer are connected to different second signal lines respectively, and the first electrodes of the first thin film transistors located at the same relative position in the corresponding first multiplexers of the plurality of first multiplexers are connected to one first signal line; and the non-display region comprises the first control line. However, in an analogous field of endeavor Iisaka teaches wherein the first control electrodes of all the first thin film transistors in the first multiplexer are connected to one first control line, the first electrodes of all the first thin film transistors in the first multiplexer are connected to different second signal lines respectively, and the first electrodes of the first thin film transistors located at the same relative position in the corresponding first multiplexers of the plurality of first multiplexers are connected to one first signal line; and the non-display region comprises the first control line. (See Iisaka fig. 2 and ¶45-47 where the control electrode of the transistors in the sampling circuit 150 are connected to a block selecting circuit 140 such that all of the TFT transistors in a block are selected. Each group of 6 transistors is connected to their respective image signal line 171. The Examiner notes that the claimed structure of the “first multiplexer” is exemplified in Applicant’s Fig. 7 and one of ordinary skill in the art would not necessarily interpret this circuit as a “multiplexer”) Therefore, it would have been obvious for one of ordinary skill in the art to modify the data line selection circuit of Cassidy with other known structures for selecting data lines as taught by Iisaka. One of ordinary skill in the art would have been motived to perform the modification for the advantage of/ benefit of substituting other known structures that perform a similar function to yield similar results. Claim(s) 5, 6, 8-10, 13, 15, 17, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cassidy in view of Sato as applied to claim 1 above, in further view of Zhou et al. (WO2004/107305) Consider claim 5, where Cassidy in view of Sato teaches the display panel according to claim 1, however, they do not explicitly teach wherein in a case that the first region group comprises a plurality of regions arranged in the second direction, (See Zhou Fig. 4 and page 8 lines 8-26 where there are regions 70-72 driven by row drivers 60-62 respectively) the display region further internally comprises a plurality of third signal lines arranged in the second direction, and the third signal lines are electrically connected to the pixel sub-electrodes in the pixels arranged in the first direction; (See Zhou Fig. 4 and page 8 lines 8-26 where there are regions 70-72 driven by row drivers 60-62 through scan lines 41-43 connected to the pixels and arranged in the horizontal direction) the non-display region further comprises: a plurality of fourth signal lines corresponding to the first direction, and a plurality of second multiplexers, the second multiplexers correspond to second region groups, the second region group consist of a plurality of regions located at the same arrangement position in each first region group of the plurality of first region groups, the plurality of second multiplexers share the plurality of fourth signal lines, and output ends of the second multiplexers are connected to the third signal lines in the second region groups one to one; (See Zhou Fig. 4 and page 8 lines 8-26 where there are regions 70-72 located in the display area driven by row drivers 60-62 through scan lines 41-43 connected to the pixels and arranged in the horizontal direction) and the plurality of second multiplexers, under control of a second gating signal, transmit signals on the plurality of fourth signal lines into the corresponding second region groups in a time-sharing manner, (See Zhou’s abstract and page 8 lines 8-26 where the electrophoretic display is driven according to frame periods and controlled by drive lines 24 to control the row drivers 60-62) and in conjunction with the first gating signal corresponding to the plurality of first multiplexers, cause all the pixel sub-electrodes corresponding to each row of pixels in the first region groups to be simultaneously loaded with corresponding voltages, or cause all the pixel sub-electrodes corresponding to one scanning line in the display region to be simultaneously loaded with corresponding voltages. (See Zhou’s abstract and page 8 lines 8-26 where the electrophoretic display is driven according to frame periods and controlled by drive lines 24 to control the row drivers 60-62 in order to control the rows in each of the regions 70-72 in parallel (meaning that one or more lines of the first group 70 and one or more lines of the second group 71 and one or more lines of the third group 72 are driven simultaneously)) However, in an analogous field of endeavor Zhou provides the teachings for the limitations in claim 5 (see mapping above). Therefore, it would have been obvious for one of ordinary skill in the art to modify the driving circuitry of Cassidy to additionally extend to both column and rows as taught by Zhou. One of ordinary skill in the art would have been motivated to perform the modification for the advantage of/ benefit of reducing the frame period as taught by Zhou. (See Zhou’s abstract) Consider claim 6, where Cassidy in view of Sato in view of Zhou teaches the display panel according to claim 5, wherein each of the second multiplexers comprises: a plurality of second thin film transistors in one-to-one correspondence with the third signal lines in the second region group; and each of the second thin film transistor comprises a second control electrode, a third electrode and a fourth electrode, and each fourth electrode is connected to one of the third signal lines in the corresponding second region group. (See Cassidy Fig. 4 and ¶65-68, 144 where each multiplexer element 50 is associated with an individual column, thus a one-to-one mapping. The columns intersect with the row address signal in order to drive the pixels. Each of the columns can control a sub-element of a pixel such that each of the sub elements R, G, and B together form a pixel) (See Zhou’s abstract and page 8 lines 8-26 where the electrophoretic display is driven according to frame periods and controlled by drive lines 24 to control the row drivers 60-62 in order to control the rows in each of the regions 70-72 in parallel (meaning that one or more lines of the first group 70 and one or more lines of the second group 71 and one or more lines of the third group 72 are driven simultaneously)) Consider claim 8, where Cassidy in view of Sato in view of Zhou teaches the display panel according to claim 6, wherein the second control electrodes in the second multiplexer are connected to different second control lines respectively, all the third electrodes in the second multiplexer are connected to one fourth signal line, (See Cassidy Fig. 4 and ¶66-70 where Vdata extends in the row direction in order to connect to the multiplexer circuits 50) and the fourth electrodes of the second thin film transistors located at the same relative position in the plurality of second multiplexers are connected to the different third signal lines; and the non-display region comprises the second control lines. (See Cassidy ¶66-70 where it will be apparent to those skilled in the art that each block of three multiplexer elements can share the three select lines. Thus, each column1 may provide be connected to the select1 signal of each respective block. Thus, the selection circuitry in Zhou can be similarly implemented using the selection circuitry taught in Cassidy) Consider claim 9, where Cassidy in view of Sato teaches the display panel according to claim 1, wherein the non-display region further comprises: a scanning driving circuit and a data driving circuit; when the first signal lines are data lines, the second signal lines are connected between the data driving circuit and the corresponding first multiplexers; when the first signal lines are scanning lines, the second signal lines are connected between the scanning driving circuit and the corresponding first multiplexers; and in a case that the first region groups comprise the plurality of regions, when the first signal lines are one of the data lines or the scanning lines and the second signal lines are the other of the data lines or the scanning lines, (See Cassidy Fig. 4 and ¶65-68 where each multiplexer element 50 is associated with an individual column, thus a one to one mapping. The columns intersect with the row address signal in order to drive the pixels. Thus, the data can be loaded in the columns while being addressed using the row address signal line) Cassidy teaches the first multiplexers connected to the data driving circuit; however Cassidy does not explicitly teach the second signal lines are connected between one of the data driving circuit or the scanning driving circuit and the corresponding first multiplexers, and the fourth signal lines are connected between the other of the data driving circuit or the scanning driving circuit and the corresponding second multiplexers. However, in an analogous field of endeavor Zhou teaches the second signal lines are connected between one of the data driving circuit or the scanning driving circuit and the corresponding first multiplexers, and the fourth signal lines are connected between the other of the data driving circuit or the scanning driving circuit and the corresponding second multiplexers. (See Zhou’s abstract and page 8 lines 8-26 where the electrophoretic display is driven according to frame periods and controlled by drive lines 24 to control the row drivers 60-62) Therefore, it would have been obvious for one of ordinary skill in the art that the row address signal in Cassidy could be controlled using known row addressing methods in the art as taught by Zhou. One of ordinary skill in the art would have been motivated to perform the modification for the advantage of/ benefit of using known methods to yield predictable results. Consider claim 10, where Cassidy in view of Sato in view of Zhou teaches the display panel according to claim 9, wherein the non-display region further comprises a first control circuit and a second control circuit, the first control lines are connected between the first control circuit and the corresponding first multiplexers, (See Cassidy Fig. 2, 4 where the multiplexers are connected to control lines that supply the data signal) and the second control lines are connected between the second control circuit and the corresponding second multiplexers; and the first control circuit and the second control circuit comprise the scanning driving circuit and the data driving circuit. (See Zhou’s abstract and page 8 lines 8-26 where the electrophoretic display is driven according to frame periods and controlled by drive lines 24 to control the row drivers 60-62) Consider claim 13, where Cassidy in view of Sato teaches a driving method based on the display panel according to claim 1, however, they do not explicitly teach comprising: loading voltages corresponding to corresponding rows of pixel sub-electrodes simultaneously row by row in a display region; or, controlling all pixel sub-electrodes corresponding to each row of pixels in each first region group of the plurality of first region groups contained in the display region to be loaded with corresponding voltages simultaneously. (See Zhou’s abstract and page 8 lines 8-26 where the electrophoretic display is driven according to frame periods and controlled by drive lines 24 to control the row drivers 60-62 in order to sequentially control the rows in each of the regions 70-72 in parallel (meaning that one or more lines of the first group 70 and one or more lines of the second group 71 and one or more lines of the third group 72 are driven simultaneously)) However, in an analogous field of endeavor Zhou provides the teachings for the limitations in claim 5 (see mapping above). Therefore, it would have been obvious for one of ordinary skill in the art to modify the driving circuitry of Cassidy to additionally extend to both column and rows as taught by Zhou. One of ordinary skill in the art would have been motivated to perform the modification for the advantage of/ benefit of reducing the frame period as taught by Zhou. (See Zhou’s abstract) Consider claim 15, where Cassidy in view of Sato in view of Zhou teaches the driving method according to claim 13, wherein the controlling all pixel sub-electrodes corresponding to each row of pixels in each first region group of the plurality of first region groups contained in the display region to be loaded with corresponding voltages simultaneously comprises: controlling, row by row, all the pixel sub-electrodes in the corresponding row of pixels in all the first region groups in the same one pixel row to be loaded with the corresponding voltages simultaneously until the voltages of the pixel sub-electrodes of the last row of pixels are loaded. (See Cassidy Fig. 6 and ¶91-100 where the data is loaded into the data lines while the row is being driven)(See Zhou’s abstract and page 8 lines 8-26 where the electrophoretic display is driven according to frame periods and controlled by drive lines 24 to control the row drivers 60-62 in order to sequentially control the rows in each of the regions 70-72 in parallel (meaning that one or more lines of the first group 70 and one or more lines of the second group 71 and one or more lines of the third group 72 are driven simultaneously)) Consider claim 17, where Cassidy in view of Sato teaches the display panel according to claim 2, however, they do not explicitly teach wherein in a case that the first region group comprises a plurality of regions arranged in the second direction, (See Zhou Fig. 4 and page 8 lines 8-26 where there are regions 70-72 driven by row drivers 60-62 respectively) the display region further internally comprises a plurality of third signal lines arranged in the second direction, and the third signal lines are electrically connected to the pixel sub-electrodes in the pixels arranged in the first direction; (See Zhou Fig. 4 and page 8 lines 8-26 where there are regions 70-72 driven by row drivers 60-62 through scan lines 41-43 connected to the pixels and arranged in the horizontal direction) the non-display region further comprises: a plurality of fourth signal lines corresponding to the first direction, and a plurality of second multiplexers, the second multiplexers correspond to second region groups, the second region group consist of a plurality of regions located at the same arrangement position in each first region group of the plurality of first region groups, the plurality of second multiplexers share the plurality of fourth signal lines, and output ends of the second multiplexers are connected to the third signal lines in the second region groups one to one; (See Zhou Fig. 4 and page 8 lines 8-26 where there are regions 70-72 located in the display area driven by row drivers 60-62 through scan lines 41-43 connected to the pixels and arranged in the horizontal direction) and the plurality of second multiplexers, under control of a second gating signal, transmit signals on the plurality of fourth signal lines into the corresponding second region groups in a time-sharing manner, (See Zhou’s abstract and page 8 lines 8-26 where the electrophoretic display is driven according to frame periods and controlled by drive lines 24 to control the row drivers 60-62) and in conjunction with the first gating signal corresponding to the plurality of first multiplexers, cause all the pixel sub-electrodes corresponding to each row of pixels in the first region groups to be simultaneously loaded with corresponding voltages, or cause all the pixel sub-electrodes corresponding to one scanning line in the display region to be simultaneously loaded with corresponding voltages. (See Zhou’s abstract and page 8 lines 8-26 where the electrophoretic display is driven according to frame periods and controlled by drive lines 24 to control the row drivers 60-62 in order to control the rows in each of the regions 70-72 in parallel (meaning that one or more lines of the first group 70 and one or more lines of the second group 71 and one or more lines of the third group 72 are driven simultaneously)) However, in an analogous field of endeavor Zhou provides the teachings for the limitations in claim 5 (see mapping above). Therefore, it would have been obvious for one of ordinary skill in the art to modify the driving circuitry of Cassidy to additionally extend to both column and rows as taught by Zhou. One of ordinary skill in the art would have been motivated to perform the modification for the advantage of/ benefit of reducing the frame period as taught by Zhou. (See Zhou’s abstract) Consider claim 19, where Cassidy in view of Sato teaches the display panel according to claim 2, wherein the non-display region further comprises: a scanning driving circuit and a data driving circuit; when the first signal lines are data lines, the second signal lines are connected between the data driving circuit and the corresponding first multiplexers; when the first signal lines are scanning lines, the second signal lines are connected between the scanning driving circuit and the corresponding first multiplexers; and in a case that the first region groups comprise the plurality of regions, when the first signal lines are one of the data lines or the scanning lines and the second signal lines are the other of the data lines or the scanning lines, the second signal lines are connected between one of the data driving circuit or the scanning driving circuit and the corresponding first multiplexers, and the fourth signal lines are connected between the other of the data driving circuit or the scanning driving circuit and the corresponding second multiplexers. (See Cassidy Fig. 4 and ¶65-68 where each multiplexer element 50 is associated with an individual column, thus a one-to-one mapping. The columns intersect with the row address signal in order to drive the pixels. Thus, the data can be loaded in the columns while being addressed using the row address signal line) Cassidy teaches the first multiplexers connected to the data driving circuit; however Cassidy does not explicitly teach the second signal lines are connected between one of the data driving circuit or the scanning driving circuit and the corresponding first multiplexers, and the fourth signal lines are connected between the other of the data driving circuit or the scanning driving circuit and the corresponding second multiplexers. However, in an analogous field of endeavor Zhou teaches the second signal lines are connected between one of the data driving circuit or the scanning driving circuit and the corresponding first multiplexers, and the fourth signal lines are connected between the other of the data driving circuit or the scanning driving circuit and the corresponding second multiplexers. (See Zhou’s abstract and page 8 lines 8-26 where the electrophoretic display is driven according to frame periods and controlled by drive lines 24 to control the row drivers 60-62) Therefore, it would have been obvious for one of ordinary skill in the art that the row address signal in Cassidy could be controlled using known row addressing methods in the art as taught by Zhou. One of ordinary skill in the art would have been motivated to perform the modification for the advantage of/ benefit of using known methods to yield predictable results. Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cassidy in view of Sato in view of Zhou as applied to claim 5 above, in further view of Iisaka. Consider claim 7, where Cassidy in view of Sato in view of Zhou teaches the display panel according to claim 6, wherein the second control electrodes of all the second thin film transistors in the second multiplexer are connected to one second control line, the fourth electrodes of all the second thin film transistors in the second multiplexer are connected to different third signal lines respectively, and the third electrodes of the second thin film transistors located at the same relative position in the corresponding second multiplexers of the plurality second multiplexers are connected to one fourth signal line; and the non-display region comprises the second control line. (See Iisaka fig. 2 and ¶45-47 where the control electrode of the transistors in the sampling circuit 150 are connected to a block selecting circuit 140 such that all of the TFT transistors in a block are selected. Each group of 6 transistors is connected to their respective image signal line 171. The Examiner notes that the claimed structure of the “first multiplexer” is exemplified in Applicant’s Fig. 7 and one of ordinary skill in the art would not necessarily interpret this circuit as a “multiplexer”) Therefore, it would have been obvious for one of ordinary skill in the art to modify the data line selection circuit of Cassidy with other known structures for selecting data lines as taught by Iisaka. One of ordinary skill in the art would have been motived to perform the modification for the advantage of/ benefit of substituting other known structures that perform a similar function to yield similar results. Claim(s) 18 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cassidy in view of Sato in view of Iisaka as applied to claim 3 above, in further view of Zhou Consider claim 18, where Cassidy in view of Sato in view of Iisaka teaches the display panel according to claim 3, however, they do not explicitly teach wherein in a case that the first region group comprises a plurality of regions arranged in the second direction, (See Zhou Fig. 4 and page 8 lines 8-26 where there are regions 70-72 driven by row drivers 60-62 respectively) the display region further internally comprises a plurality of third signal lines arranged in the second direction, and the third signal lines are electrically connected to the pixel sub-electrodes in the pixels arranged in the first direction; (See Zhou Fig. 4 and page 8 lines 8-26 where there are regions 70-72 driven by row drivers 60-62 through scan lines 41-43 connected to the pixels and arranged in the horizontal direction) the non-display region further comprises: a plurality of fourth signal lines corresponding to the first direction, and a plurality of second multiplexers, the second multiplexers correspond to second region groups, the second region group consist of a plurality of regions located at the same arrangement position in each first region group of the plurality of first region groups, the plurality of second multiplexers share the plurality of fourth signal lines, and output ends of the second multiplexers are connected to the third signal lines in the second region groups one to one; (See Zhou Fig. 4 and page 8 lines 8-26 where there are regions 70-72 located in the display area driven by row drivers 60-62 through scan lines 41-43 connected to the pixels and arranged in the horizontal direction) and the plurality of second multiplexers, under control of a second gating signal, transmit signals on the plurality of fourth signal lines into the corresponding second region groups in a time-sharing manner, (See Zhou’s abstract and page 8 lines 8-26 where the electrophoretic display is driven according to frame periods and controlled by drive lines 24 to control the row drivers 60-62) and in conjunction with the first gating signal corresponding to the plurality of first multiplexers, cause all the pixel sub-electrodes corresponding to each row of pixels in the first region groups to be simultaneously loaded with corresponding voltages, or cause all the pixel sub-electrodes corresponding to one scanning line in the display region to be simultaneously loaded with corresponding voltages. (See Zhou’s abstract and page 8 lines 8-26 where the electrophoretic display is driven according to frame periods and controlled by drive lines 24 to control the row drivers 60-62 in order to control the rows in each of the regions 70-72 in parallel (meaning that one or more lines of the first group 70 and one or more lines of the second group 71 and one or more lines of the third group 72 are driven simultaneously)) However, in an analogous field of endeavor Zhou provides the teachings for the limitations in claim 5 (see mapping above). Therefore, it would have been obvious for one of ordinary skill in the art to modify the driving circuitry of Cassidy to additionally extend to both column and rows as taught by Zhou. One of ordinary skill in the art would have been motivated to perform the modification for the advantage of/ benefit of reducing the frame period as taught by Zhou. (See Zhou’s abstract) Consider claim 20, where Cassidy in view of Sato in view of Iisaka teaches the display panel according to claim 3, wherein the non-display region further comprises: a scanning driving circuit and a data driving circuit; when the first signal lines are data lines, the second signal lines are connected between the data driving circuit and the corresponding first multiplexers; when the first signal lines are scanning lines, the second signal lines are connected between the scanning driving circuit and the corresponding first multiplexers; (See Cassidy Fig. 4 and ¶65-68 where each multiplexer element 50 is associated with an individual column, thus a one to one mapping. The columns intersect with the row address signal in order to drive the pixels. Thus, the data can be loaded in the columns while being addressed using the row address signal line) Cassidy teaches the first multiplexers connected to the data driving circuit; however Cassidy does not explicitly teach the second signal lines are connected between one of the data driving circuit or the scanning driving circuit and the corresponding first multiplexers, and the fourth signal lines are connected between the other of the data driving circuit or the scanning driving circuit and the corresponding second multiplexers. However, in an analogous field of endeavor Zhou teaches the second signal lines are connected between one of the data driving circuit or the scanning driving circuit and the corresponding first multiplexers, and the fourth signal lines are connected between the other of the data driving circuit or the scanning driving circuit and the corresponding second multiplexers. (See Zhou’s abstract and page 8 lines 8-26 where the electrophoretic display is driven according to frame periods and controlled by drive lines 24 to control the row drivers 60-62) Therefore, it would have been obvious for one of ordinary skill in the art that the row address signal in Cassidy could be controlled using known row addressing methods in the art as taught by Zhou. One of ordinary skill in the art would have been motivated to perform the modification for the advantage of/ benefit of using known methods to yield predictable results. Allowable Subject Matter Claims 14 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Claim 14 recites: 14. The driving method according to claim 13, wherein the controlling all pixel sub-electrodes corresponding to each row of pixels in each first region group of the plurality of first region groups contained in the display region to be loaded with corresponding voltages simultaneously comprises: loading, one by one, all the pixel sub-electrodes contained in each row of pixels in the first region groups corresponding to first multiplexers with corresponding voltages simultaneously until the voltages corresponding to all the pixel sub-electrodes corresponding to the last row of pixels in the corresponding first region groups are loaded; and loading the voltages of the pixel sub-electrodes corresponding to the next first region group after loading the voltages corresponding to all the pixel sub-electrodes in one first region group every time until the voltages corresponding to all the pixel sub-electrodes in the last first region group are loaded. While the teachings to modify the combination of Cassidy, Sato and Zhou may be found in Kim et al. (US2015/0309661) Figs 5, 6 and ¶98-102. The Examiner finds it non-obvious to combine the teachings as Kim is directed towards operation of a touch panel and it would potentially yield unexpected results combining the driving method over to an electrophoretic display. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM LU whose telephone number is (571)270-1809. The examiner can normally be reached 10am-6:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Eason can be reached at 571-270-7230. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. WILLIAM LU Primary Examiner Art Unit 2624 /WILLIAM LU/ Primary Examiner, Art Unit 2624
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Prosecution Timeline

Mar 27, 2024
Application Filed
Feb 17, 2026
Non-Final Rejection — §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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1-2
Expected OA Rounds
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Grant Probability
78%
With Interview (+6.5%)
2y 8m
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