Prosecution Insights
Last updated: May 29, 2026
Application No. 18/619,056

POWER CONVERSION SYSTEM AND CONTROL METHOD THEREOF

Final Rejection §103
Filed
Mar 27, 2024
Priority
Aug 23, 2023 — CN 202311063966.5
Examiner
ROSARIO BENITEZ, GUSTAVO A
Art Unit
2838
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
DELTA ELECTRONICS (SHANGHAI) CO., LTD.
OA Round
2 (Final)
82%
Grant Probability
Favorable
3-4
OA Rounds
5m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
606 granted / 744 resolved
+13.5% vs TC avg
Strong +25% interview lift
Without
With
+25.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
27 currently pending
Career history
774
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
83.8%
+43.8% vs TC avg
§102
4.3%
-35.7% vs TC avg
§112
11.0%
-29.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 744 resolved cases

Office Action

§103
DETAILED ACTION This office action is in response to the remarks filed on 04/04/2026. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Specification The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim Interpretation The following is a quotation of 35 U.S.C. 112(f): (f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph: An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked. As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph: (A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function; (B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and (C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function. Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function. Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function. Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. In re to claims 16-30, method claims 16-30 are rejected based on the following case law, note that under MPEP 2112.02, the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device inherently performs the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed Cir. 1986). Therefore the previous rejections based on the apparatus will not be repeated. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-4, 10, 12, 14, 16-19, 25, 27 and 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Alali US 2022/0200282 in view of Mohan US 5548165. Regarding Claims 1 and 16, Alali teaches (Figures 2-3 and 7) a power conversion system (Fig. 2), comprising a power conversion module (7), wherein the power conversion module comprises ,a damping circuit (9 and 11) and a first capacitor connected in series (at 10), and a controller (26 and 12), wherein the damping circuit comprises a first inductor (at 10), a first switch (13), a second switch (14), and a second capacitor (3), and the first switch and the second switch are connected in series to form a first bridge arm (8); the first inductor is connected between an intermediate node of the first bridge arm and the first capacitor (see fig. 3), and the second capacitor is connected in parallel to the first bridge arm (see fig. 2), the controller comprises: a capacitor voltage control unit (26, 60 and 62, Fig. 7), obtaining a first reference value (from 62) according to an input voltage of the power conversion module (Vs, 26), a voltage of the second capacitor (Vdc), and a voltage reference value of the second capacitor (Vdcref); a damping current generation unit (25a), obtaining a second reference value (determined by 25) according to the input voltage of the power conversion module (Vs) and a current signal (IL) related to an input current of the power conversion module; and an inductor current control unit (18-24), outputting a driving signal (from 18) according to a current flowing through the first inductor (Iinj) and a current reference value (Iref) of the first inductor to control the first switch and the second switch (13-14), in order to stabilize the input voltage (with active compensation) of the power conversion module (Vs), wherein the current reference value of the first inductor is obtained according to the first reference value and the second reference value (from 25a producing Iref). (For Example: Par. 196-232) Alali does not teach a first current reference value, a second current reference value, wherein the current reference value of the first inductor is obtained according to the first current reference value and the second current reference value. Mohan teaches (Figures 1-3) a first current reference value (96), a second current reference value (98), wherein the current reference value (92) of the first inductor is obtained according to the first current reference value and the second current reference value (adder, Fig. 3). (For Example: Col. 5) It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Alali to include a first current reference value, a second current reference value, wherein the current reference value of the first inductor is obtained according to the first current reference value and the second current reference value, as taught by Mohan to draw a current substantially in phase with the voltage across it in order to provide damping. Regarding Claims 2 and 17, Alali teaches (Figures 2-3 and 7) wherein the capacitor voltage control unit comprises a phase-locked loop (at 26), and the phase-locked loop are used to track at least part of AC harmonic components of the input voltage (Vs) of the power conversion module (par. 196), and obtaining the first reference value according to the at least part of the AC harmonic components, the voltage of the second capacitor (Vdc) and the voltage reference value of the second capacitor (Vdcref). (For Example: Par. 196-232) Alali does not teach a first current reference value, a second current reference value; and a first filter. Mohan teaches (Figures 1-3) a first current reference value (96), a second current reference value (98), wherein the current reference value (92); and a first filter (102). (For Example: Col. 5) It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Alali to include a first current reference value, a second current reference value; and a first filter, as taught by Mohan to draw a current substantially in phase with the voltage across it in order to provide damping. Regarding Claims 3 and 18, Alali teaches (Figures 2-3 and 7), wherein the capacitor voltage control unit (26, 60-62) further comprises a first subtracter (60), a first regulator (62), and the first subtractor performs a subtraction operation on the voltage of the second capacitor (Vdc) and the voltage reference value of the second capacitor (Vdcref) to output a first error signal which is regulated by the first regulator (62). multiplied by a per-unit value of the at least part of AC harmonic components by the first multiplier to obtain the first current reference value. Alali does not teach a first multiplier; multiplying by a per-unit value of the at least part of AC harmonic components by the first multiplier to obtain the first current reference value. Mohan teaches (Figures 1-3) a first multiplier (113); multiplying by a per-unit value of the at least part of AC harmonic components (Col. 3 lines 23-40) by the first multiplier to obtain the first current reference value (Col. 5 lines 15-45). (For Example: Col. 5) It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Alali to include a first current reference value, a second current reference value; and a first filter, as taught by Mohan to draw a current substantially in phase with the voltage across it in order to provide damping. Regarding Claims 4 and 19, Alali teaches (Figures 2-3 and 7) wherein the power conversion system (fig. 2) further comprises a three-phase rectification circuit (par. 64 and claim 12), and an input port of the power conversion module (at 7) is connected to an output port of the three-phase rectification circuit (connected to 1); an input port of the three-phase rectification circuit is connected to a three-phase AC power source (1), and the at least part of AC harmonic components tracked by the phase-locked loop (196) comprise a harmonic component of the output voltage of the three-phase rectification circuit (par. 64 and claim 12). (For Example: Par. 196-232) Alali does not teach a 12th harmonic component. Mohan teaches (Figures 1-3) a 12th harmonic component (Col. 4 lines 5-30). It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Alali to include a 12th harmonic component, as taught by Mohan to draw a current substantially in phase with the voltage across it in order to provide damping. Regarding Claims 10 and 25, Alali teaches (Figures 2-3 and 7) wherein the power conversion module (7) further comprises a second adder (63), and the current reference value of the first inductor (iref) is obtained by adding the first reference value and the second reference value through the second adder (see fig. 7). (For Example: Par. 196-232) Alali does not teach a first current reference value, a second current reference value. Mohan teaches (Figures 1-3) a first current reference value (96), a second current reference value (98), wherein the current reference value (92). (For Example: Col. 5) It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Alali to include a first current reference value, a second current reference value, as taught by Mohan to draw a current substantially in phase with the voltage across it in order to provide damping. Regarding Claims 12 and 27, Alali teaches (Figures 2-3 and 7) the system. Alali does not teach wherein the damping circuit is equivalent to a resistor after being regulated by the capacitor voltage control unit, the damping current generation unit, and the inductor current control unit. Mohan teaches (Figures 1-3) wherein the damping circuit (with 24) is equivalent to a resistor (Col. 6 lines 15-40) after being regulated by the capacitor voltage control unit (at 112), the damping current generation unit (at 51), and the inductor current control unit (at 92 and 121). (For Example: Col. 5) It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Alali to include wherein the damping circuit is equivalent to a resistor after being regulated by the capacitor voltage control unit, the damping current generation unit, and the inductor current control unit. as taught by Mohan to draw a current substantially in phase with the voltage across it in order to provide damping. Regarding Claims 14 and 29, Alali teaches (Figures 2-3 and 7) a load conversion circuit (at 2), wherein the input port of the power conversion module (at 7) is connected in parallel to the input port of the load conversion circuit (Fig. 2), and the current signal related to the input current of the power conversion module is the input current of the load conversion circuit (IL) or the output current of the load conversion circuit. (For Example: Par. 196-232) Claim(s) 5 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Alali US 2022/0200282 in view of Mohan US 5548165 and further in view of Chang US 2010/0302818. Regarding Claims 5 and 20, Alali teaches (Figures 2-3 and 7) the power conversion system. Alali does not teach a single-phase rectification circuit, and an input port of the single-phase rectification circuit is connected to a single-phase AC power source; an input port of the power conversion module is connected to an output port of the single-phase rectification circuit, and the at least part of AC harmonic components tracked by the phase-locked loop comprise a second harmonic component, and/or 4th harmonic component, and/or 6th harmonic component of the output voltage of the single-phase rectification circuit. Chang teaches (Figures 3) a single-phase rectification circuit (Fig, 3, 22), and an input port of the single-phase rectification circuit is connected to a single-phase AC power source (26); an input port of the power conversion module (boost converter) is connected to an output port of the single-phase rectification circuit (22), and the at least part of AC harmonic components tracked by the phase-locked loop comprise a second harmonic component (par. 8), and/or 4th harmonic component, and/or 6th harmonic component of the output voltage of the single-phase rectification circuit. (For Example: Par. 6-8) It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Alali to include a single-phase rectification circuit, and an input port of the single-phase rectification circuit is connected to a single-phase AC power source; an input port of the power conversion module is connected to an output port of the single-phase rectification circuit, and the at least part of AC harmonic components tracked by the phase-locked loop comprise a second harmonic component, and/or 4th harmonic component, and/or 6th harmonic component of the output voltage of the single-phase rectification circuit, as taught by Chang for improvement of the power factor and input current harmonics. Claim(s) 9 and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Alali US 2022/0200282 in view of Mohan US 5548165 and further in view of Chapman US 20120087159. Regarding Claims 9 and 24, Alali teaches (Figures 2-3 and 7) wherein the inductor current control unit (18-24) comprises a second subtractor (24), a second regulator (23), and; the second subtractor (24) performs a subtraction operation on the current flowing through the first inductor and the current reference value of the first inductor to output a second error signal (U) and the second error signal is regulated by the second regulator (23). (For Example: Par. 196-232) Alali does not teach a first adder; and added to a duty cycle feedforward value by the first adder to obtain the driving signal. Chapman teaches (Figure 10b) a first adder (at 236); and added to a duty cycle feedforward value (from 337) by the first adder to obtain the driving signal (d). (For Example: Par. 86 and 98) It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Alali to include a first adder; and added to a duty cycle feedforward value by the first adder to obtain the driving signal, as taught by Chapman for ripple attenuation and to adaptively alter the calculation to improve the effectiveness. Claim(s) 11 and 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Alali US 2022/0200282 in view of Mohan US 5548165 and further in view of Li US2019/0229609. Regarding Claims 11 and 26, Alali teaches (Figures 2-3 and 7) the system. Alali does not teach a rectification circuit and a load conversion circuit, and the input port of the power conversion module is connected in parallel to the output port of the rectification circuit and the input port of the load conversion circuit; the sum of the input current of the power conversion module and the output current of the rectification circuit is the input current of the load conversion circuit, and the load conversion circuit is a DC-AC conversion circuit or a DC-DC conversion circuit. Li teaches (Figures 1-5) a rectification circuit (10) and a load conversion circuit (ACDC or DC/DC converter), and the input port of the power conversion module is connected in parallel to the output port of the rectification circuit (10) and the input port of the load conversion circuit (Fig. 1 and 5a); the sum of the input current of the power conversion module and the output current of the rectification circuit is the input current of the load conversion circuit (see fig. 5a), and the load conversion circuit is a DC-AC conversion circuit or a DC-DC conversion circuit (Fig. 1). (For Example: Par. 55) It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Alali to include a rectification circuit and a load conversion circuit, and the input port of the power conversion module is connected in parallel to the output port of the rectification circuit and the input port of the load conversion circuit; the sum of the input current of the power conversion module and the output current of the rectification circuit is the input current of the load conversion circuit, and the load conversion circuit is a DC-AC conversion circuit or a DC-DC conversion circuit, as taught by Li to actively removes undesired DC-link ripple. Allowable Subject Matter Claims 6-8, 13, 15, 21-23, 28 and 30 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Reasons for Indicating Allowable Subject Matter The following is an examiner’s statement of reasons for indicating Allowable Subject Matter: Claims 6 and 21; prior art of record fails to disclose either by itself or in combination: “…wherein: the damping current generation unit comprises a second filter and a second multiplier; the second filter performs high pass filtering on the input voltage of the power conversion module to obtain a first voltage value, and the second multiplier performs a multiplication operation on the first voltage value and a first admittance parameter to obtain the second current reference value; or the damping current generation unit comprises a second filter and a first divider; the second filter performs high pass filtering on the input voltage of the power conversion module to obtain a first voltage value, and the first divider performs a division operation on the first voltage value and a first resistance parameter to obtain the second current reference value.” Claims 13 and 28; prior art of record fails to disclose either by itself or in combination: “…wherein the power conversion system further comprises an AC power source, an input inductor, a rectification circuit, and a bus capacitor, and the input inductor is connected between the AC power source and the input port of the rectification circuit; the bus capacitor and the power conversion module are sequentially connected in parallel to the output port of the rectification circuit, and the step of obtaining a second current reference value according to the input voltage of the power conversion module and the current signal related to the input current of the power conversion module comprises: obtaining a ripple component of the input voltage of the power conversion module; obtaining a resistance parameter based on the input voltage of the power conversion module and the current signal related to the input current of the power conversion module; obtaining the second current reference value based on a first coefficient, the resistance parameter and the ripple component of the input voltage, wherein the first coefficient is adaptively adjusted according to the input inductance.” These features taken alone or in combination are neither disclosed nor suggested by the prior art of record. Response to Arguments Applicant's arguments filed 04/09/2026 have been fully considered but they are not persuasive. Applicant argued that “Further, in this application, the first capacitor 13b and the damping circuit 13a are connected in series, the purpose is to block DC or low-frequency voltages, thereby reducing the voltage component applied to the damping circuit 13a, and thus reducing the power consumption of the circuit behind the damping circuit 13a. However, Aliali's capacitor 17 is connected in parallel in the circuit, together with inductor 15 and 16, to form a high-frequency filter”. However, the examiner is entitle to the broadest reasonable interpretation. In this case, see the drawing below the same current Iinj the passed from the circuit 9 passed through circuit 10 so that said current Iinj can be supplied to the 3 phase lines. Since both circuits have the same current passing through them the connection can be considered as a series connection. PNG media_image1.png 286 304 media_image1.png Greyscale PNG media_image2.png 442 176 media_image2.png Greyscale Applicant argued that “This technical feature is different from the "a damping current generation unit, obtaining a second current reference value according to the input voltage of the power conversion module and a current signal related to an input current of the power conversion module”. However, claim 1 above requires that the second reference current value be according to the input voltage, Vs in Alali and a current signal related to an input current, IL in Alali see fig. 7 and the circuit 25 generates different reference currents based on at least the VS and IL signals. The technical features as to how to generate the reference current are not disclosed in the claim. Applicant argued that “Further, Alali's technical solution requires the identification and control of the injected current. However, this application does not need to detect or monitor the injected current. Alali also needs to calculate multiple instantaneous disturbance…”. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., this application does not need to detect or monitor the injected current) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO A ROSARIO-BENITEZ whose telephone number is (571)270-7888. The examiner can normally be reached M-F 9AM-5PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MONICA LEWIS can be reached at 5712721838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /GUSTAVO A ROSARIO-BENITEZ/Primary Examiner, Art Unit 2838
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Prosecution Timeline

Mar 27, 2024
Application Filed
Jan 15, 2026
Non-Final Rejection mailed — §103
Apr 09, 2026
Response Filed
May 15, 2026
Final Rejection mailed — §103 (current)

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