DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the filling of the Amendment on 03/09/2026.
Claim Objections
Claim 9 is objected to because of the following informalities: Claim 9, line 12 recites “a control signal”, which should be --the control signal-- because this term was previously presented in the claim.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 and 9-15 are rejected under 35 U.S.C. 103 as being unpatentable over La Pila et al. (US 2024/0006996), hereinafter La Pila, in view of Tang et al. (US 2015/0303799), hereinafter Tang.
Regarding claim 1, La Pila discloses (see figures 1-20) a power stage (figure 13, part 402) of a switching converter (figure 13) comprising: a high-side switch (figure 13, part 404) and a low-side switch (figure 13, part 414) to respectively drive an inductor (figure 13, part 430) in a first interval (figure 13, part 404/414; first interval) and a second interval (figure 13, part 404/414; second interval) periodically based on a control signal (figure 13, part PWM control signal used to generates 410/420) (paragraph [110]; pulse width modulated (PWM) signal), wherein said inductor (figure 13, part 430) is coupled to a junction of said high-side switch (figure 13, part 404) and said low-side switch (figure 13, part 414); wherein said control signal is in a first logic state (figures 13, 14 and 16, part PWM control signal at first logic state [at Ton] used to generates 410/420) to turn on said high-side switch (figures 13, 14 and 16, part 404; turn-on [at Ton]) and turn off said low-side switch (figures 13, 14 and 16, part 414; turn-off [at Ton]) and in a second logic state (figures 13, 14 and 16, part PWM control signal at second logic state [at Toff] used to generates 410/420) to turn off said high-side switch (figures 13, 14 and 16, part 404; turn-off [at Toff]) and turn on said low-side switch (figures 13, 14 and 16, part 414; turn-on [at Toff]) (paragraph [0126]), wherein said control signal is repeatedly switched between said first logic state (figures 13 and 14, part PWM control signal at first logic state [at Ton] used to generates 410/420) and said second logic state (figures 13 and 14, part PWM control signal at second logic state [at Toff] used to generates 410/420) with a period (figure 14, part period) to cause said power stage (figure 13, part 402) to contribute to said requisite load current in a first duration (figure 13, part requisite load current at Load), wherein said control signal is in another state (figures 13 and 16, part PWM control signal at another state [at High-Z] used to generates 410/420) to turn off both of said high-side switch (figures 13 and 16, part 404; turn-off [at High-Z]) and said low-side switch (figures 13 and 16, part 414; turn-off [at High-Z]) to place said power stage (figure 13, part 402) in an inactive state (figure 13, part 402; inactive state) in which said power stage does not to contribute to requisite load current in a second duration (figure 13, part not contribution to requisite load current at Load at High-Z) (paragraph [0126]; the high-impedance (High-Z) state of controlling switching (where both of the transistors 404 and 414 are turned off and a high impedance condition exists at the switching node 406) introduces a contribution to the average coil current in which the coil current is zero); a current-sense block (figures 13 and 17, part 440) to generate on an output node of said power stage (figure 17, part output node at right side of 480), information (figure 17, part information in output node at right side of 480) representing a magnitude of inductor-current flowing through said inductor (figure 13, part inductor-current flowing at 430) (paragraphs [0127]-[0137]; the voltage of the output signal Vsense is directly proportional to the output current IOUT flowing in the inductor); and a switch (figure 17, part M25) coupled between said output node (figure 17, part output node at right side of 480) and an output pin of said power stage (figure 17, part output pin at 456), wherein, when said power stage is inactive (figure 13, part 402 inactive at high-impedance [High -Z]; when 404 and 414 are turned off) (paragraph [0126]; The reason for this is that the high-impedance (High-Z) state of controlling switching (where both of the transistors 404 and 414 are turned off and a high impedance condition exists at the switching node 406) introduces a contribution to the average coil current in which the coil current is zero): a portion of said current-sense block (figures 13 and 17, part 440) driving said output node (figure 17, part output node at right side of 480) is maintained in a powered-ON state (figure 17, part portion 442 is maintained in a powered-ON state); and said switch (figure 17, part M25) is operated to be open (figure 17, part M25; open) to disconnect said output node (figure 17, part output node at right side of 480) from said output pin (figure 17, part output pin at 456) in said entire second duration (figure 13, part not contribution to requisite load current at Load at High-Z) (paragraphs [0127]-[0140]; The circuitry formed by the second and third switching transistors M25, M26 functions as a masking circuit that masks (or blocks) the contribution of the signal at node 470 during the high impedance (High-Z) state. During the high impedance (High-Z) state, the switching transistor M25 is deactuated (blocking the signal at node 470 from passing to node 472) and the switching transistor M26 is actuated (connecting node 472 to ground). Conversely, when not in the high impedance (High-Z) state, the switching transistor M25 is actuated (passing the signal at node 470 to node 472 to be filtered by resistor 474 and capacitor 476) and the switching transistor M26 is deactuated (disconnecting node 472 from ground)).
La Pila does not expressly disclose a plurality of power stages contained in a multi-phase switching converter, wherein only select ones of said plurality of power stages are placed in an active state to together generate a requisite load current and any remaining ones of said plurality of power stages are placed in an inactive state to not contribute to said requisite load current; wherein said control signal is in another state to turn off both of said high-side switch and said low-side switch to place said power stage in an inactive state in which said power stage does not to contribute to requisite load current in a second duration, wherein said second duration spans multiple successive ones of said period; said entire second duration spanning said multiple successive ones of said period in said inactive state.
Tang teaches (see figures 1-5) a power stage (figure 1, part 102) of a plurality of power stages (figure 1, part plurality of 102) contained in a multi-phase switching converter (figure 1, part 100), wherein only select ones of said plurality of power stages are placed in an active state (figure 1, part select ones of said plurality of power stages 102 placed in active state to meet with the requisite load current at 106) to together generate a requisite load current (figure 1, part requisite load current at 106) and any remaining ones of said plurality of power stages are placed in an inactive state (figure 1, part remaining ones of said plurality of power stages 102 placed in inactive state to not contribute to said requisite load current at 106) to not contribute to said requisite load current (figure 1, part requisite load current at 106), said power stage (figures 1 and 5, part 102) (paragraphs [0002]-[0003]; Multiple phases (power stages) can be connected in parallel to the load through respective inductors to meet high output current requirements… Light load conditions result in periods where the power stage has little or no activity. Multiphase converters typically have the ability to drop phases, where one or more phases are not actively switching and not supporting any of the additional current. In addition, for extremely light load currents, phases may be operating in pulse frequency mode, where a substantial amount of time passes between switch cycles in which the power stage is not switching. Thus, DC-DC voltage regulators have multiple operating modes where having one or more power stages in sleep mode is desirable to reduce power loss) comprising: a high-side switch (figure 5, part HS FET) and a low-side switch (figure 5, part LS FET) to respectively drive an inductor (figures 1 and 5, part L) in a first interval (figure 4, part first interval) and a second interval periodically (figure 4, part second interval) based on a control signal (figures 1, 4 and 5, part PWM), wherein said inductor (figures 1 and 5, part L) is coupled to a junction of said high-side switch (figure 5, part HS FET) and said low-side switch (figure 5, part LS FET); wherein said control signal (figures 1, 4 and 5, part PWM) is in a first logic state (figures 1, 4 and 5, part PWM; first logic state at on time) to turn on said high-side switch (figures 4 and 5, part HS FET; turn on at on time) and turn off said low-side switch (figures 4 and 5, part LS FET; turn-off at on time) and in a second logic state (figures 1, 4 and 5, part PWM; second logic state at off time) to turn off said high-side switch (figures 4 and 5, part HS FET; turn off at off time) and turn on said low-side switch (figures 4 and 5, part LS FET; turn-on at off time), wherein said control signal (figures 1, 4 and 5, part PWM) is repeatedly switched between said first logic state (figures 1, 4 and 5, part PWM; first logic state at on time) and said second logic state (figures 1, 4 and 5, part PWM; second logic state at off time) with a period to cause said power stage (figures 1 and 5, part 102; period where the power stage 102 is in active state to contribute to said requisite load current at 106) to contribute to said requisite load current in a first duration (figures 1 and 5, part 102; period where the power stage 102 is in active state to contribute to said requisite load current at 106 in first duration), wherein said control signal is in another state (figures 1, 4 and 5, part PWM; another state at HiZ) to turn off both of said high-side switch (figures 4 and 5, part HS FET; turn off at Hiz) and said low-side switch (figures 4 and 5, part LS FET; turn-off at HiZ) to place said power stage in an inactive state (figures 1 and 5, part 102; at inactive state) in which said power stage does not to contribute (figures 1 and 5, part 102; inactive state because does not contribute to said requisite load current at 106) to requisite load current in a second duration (figures 1 and 5, part 102; inactive state because does not contribute to said requisite load current at 106 in second duration), wherein said second duration spans multiple successive ones of said period (figures 1 and 5, part 102; inactive state because does not contribute to said requisite load current at 106 in second duration; where this second duration spans multiple successive ones of said period depending on the time at sleep mode [where is no needed the power contribution of this phase]) (paragraphs [0017]-[0022]; the switching state of the power stage 102 is determined by PWM control. The power stage 102 connects the load 106 to an input voltage of the voltage regulator 100 in a first switching state when the PWM control signal provided to the power stage 102 is active (on) and to ground in a second switching state when the PWM control signal is not active (off) as shown in FIG. 4. The power stage 102 operates in the nominal power mode in either PWM switching state (i.e. PWM on or off). To force the power stage 102 into the sleep mode, the controller 104 deactivates the PWM control signal to indicate a HiZ state in which the power stage 102 does not switch i.e. the high-side and low-side switches of the power stage 102 are off. If the power management unit 112 of the power stage 102 detects the PWM control signal is in the HiZ non-switching state for a predetermined period of time, the power stage 102 moves from the nominal power mode to the sleep (low power) mode (Block 300). The controller 102 includes control logic 114 that keeps the PWM control signal asserted in the HiZ state for a sufficient period of time to force the power stage 102 into the sleep mode); a current-sense block (figure 5, part 216) to generate on an output node of said power stage (figure 5, part output node of 216), information (figure 5, part imon) representing a magnitude of inductor-current flowing through said inductor (figures 1 and 5, part inductor-current flowing through L) (paragraph [0024]-[0033]; the power stage 102 can include a current monitor 216 for measuring or sensing the output current of the power stage 102 through the inductor (L)… the power management unit 112 can disable the current monitor 216 and/or the temperature sensor 218 in both the sleep and deep sleep modes because the power stage output current is zero and the power stage temperature is non-critical when the power stage 102 is idle/not switching); and said entire second duration spanning said multiple successive ones of said period in said inactive state (figures 1 and 5, part 102; inactive state because does not contribute to said requisite load current at 106 in second duration; where this second duration spans multiple successive ones of said period depending on the time at sleep mode [where is no needed the power contribution of this phase]).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to apply the switching converter features of La Pila to the multi-phase switching converter as taught Tang and obtain a power stage of a plurality of power stages contained in a multi-phase switching converter, wherein only select ones of said plurality of power stages are placed in an active state to together generate a requisite load current and any remaining ones of said plurality of power stages are placed in an inactive state to not contribute to said requisite load current, said power stage comprising: a high-side switch and a low-side switch to respectively drive an inductor in a first interval and a second interval periodically based on a control signal, wherein said inductor is coupled to a junction of said high-side switch and said low-side switch, wherein said control signal is in a first logic state to turn on said high-side switch and turn off said low-side switch and in a second logic state to turn off said high-side switch and turn on said low-side switch, wherein said control signal is repeatedly switched between said first logic state and said second logic state with a period to cause said power stage to contribute to said requisite load current in a first duration, wherein said control signal is in another state to turn off both of said high-side switch and said low-side switch to place said power stage in an inactive state in which said power stage does not to contribute to requisite load current in a second duration, wherein said second duration spans multiple successive ones of said period; a current-sense block to generate on an output node of said power stage, information representing a magnitude of inductor-current flowing through said inductor; and a switch coupled between said output node and an output pin of said power stage, wherein, when said power stage is inactive: a portion of said current-sense block driving said output node is maintained in a powered-ON state; and said switch is operated to be open to disconnect said output node from said output pin in said entire second duration spanning said multiple successive ones of said period in said inactive state, because the combination result in more efficient and accurate power conversion in a multi-phase system with more accurate control and power dissipation reduction (paragraph [0015]).
Regarding claim 2, La Pila and Tang teaches everything claimed as applied above (see claim 1). Further, La Pila discloses (see figures 1-20) said portion (figure 17, part portion 442 is maintained in a powered-ON state) of said current-sense block (figure 17, part 440) is an amplifier (figure 17, part 442).
Regarding claim 3, La Pila and Tang teaches everything claimed as applied above (see claim 2). Further, La Pila discloses (see figures 1-20) said information (figure 17, part information in output node at right side of 480) is a current (figure 17, part current in output node at right side of 480), wherein said amplifier (figure 17, part 442) has a non-zero output offset voltage (figure 17, part 442) that causes said current to be non-zero (figure 17, part current in output node at right side of 480) in said second duration (figures 13 and 16, part at High-Z) even when input of said amplifier is set to zero volts (figure 17, part input of 442) when said power stage is inactive (figures 13 and 16, part 402 inactive at high-impedance [High -Z]; when 404 and 414 are turned off).
Regarding claim 4, La Pila and Tang teaches everything claimed as applied above (see claim 3). Further, La Pila discloses (see figures 1-20) said switch is closed (figure 17, part M25; closed at active state [non-high-impedance state]) when said power stage is active (figure 13, part 402; at active state), wherein said high-side switch (figure 13, part 404) and said low-side switch (figure 13, part 414) respectively drive said inductor (figure 13, part 430) in said first interval (figure 13, part 404/414; first interval) and said second interval (figure 13, part 404/414; second interval) only when said power stage is active (figure 13, part 402; at active state) (paragraphs [0129]; The circuitry formed by the second and third switching transistors M25, M26 functions as a masking circuit that masks (or blocks) the contribution of the signal at node 470 during the high impedance (High-Z) state. During the high impedance (High-Z) state, the switching transistor M25 is deactuated (blocking the signal at node 470 from passing to node 472) and the switching transistor M26 is actuated (connecting node 472 to ground). Conversely, when not in the high impedance (High-Z) state, the switching transistor M25 is actuated (passing the signal at node 470 to node 472 to be filtered by resistor 474 and capacitor 476) and the switching transistor M26 is deactuated (disconnecting node 472 from ground)).
Regarding claim 5, La Pila and Tang teaches everything claimed as applied above (see claim 4). Further, La Pila discloses (see figures 1-20) said control signal (figure 13, part 410/420) indicates whether said power stage is to be active (figure 13, part 402; at active state) or inactive (figure 13, part 402 inactive at high-impedance [High -Z]; when 404 and 414 are turned off).
Regarding claim 6, La Pila and Tang teaches everything claimed as applied above (see claim 5). Further, La Pila discloses (see figures 1-20) said another state of said control signal (figures 13 and 16, part PWM control signal at another state [at High-Z] used to generates 410/420) is a high-impedance (Hi-Z) state (figure 16, part High-Z) of said control signal (figure 13, part PWM control signal used to generates 410/420) indicating that said power stage is to be inactive (figures 13 and 16, part 402 inactive at high-impedance [High -Z]; when 404 and 414 are turned off) (paragraph [0126]; The reason for this is that the high-impedance (High-Z) state of controlling switching (where both of the transistors 404 and 414 are turned off and a high impedance condition exists at the switching node 406) introduces a contribution to the average coil current in which the coil current is zero).
Regarding claim 7, La Pila and Tang teaches everything claimed as applied above (see claim 6). Further, La Pila discloses (see figures 1-20) a gate driver (figure 13, part gate driver generated by 408/418), said gate driver (figure 13, part gate driver generated by 408/418) to generate corresponding signals to operate said high-side switch (figure 13, part 404) and said low-side switch (figure 13, part 414) to be correspondingly open or closed (figure 13, part 404/414; open or closed), wherein if a state of said control signal is said high-impedance (Hi-Z) state (figure 13, part 410/420; both turn-off at high impedance (High-Z) state), said gate driver (figure 13, part gate driver generated by 408/418) generates an output signal with a value (figures 13 and 17, part gate driver generated by 408/418 generates 410/420 to enter in Control) to cause said switch to be open (figure 17, part M25; open) (paragraphs [0127]-[0140]; The circuitry formed by the second and third switching transistors M25, M26 functions as a masking circuit that masks (or blocks) the contribution of the signal at node 470 during the high impedance (High-Z) state. During the high impedance (High-Z) state, the switching transistor M25 is deactuated (blocking the signal at node 470 from passing to node 472) and the switching transistor M26 is actuated (connecting node 472 to ground). Conversely, when not in the high impedance (High-Z) state, the switching transistor M25 is actuated (passing the signal at node 470 to node 472 to be filtered by resistor 474 and capacitor 476) and the switching transistor M26 is deactuated (disconnecting node 472 from ground)). However, La Pila does not expressly disclose a gate driver to receive said control signal, said gate driver to generate based on a logic level of said control signal corresponding signals to operate said high-side switch and said low-side switch to be correspondingly open or closed.
Tang teaches (see figures 1-5) a gate driver (figure 5, part gate driver generated by 202-212) to receive said control signal (figure 5, part pwm), said gate driver (figure 5, part gate driver generated by 202-212) to generate based on a logic level of said control signal (figure 5, part logic of pwm) corresponding signals to operate said high-side switch (figure 5, part HS FET) and said low-side switch (figure 5, part LS FET) to be correspondingly open or closed (figure 5, part HS/LS FET; open and closed).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to apply the switching converter features of La Pila to the multi-phase switching converter as taught Tang and obtain a gate driver to receive said control signal, said gate driver to generate based on a logic level of said control signal corresponding signals to operate said high-side switch and said low-side switch to be correspondingly open or closed, wherein if a state of said control signal is said high-impedance (Hi-Z) state, said gate driver generates an output signal with a value to cause said switch to be open, because the combination result in more efficient and accurate power conversion in a multi-phase system with more accurate control and power dissipation reduction (paragraph [0015]).
Regarding claim 9, La Pila discloses (see figures 1-20) a switching converter (figure 13) comprising: a power stage (figure 13, part 402) for generating a regulated supply voltage on a power rail (figure 13, part supply voltage at output to Load), wherein the power stage comprises: a high-side switch (figure 13, part 404) and a low-side switch (figure 13, part 414) to respectively drive an inductor (figure 13, part 430) in a first interval (figure 13, part 404/414; first interval) and a second interval (figure 13, part 404/414; second interval) periodically based on a control signal (figure 13, part 410/420) (paragraph [110]), wherein said inductor (figure 13, part 430) is coupled to a junction of said high-side switch (figure 13, part 404) and said low-side switch (figure 13, part 414); wherein said control signal is in a first logic state (figures 13, 14 and 16, part PWM control signal at first logic state [at Ton] used to generates 410/420) to turn on said high-side switch (figures 13, 14 and 16, part 404; turn-on [at Ton]) and turn off said low-side switch (figures 13, 14 and 16, part 414; turn-off [at Ton]) and in a second logic state (figures 13, 14 and 16, part PWM control signal at second logic state [at Toff] used to generates 410/420) to turn off said high-side switch (figures 13, 14 and 16, part 404; turn-off [at Toff]) and turn on said low-side switch (figures 13, 14 and 16, part 414; turn-on [at Toff]) (paragraph [0126]), wherein said control signal is repeatedly switched between said first logic state (figures 13 and 14, part PWM control signal at first logic state [at Ton] used to generates 410/420) and said second logic state (figures 13 and 14, part PWM control signal at second logic state [at Toff] used to generates 410/420) with a period (figure 14, part period) to cause said power stage (figure 13, part 402) to contribute to said requisite load current in a first duration (figure 13, part requisite load current at Load), wherein said control signal is in another state (figures 13 and 16, part PWM control signal at another state [at High-Z] used to generates 410/420) to turn off both of said high-side switch (figures 13 and 16, part 404; turn-off [at High-Z]) and said low-side switch (figures 13 and 16, part 414; turn-off [at High-Z]) to place said power stage (figure 13, part 402) in an inactive state (figure 13, part 402; inactive state) in which said power stage does not to contribute to requisite load current in a second duration (figure 13, part not contribution to requisite load current at Load at High-Z) (paragraph [0126]; the high-impedance (High-Z) state of controlling switching (where both of the transistors 404 and 414 are turned off and a high impedance condition exists at the switching node 406) introduces a contribution to the average coil current in which the coil current is zero); a current-sense block (figures 13 and 17, part 440) to generate on an output node of said power stage (figure 17, part output node at right side of 480), information (figure 17, part information in output node at right side of 480) representing a magnitude of inductor-current flowing through said inductor (figure 13, part inductor-current flowing at 430) (paragraphs [0127]-[0137]; the voltage of the output signal Vsense is directly proportional to the output current IOUT flowing in the inductor); and a switch (figure 13, part M25) coupled between said output node (figure 17, part output node at right side of 480) and an output pin of said power stage (figure 17, part output pin at 456), wherein, when said power stage is inactive (figure 13, part power stage inactive at high-impedance [High -Z]; when 404 and 414 are turned off) (paragraph [0126]; The reason for this is that the high-impedance (High-Z) state of controlling switching (where both of the transistors 404 and 414 are turned off and a high impedance condition exists at the switching node 406) introduces a contribution to the average coil current in which the coil current is zero): a portion of said current-sense block (figures 13 and 17, part 440) driving said output node (figure 17, part output node at right side of 480) is maintained in a powered-ON state (figure 17, part portion 442 is maintained in a powered-ON state); and said switch (figure 17, part M25) is operated to be open (figure 17, part M25; open) to disconnect said output node (figure 17, part output node at right side of 480) from said output pin in said entire second duration (figure 13, part not contribution to requisite load current at Load at High-Z) (figure 17, part output pin at 456) (paragraphs [0127]-[0140]; The circuitry formed by the second and third switching transistors M25, M26 functions as a masking circuit that masks (or blocks) the contribution of the signal at node 470 during the high impedance (High-Z) state. During the high impedance (High-Z) state, the switching transistor M25 is deactuated (blocking the signal at node 470 from passing to node 472) and the switching transistor M26 is actuated (connecting node 472 to ground). Conversely, when not in the high impedance (High-Z) state, the switching transistor M25 is actuated (passing the signal at node 470 to node 472 to be filtered by resistor 474 and capacitor 476) and the switching transistor M26 is deactuated (disconnecting node 472 from ground)).
La Pila does not expressly disclose a multi-phase switching converter comprising: a plurality of power stages for generating a regulated supply voltage on a power rail; and a phase controller to control the operation of one or more of said plurality of power stages to cause generation of said regulated supply voltage via control signal, wherein said phase controller places only select ones of said plurality of power stages in an active state to together generate a requisite load current and places any remaining ones of said plurality of power stages in an inactive state to not contribute to said requisite load current, wherein a first power stage of said plurality of power stages comprises: wherein said control signal is in another state to turn off both of said high-side switch and said low-side switch to place said power stage in an inactive state in which said power stage does not to contribute to requisite load current in a second duration, wherein said second duration spans multiple successive ones of said period; said entire second duration spanning said multiple successive ones of said period.
Tang teaches (see figures 1-5) a multi-phase switching converter (figure 1, part 100) comprising: a plurality of power stages (figures 1 and 5, part 102) for generating a regulated supply voltage on a power rail (figures 1 and 5, part Vout); and a phase controller (figures 1 and 5, part 104) to control the operation of one or more of said plurality of power stages (figures 1 and 5, part 102; through pwm) to cause generation of said regulated supply voltage (figures 1 and 5, part Vout) via control signal (figures 1, 4 and 5, part PWM), wherein said phase controller (figures 1 and 5, part 104) places only select ones of said plurality of power stages in an active state (figure 1, part select ones of said plurality of power stages 102 placed in active state to meet with the requisite load current at 106) to together generate a requisite load current (figure 1, part requisite load current at 106) and places any remaining ones of said plurality of power stages in an inactive state (figure 1, part remaining ones of said plurality of power stages 102 placed in inactive state to not contribute to said requisite load current at 106) to not contribute to said requisite load current (figure 1, part requisite load current at 106) (paragraphs [0002]-[0003]; Multiple phases (power stages) can be connected in parallel to the load through respective inductors to meet high output current requirements… Light load conditions result in periods where the power stage has little or no activity. Multiphase converters typically have the ability to drop phases, where one or more phases are not actively switching and not supporting any of the additional current. In addition, for extremely light load currents, phases may be operating in pulse frequency mode, where a substantial amount of time passes between switch cycles in which the power stage is not switching. Thus, DC-DC voltage regulators have multiple operating modes where having one or more power stages in sleep mode is desirable to reduce power loss), wherein a first power stage (figures 1 and 5, part first 102) of said plurality of power stages (figures 1 and 5, part 102) comprises: a high-side switch (figure 5, part HS FET) and a low-side switch (figure 5, part LS FET) to respectively drive an inductor (figures 1 and 5, part L) in a first interval (figure 4, part first interval) and a second interval periodically (figure 4, part second interval) based on a control signal (figures 1, 4 and 5, part PWM), wherein said inductor (figures 1 and 5, part L) is coupled to a junction of said high-side switch (figure 5, part HS FET) and said low-side switch (figure 5, part LS FET); wherein said control signal (figures 1, 4 and 5, part PWM) is in a first logic state (figures 1, 4 and 5, part PWM; first logic state at on time) to turn on said high-side switch (figures 4 and 5, part HS FET; turn on at on time) and turn off said low-side switch (figures 4 and 5, part LS FET; turn-off at on time) and in a second logic state (figures 1, 4 and 5, part PWM; second logic state at off time) to turn off said high-side switch (figures 4 and 5, part HS FET; turn off at off time) and turn on said low-side switch (figures 4 and 5, part LS FET; turn-on at off time), wherein said control signal (figures 1, 4 and 5, part PWM) is repeatedly switched between said first logic state (figures 1, 4 and 5, part PWM; first logic state at on time) and said second logic state (figures 1, 4 and 5, part PWM; second logic state at off time) with a period to cause said power stage (figures 1 and 5, part 102; period where the power stage 102 is in active state to contribute to said requisite load current at 106) to contribute to said requisite load current in a first duration (figures 1 and 5, part 102; period where the power stage 102 is in active state to contribute to said requisite load current at 106 in first duration), wherein said control signal is in another state (figures 1, 4 and 5, part PWM; another state at HiZ) to turn off both of said high-side switch (figures 4 and 5, part HS FET; turn off at Hiz) and said low-side switch (figures 4 and 5, part LS FET; turn-off at HiZ) to place said power stage in an inactive state (figures 1 and 5, part 102; at inactive state) in which said power stage does not to contribute (figures 1 and 5, part 102; inactive state because does not contribute to said requisite load current at 106) to requisite load current in a second duration (figures 1 and 5, part 102; inactive state because does not contribute to said requisite load current at 106 in second duration), wherein said second duration spans multiple successive ones of said period (figures 1 and 5, part 102; inactive state because does not contribute to said requisite load current at 106 in second duration; where this second duration spans multiple successive ones of said period depending on the time at sleep mode [where is no needed the power contribution of this phase]) (paragraphs [0017]-[0022]; the switching state of the power stage 102 is determined by PWM control. The power stage 102 connects the load 106 to an input voltage of the voltage regulator 100 in a first switching state when the PWM control signal provided to the power stage 102 is active (on) and to ground in a second switching state when the PWM control signal is not active (off) as shown in FIG. 4. The power stage 102 operates in the nominal power mode in either PWM switching state (i.e. PWM on or off). To force the power stage 102 into the sleep mode, the controller 104 deactivates the PWM control signal to indicate a HiZ state in which the power stage 102 does not switch i.e. the high-side and low-side switches of the power stage 102 are off. If the power management unit 112 of the power stage 102 detects the PWM control signal is in the HiZ non-switching state for a predetermined period of time, the power stage 102 moves from the nominal power mode to the sleep (low power) mode (Block 300). The controller 102 includes control logic 114 that keeps the PWM control signal asserted in the HiZ state for a sufficient period of time to force the power stage 102 into the sleep mode); a current-sense block (figure 5, part 216) to generate on an output node of said power stage (figure 5, part output node of 216), information (figure 5, part imon) representing a magnitude of inductor-current flowing through said inductor (figures 1 and 5, part inductor-current flowing through L) (paragraph [0024]-[0033]; the power stage 102 can include a current monitor 216 for measuring or sensing the output current of the power stage 102 through the inductor (L)… the power management unit 112 can disable the current monitor 216 and/or the temperature sensor 218 in both the sleep and deep sleep modes because the power stage output current is zero and the power stage temperature is non-critical when the power stage 102 is idle/not switching); and said entire second duration spanning said multiple successive ones of said period (figures 1 and 5, part 102; inactive state because does not contribute to said requisite load current at 106 in second duration; where this second duration spans multiple successive ones of said period depending on the time at sleep mode [where is no needed the power contribution of this phase]).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to apply the switching converter features of La Pila to the multi-phase switching converter as taught Tang and obtain a multi-phase switching converter comprising: a plurality of power stages for generating a regulated supply voltage on a power rail; and a phase controller to control the operation of one or more of said plurality of power stages to cause generation of said regulated supply voltage via a control signal, wherein said phase controller places only select ones of said plurality of power stages in an active state to together generate a requisite load current and places any remaining ones of said plurality of power stages in an inactive state to not contribute to said requisite load current, wherein a first power stage of said plurality of power stages comprises: a high-side switch and a low-side switch to respectively drive an inductor in a first interval and a second interval periodically based on a control signal, wherein said inductor is coupled to a junction of said high-side switch and said low-side switch, wherein said control signal is in a first logic state to turn on said high-side switch and turn off said low-side switch and in a second logic state to turn off said high-side switch and turn on said low-side switch, wherein said control signal is repeatedly switched between said first logic state and said second logic state with a period to cause said power stage to contribute to said requisite load current in a first duration, wherein said control signal is in another state to turn off both of said high-side switch and said low-side switch to place said power stage in an inactive state in which said power stage does not to contribute to requisite load current in a second duration, wherein said second duration spans multiple successive ones of said period; a current-sense block to generate on an output node of said power stage, information representing a magnitude of inductor-current flowing through said inductor; and a switch coupled between said output node and an output pin of said power stage, wherein, when said power stage is inactive: a portion of said current-sense block driving said output node is maintained in a powered-ON state; and said switch is operated to be open to disconnect said output node from said output pin in said entire second duration spanning said multiple successive ones of said period, because the combination result in more efficient and accurate power conversion in a multi-phase system with more accurate control and power dissipation reduction (paragraph [0015]).
Regarding claim 10, claim 2 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 11, claim 3 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 12, claim 4 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 13, claim 5 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 14, claim 6 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 15, claim 7 has the same limitations, based on this is rejected for the same reasons.
Allowable Subject Matter
Claims 8 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The closest prior art (which has been made of record) fail to disclose (by themselves or in combination):
Regarding claim 8, said current-sense block comprises: a fully differential amplifier as said amplifier, coupled to receive, on differential input terminals, a voltage across said low-side switch; a first capacitor, a second capacitor, a first transistor, a second transistor; and a first switch, a second switch and a third switch, wherein a first current terminal of said first transistor is coupled to a first constant reference potential, and a second current terminal of said first transistor is coupled to said output node, wherein a first current terminal of said second transistor is coupled to a second constant reference potential, and a second current terminal of said second transistor is coupled to said output node, wherein said first capacitor is coupled between a control terminal of said first transistor and said first constant reference potential, wherein said second capacitor is coupled between a control terminal of said second transistor and said second constant reference potential, wherein said first switch is coupled between a first one of a pair of differential outputs of said fully differential amplifier and said control terminal of said first transistor, wherein said second switch is coupled between a second one of said pair of differential outputs and said control terminal of said second transistor, wherein said third switch is coupled between said differential input terminals, wherein said third switch is operable to be closed when said power stage is inactive, and wherein each of said first switch and said second switch is operable to be closed in said first interval and said second interval, except during a blanking interval between said first interval and said second interval;
Regarding claim 16, said current-sense block comprises: a fully differential amplifier as said amplifier, coupled to receive, on differential input terminals, a voltage across said low-side switch; a first capacitor, a second capacitor, a first transistor, a second transistor; and a first switch, a second switch and a third switch, wherein a first current terminal of said first transistor is coupled to a first constant reference potential, and a second current terminal of said first transistor is coupled to said output node, wherein a first current terminal of said second transistor is coupled to a second constant reference potential, and a second current terminal of said second transistor is coupled to said output node, wherein said first capacitor is coupled between a control terminal of said first transistor and said first constant reference potential, wherein said second capacitor is coupled between a control terminal of said second transistor and said second constant reference potential, wherein said first switch is coupled between a first one of a pair of differential outputs of said fully differential amplifier and said control terminal of said first transistor, wherein said second switch is coupled between a second one of said pair of differential outputs and said control terminal of said second transistor, wherein said third switch is coupled between said differential input terminals, wherein said third switch is operable to be closed when said power stage is inactive, and wherein each of said first switch and said second switch is operable to be closed in said first interval and said second interval, except during a blanking interval between said first interval and said second interval;
In combination with the additionally claimed features, as are claimed by the Applicant. Thus, the Applicant’s claims are determined to be novel and non-obvious.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance”.
Response to Arguments
Applicant's arguments filed 03/09/2026 have been fully considered but they are not persuasive.
Applicant’s argues on pages 8-9 of the Applicant's Response (“it is submitted that the presented claims are allowable over the art of record… The operation in DCM mode cannot be equated to the claimed inactive state”).
The Examiner respectfully disagrees with Applicant’s arguments, because the rejection is a 103 combination of La Pila and Tang. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). In this case, La Pila discloses in a single a power stage (figure 13, part 402) with almost all the controller features (see rejection above). Additional, La Pila discloses said control signal is in another state (figures 13 and 16, part PWM control signal at another state [at High-Z] used to generates 410/420) to turn off both of said high-side switch (figures 13 and 16, part 404; turn-off [at High-Z]) and said low-side switch (figures 13 and 16, part 414; turn-off [at High-Z]) to place said power stage (figure 13, part 402) in an inactive state (figure 13, part 402; inactive state) in which said power stage does not to contribute to requisite load current in a second duration (figure 13, part not contribution to requisite load current at Load at High-Z) (paragraph [0126]; the high-impedance (High-Z) state of controlling switching (where both of the transistors 404 and 414 are turned off and a high impedance condition exists at the switching node 406) introduces a contribution to the average coil current in which the coil current is zero). Tang teaches a power stage (figure 1, part 102) of a plurality of power stages (figure 1, part plurality of 102) contained in a multi-phase switching converter (figure 1, part 100), wherein only select ones of said plurality of power stages are placed in an active state (figure 1, part select ones of said plurality of power stages 102 placed in active state to meet with the requisite load current at 106) to together generate a requisite load current (figure 1, part requisite load current at 106) and any remaining ones of said plurality of power stages are placed in an inactive state (figure 1, part remaining ones of said plurality of power stages 102 placed in inactive state to not contribute to said requisite load current at 106) to not contribute to said requisite load current (figure 1, part requisite load current at 106), said power stage (figures 1 and 5, part 102) (paragraphs [0002]-[0003]; Multiple phases (power stages) can be connected in parallel to the load through respective inductors to meet high output current requirements… Light load conditions result in periods where the power stage has little or no activity. Multiphase converters typically have the ability to drop phases, where one or more phases are not actively switching and not supporting any of the additional current. In addition, for extremely light load currents, phases may be operating in pulse frequency mode, where a substantial amount of time passes between switch cycles in which the power stage is not switching. Thus, DC-DC voltage regulators have multiple operating modes where having one or more power stages in sleep mode is desirable to reduce power loss) comprising: wherein said control signal (figures 1, 4 and 5, part PWM) is in a first logic state (figures 1, 4 and 5, part PWM; first logic state at on time) to turn on said high-side switch (figures 4 and 5, part HS FET; turn on at on time) and turn off said low-side switch (figures 4 and 5, part LS FET; turn-off at on time) and in a second logic state (figures 1, 4 and 5, part PWM; second logic state at off time) to turn off said high-side switch (figures 4 and 5, part HS FET; turn off at off time) and turn on said low-side switch (figures 4 and 5, part LS FET; turn-on at off time), wherein said control signal (figures 1, 4 and 5, part PWM) is repeatedly switched between said first logic state (figures 1, 4 and 5, part PWM; first logic state at on time) and said second logic state (figures 1, 4 and 5, part PWM; second logic state at off time) with a period to cause said power stage (figures 1 and 5, part 102; period where the power stage 102 is in active state to contribute to said requisite load current at 106) to contribute to said requisite load current in a first duration (figures 1 and 5, part 102; period where the power stage 102 is in active state to contribute to said requisite load current at 106 in first duration), wherein said control signal is in another state (figures 1, 4 and 5, part PWM; another state at HiZ) to turn off both of said high-side switch (figures 4 and 5, part HS FET; turn off at Hiz) and said low-side switch (figures 4 and 5, part LS FET; turn-off at HiZ) to place said power stage in an inactive state (figures 1 and 5, part 102; at inactive state) in which said power stage does not to contribute (figures 1 and 5, part 102; inactive state because does not contribute to said requisite load current at 106) to requisite load current in a second duration (figures 1 and 5, part 102; inactive state because does not contribute to said requisite load current at 106 in second duration), wherein said second duration spans multiple successive ones of said period (figures 1 and 5, part 102; inactive state because does not contribute to said requisite load current at 106 in second duration; where this second duration spans multiple successive ones of said period depending on the time at sleep mode [where is no needed the power contribution of this phase]) (paragraphs [0017]-[0022]; the switching state of the power stage 102 is determined by PWM control. The power stage 102 connects the load 106 to an input voltage of the voltage regulator 100 in a first switching state when the PWM control signal provided to the power stage 102 is active (on) and to ground in a second switching state when the PWM control signal is not active (off) as shown in FIG. 4. The power stage 102 operates in the nominal power mode in either PWM switching state (i.e. PWM on or off). To force the power stage 102 into the sleep mode, the controller 104 deactivates the PWM control signal to indicate a HiZ state in which the power stage 102 does not switch i.e. the high-side and low-side switches of the power stage 102 are off. If the power management unit 112 of the power stage 102 detects the PWM control signal is in the HiZ non-switching state for a predetermined period of time, the power stage 102 moves from the nominal power mode to the sleep (low power) mode (Block 300). The controller 102 includes control logic 114 that keeps the PWM control signal asserted in the HiZ state for a sufficient period of time to force the power stage 102 into the sleep mode); a current-sense block (figure 5, part 216) to generate on an output node of said power stage (figure 5, part output node of 216), information (figure 5, part imon) representing a magnitude of inductor-current flowing through said inductor (figures 1 and 5, part inductor-current flowing through L) (paragraph [0024]-[0033]; the power stage 102 can include a current monitor 216 for measuring or sensing the output current of the power stage 102 through the inductor (L)… the power management unit 112 can disable the current monitor 216 and/or the temperature sensor 218 in both the sleep and deep sleep modes because the power stage output current is zero and the power stage temperature is non-critical when the power stage 102 is idle/not switching); and said entire second duration spanning said multiple successive ones of said period in said inactive state (figures 1 and 5, part 102; inactive state because does not contribute to said requisite load current at 106 in second duration; where this second duration spans multiple successive ones of said period depending on the time at sleep mode [where is no needed the power contribution of this phase]). It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to apply the switching converter features of La Pila to the multi-phase switching converter as taught Tang and obtain a power stage of a plurality of power stages contained in a multi-phase switching converter, wherein only select ones of said plurality of power stages are placed in an active state to together generate a requisite load current and any remaining ones of said plurality of power stages are placed in an inactive state to not contribute to said requisite load current, said power stage comprising: a high-side switch and a low-side switch to respectively drive an inductor in a first interval and a second interval periodically based on a control signal, wherein said inductor is coupled to a junction of said high-side switch and said low-side switch, wherein said control signal is in a first logic state to turn on said high-side switch and turn off said low-side switch and in a second logic state to turn off said high-side switch and turn on said low-side switch, wherein said control signal is repeatedly switched between said first logic state and said second logic state with a period to cause said power stage to contribute to said requisite load current in a first duration, wherein said control signal is in another state to turn off both of said high-side switch and said low-side switch to place said power stage in an inactive state in which said power stage does not to contribute to requisite load current in a second duration, wherein said second duration spans multiple successive ones of said period; a current-sense block to generate on an output node of said power stage, information representing a magnitude of inductor-current flowing through said inductor; and a switch coupled between said output node and an output pin of said power stage, wherein, when said power stage is inactive: a portion of said current-sense block driving said output node is maintained in a powered-ON state; and said switch is operated to be open to disconnect said output node from said output pin in said entire second duration spanning said multiple successive ones of said period in said inactive state, because the combination result in more efficient and accurate power conversion in a multi-phase system with more accurate control and power dissipation reduction (paragraph [0015]). Therefore, the combination of La Pila and Tang result in the claimed limitation.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Carlos O. Rivera-Pérez, whose telephone number is (571) 272-2432 and fax is (571) 273-2432. The examiner can normally be reached on Monday through Friday, 8:30 AM – 5:00 PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V. Tran can be reached on (571) 270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C.O.R. /
Examiner, Art Unit 2838
Prosecution Insights