DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4-6, 8, 10, 11, and 13-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tanaka et al. (US Publication 2020/0266001).
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Figure 3 of Tanaka with Examiner’s Comments (Figure 3EC)
In re claim 1, Tanaka discloses a multilayer ceramic capacitor comprising:
a multilayer body (12 – Figure 1, Figure 2, Figure 3, ¶29) including a plurality of laminated dielectric layers (20 – Figure 2, Figure 3, ¶30) and a plurality of laminated internal electrode layers (22, 24 – Figure 2, Figure 3, ¶30), a first main surface and a second main surface (17, 18 – Figure 1, Figure 2, ¶29) opposed to each other in a height direction (‘T’ direction – Figure 1), a first lateral surface and a second lateral surface (15, 16 – Figure 1, ¶29) opposed to each other in a width direction (‘W’ direction – Figure 1) orthogonal or substantially orthogonal to the height direction (‘T’ direction – Figure 1), a first end surface and a second end surface (13, 14 – Figure 1, ¶29) opposed to each other in a length direction (‘L’ direction – Figure 1) orthogonal or substantially orthogonal to the height direction and the width direction (Figure 1), an effective layer portion (EL – Figure 3EC, ¶30) including the plurality of dielectric layers and the plurality of internal electrode layers that are alternately laminated (Figure 3EC), and outer layer portions (OL – Figure 3EC, ¶30) that sandwich the effective layer portion in the height direction (‘T’ direction – Figure 1, Figure 3EC);
a first external electrode (40 – Figure 1, Figure 2, ¶52) on the first end surface (Figure 1); and
a second external electrode (42 – Figure 1, Figure 2, ¶52) on the second end surface (Figure 1); wherein
the multilayer body further includes:
an outer layer interior portion (32b, 34b within OL – Figure 3EC, ¶41) inside one of the outer layer portions (OL – Figure 3EC);
an outermost effective layer vicinity portion (topmost or bottommost 22a, 24a within EL – Figure 3EC, ¶38) , which is closest to one of the outer layer portions (Figure 3EC), in the effective layer portion (EL – Figure 3EC);
a chip middle portion (32a, 34a in a central portion of 12 in the ‘T’ direction – Figure 1, Figure 3EC, ¶41) in a middle portion of the multilayer body (12 – Figure 3EC); and
a plurality of silicon oxide segregation regions (Figure 5, ¶19, ¶38, ¶45) ; and
in a cross section of the multilayer body in a plane parallel or substantially parallel to the width direction and the height direction (Figure 3EC, Figure 5), a relationship of average cross sectional areas of a plurality of silicon oxide segregation regions in respective portions of the outer layer interior portion (32b, 34b within OL – Figure 3EC, ¶41), the chip middle portion (32a, 34a in a central portion of 12 in the ‘T’ direction – Figure 1, Figure 3EC, ¶41), and the outermost effective layer vicinity portion (topmost or bottommost 22a, 24a within EL – Figure 3EC, ¶38) is expressed as:
the outer layer interior portion < the chip middle portion < the outermost effective layer vicinity portion (Figure 5; Note that Si is segregated more in region 34a than 34b. Further, note that Si is segregated more in region 22a than 34a.).
In re claim 4, Tanaka discloses the multilayer ceramic capacitor according to claim 1, as explained above. Tanaka further discloses wherein the multilayer body (12 – Figure 1) has a rectangular or substantially rectangular parallelepiped shape (Figure 12).
In re claim 5, Tanaka discloses the multilayer ceramic capacitor according to claim 1, as explained above. Tanaka further discloses wherein a dimension in the length direction of the multilayer body is about 0.2 mm or more and about 6 mm or less, a dimension in the height direction of the multilayer body is about 0.05 mm or more and about 5 mm or less, and a dimension of the multilayer body in the width direction is about 0.1 mm or more and about 5 mm or less (¶95).
In re claim 6, Tanaka discloses the multilayer ceramic capacitor according to claim 1, as explained above. Tanaka further discloses wherein each of the plurality of dielectric layers (20 – Figure 2, Figure 3) includes barium titanate, calcium titanate, strontium titanate, or calcium zirconate as a main component (¶31, ¶44).
In re claim 8, Tanaka discloses the multilayer ceramic capacitor according to claim 1, as explained above. Tanaka further discloses wherein a thickness of each of the plurality of dielectric layers is about 0.2 μm or more and about 10 μm or less (¶30).
In re claim 10, Tanaka discloses the multilayer ceramic capacitor according to claim 1, as explained above. Tanaka further discloses wherein each of the plurality of internal electrode layers includes nickel, copper, silver, palladium, or gold, or an alloy including at least one of nickel, copper, silver, palladium, or gold (¶37).
In re claim 11, Tanaka discloses the multilayer ceramic capacitor according to claim 1, as explained above. Tanaka further discloses wherein a thickness of each of the plurality of internal electrode layers is about 0.2 μm or more and about 2.0 μm or less (¶36).
In re claim 13, Tanaka discloses the multilayer ceramic capacitor according to claim 1, as explained above. Tanaka further discloses wherein the first external electrode (40 – Figure 1) extends from the first end surface (13 – Figure 1) to portions of each of the first and second main surfaces (17, 18 – Figure 1) and each of the first and second lateral surfaces (15, 16 – Figure 1); and
the second external electrode (42 – Figure 1) extends from the first end surface (14 – Figure 1) to portions of each of the first and second main surfaces (17, 18 – Figure 1) and each of the first and second lateral surfaces (15, 16 – Figure 1).
In re claim 14, Tanaka discloses the multilayer ceramic capacitor according to claim 1, as explained above. Tanaka further discloses wherein the first external electrode (40 – Figure 1) includes a first base electrode layer (40a – Figure 1, ¶56) and a first plated layer (40b – Figure 1, ¶57); and
the second external electrode (42 – Figure 1) includes a second base electrode layer (42a – Figure 2, ¶56) and a second plated layer (42b – Figure 2, ¶57).
In re claim 15, Tanaka discloses the multilayer ceramic capacitor according to claim 14, as explained above. Tanaka further discloses wherein each of the first and second base electrode layers (40a, 42a – Figure 1) is a fired layer (¶56).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka et al. (US Publication 2020/0266001) in view of Sato et al. (US Publication 2009/0195960).
In re claim 7, Tanaka discloses the multilayer ceramic capacitor according to claim 1, as explained above. Tanaka does not disclose wherein each of the plurality of dielectric layers includes a manganese compound, an iron compound, a copper compound, a cobalt compound, or a nickel compound as a subcomponent.
Sato discloses each of the plurality of dielectric layers includes a manganese compound (¶24), an iron compound, a copper compound, a cobalt compound, or a nickel compound as a subcomponent (¶81).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the manganese subcomponent of Sato to increase IR and improve high temperature accelerated lifetime (¶81: Tanaka).
Claim(s) 9 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka et al. (US Publication 2020/0266001).
In re claim 9, Tanaka discloses the multilayer ceramic capacitor according to claim 1, as explained above. Tanaka does not disclose wherein a number of the plurality of dielectric layers is 15 or more and 1200 or less. However, it is well-known in the art that adjusting the number of dielectric layers, and thus conductive layers, is correlated to the capacitance of the device. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to adjust the number of dielectric layers to achieve a device having a desired balance between capacitance and component size per user specifications, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
In re claim 12, Tanaka discloses the multilayer ceramic capacitor according to claim 1, as explained above. Tanaka does not disclose wherein a number of the plurality of internal electrode layers is 15 or more and 1000 or less. However, it is well-known in the art that adjusting the number of conductive layers is correlated to the capacitance of the device. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to adjust the number of internal electrode layers to achieve a device having a desired balance between capacitance and component size per user specifications, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Claim(s) 16-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka et al. (US Publication 2020/0266001) in view of Morita (US Publication 20230223196).
In re claim 16, Tanaka discloses the multilayer ceramic capacitor according to claim 15, as explained above. Tanaka does not disclose wherein the fired layer includes a metal component and at least one of a glass component and a ceramic component.
Morita discloses wherein the fired layer (combination of 21, 22 – Figure 6, ¶58, ¶54) includes a metal component (¶61) and at least one of a glass component (24 – Figure 6, ¶73) and a ceramic component (23 – Figure 6, ¶69-70, ¶72).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the external electrode material of Morita to suppress cracks in the electronic component (¶8: Morita).
In re claim 17, Tanaka discloses the multilayer ceramic capacitor according to claim 16, as explained above. Tanaka further discloses wherein the metal component includes at least one of one of copper, nickel, silver, palladium, an alloy of silver and palladium, or gold (¶55-56).
In re claim 18, Tanaka discloses the multilayer ceramic capacitor according to claim 15, as explained above. Tanaka does not disclose wherein the glass component includes at least one of boron, silicon, barium, magnesium, aluminum, or lithium.
Morita discloses wherein the glass component (24 – Figure 6) includes at least one of boron, silicon, barium, magnesium, aluminum, or lithium (¶73).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the external electrode material of Morita to suppress cracks in the electronic component (¶8: Morita).
In re claim 19, Tanaka discloses the multilayer ceramic capacitor according to claim 15, as explained above. Tanaka does not disclose wherein the ceramic component includes at least one of barium titanate, calcium titanate, a mixed crystal material obtained by replacing a portion of the barium of barium titanate with calcium, strontium titanate, or calcium zirconate.
Morita discloses wherein the ceramic component (23 – Figure 6) includes at least one of barium titanate, calcium titanate, a mixed crystal material obtained by replacing a portion of the barium of barium titanate with calcium, strontium titanate, or calcium zirconate (¶68).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the external electrode material of Morita to suppress cracks in the electronic component (¶8: Morita).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka et al. (US Publication 2020/0266001) in view of Kim et al. (US Publication 2023/0215649).
In re claim 20, Tanaka discloses the multilayer ceramic capacitor according to claim 14, as explained above. Tanaka does not disclose wherein a thickness of each of the first and second base electrode layers is about 10 μm or more and about 200 μm or less.
Kim discloses that adjusting the thickness of an external electrode layer is correlated with the ESR characteristics of the device (¶82).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to adjust the thickness of the external electrodes to realize a device having a desired balance between ESR characteristics and component size per user specifications, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Allowable Subject Matter
Claim 2 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The prior art does not teach nor suggest (in combination with other claim limitations) a relationship of values of an area equivalent diameter of the plurality of silicon oxide segregation regions in the respective portions of the outer layer interior portion, the chip middle portion, and the outermost effective layer vicinity portion is expressed as: the outer layer interior portion < the chip middle portion < the outermost effective layer vicinity portion.
Claim 3 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The prior art does not teach nor suggest (in combination with other claim limitations) a relationship of an average cross sectional area of cross sections of the multilayer body in a plane parallel or substantially parallel to the width direction and the height direction at portions having a circularity of about 0.8 or less among the plurality of silicon oxide segregation regions in the respective portions of the outer layer interior portion, the chip middle portion, and the outermost effective layer vicinity portion is expressed as: the outer layer interior portion < the chip middle portion < the outermost effective layer vicinity portion.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Taniguchi (US Publication 2023/0352240) Claim 1, Figure 4
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/ARUN RAMASWAMY/ Primary Examiner, Art Unit 2848