DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in this application.
Response to Amendment
Claims 1-4, 6, 8, 10-14, 16, 18, and 20 are amended.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. While allowable subject matter was indicated in the previous action mailed 10/23/2025, the scope of the amended claims has been significantly changed and no longer contain all of the limitations of any of the claims that were indicated as containing allowable subject matter.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 13 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 13 recites the limitation "the NTC resistor" in line 4 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 10-12, and 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsukamoto et al. U.S. Patent Application 2018/0034458 (hereinafter “Tsukamoto”)
Regarding claim 1, Tsukamoto teaches a circuit (refer to fig.1) comprising: an amplifier (i.e. comparator 30)(fig.1) having first (refer to Vin(+))(fig.1) and second amplifier inputs (refer to Vin(-))(fig.1) and an amplifier output (i.e. Vout)(fig.1), the first amplifier input coupled to a first transistor current terminal (i.e. S)(fig.1), and the amplifier output coupled to a transistor control terminal (i.e. G)(fig.1)(output of CMP1 is coupled to the control terminal through the control circuit 40 and FET driver 21); a resistor (i.e. resistor 34)(fig.1) coupled between a second transistor current terminal (i.e. D)(fig.1) and the second amplifier input (implicit); and a current source (i.e. constant current source 35)(fig.1) coupled to the second amplifier input (implicit).
Regarding claim 10, Tsukamoto teaches the circuit of claim 1, further comprising a gate drive circuit (i.e. control circuit 40 and FET driver 21)(fig.1) having a gate drive input (implicit) and a gate drive output (implicit), wherein the gate drive input is coupled to the amplifier output (implicit), and the gate drive output is coupled to the transistor control terminal (implicit).
Regarding claim 11, Tsukamoto teaches a system (refer to fig.1) comprising: a transistor (i.e. switch 20)(fig.1) having first (i.e. S)(fig.1) and second transistor current terminals (i.e. D)(fig.1) and a transistor control terminal (i.e. G)(fig.1); an amplifier (i.e. comparator 30)(fig.1) having first (i.e. Vin(+)(fig.1) and second amplifier inputs (i.e. Vin(-)(fig.1) and an amplifier output (i.e. Vout)(fig.1), the first amplifier input coupled to the first transistor current terminal (implicit); a resistor (i.e. resistor 34)(fig.1) coupled between the second transistor current terminal and the second amplifier input (implicit); and a current source (i.e. constant current source 35)(fig.1) coupled to the second amplifier input (implicit).
Regarding claim 12, Tsukamoto teaches the system of claim 11, further comprising a gate drive circuit (i.e. control circuit 40 and FET driver 21)(fig.1) having a gate drive input (implicit) and a gate drive output (implicit), wherein the gate drive input is coupled to the amplifier output (implicit), the gate drive output is coupled to the transistor control terminal (implicit), and the gate drive circuit is configured to control the transistor to shut off responsive to a comparison involving a voltage at the second amplifier input and a voltage at the first amplifier input (implicit)(refer to [0029]).
Regarding claim 15, Tsukamoto teaches the system of claim 11, wherein the amplifier is configured as a comparator (i.e. comparator 30)(fig.1).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 2 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsukamoto as applied to claim 1 above, and further in view of Oshima U.S. Patent N. 6,831,821 (hereinafter “Oshima”).
Regarding claim 2, Tsukamoto teaches the circuit of claim 1, wherein the resistor is a first resistor (implicit); however, Tsukamoto does not teach wherein the circuit further comprises: a voltage source and a second resistor coupled between the first transistor current terminal and the first amplifier input. However, Oshima teaches wherein the circuit further comprises: a voltage source (i.e. voltage setting circuit 2)(fig.1) and a second resistor (i.e. resistor R3)(fig.1) coupled between the first transistor current terminal (i.e. first terminal in the figure below)(fig.1) and the first amplifier input (i.e. first input in the figure below)(fig.1). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Tsukamoto to include the voltage source of Oshima to provide the advantage of creating a threshold bias voltage for determining overcurrent.
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Regarding claim 6, Tsukamoto and Oshima teach the circuit of claim 2, wherein the voltage source is configurable to provide a voltage representing to an overcurrent limit threshold (refer to Oshima col. 6 lines 1-15).
Claim(s) 8, 9, 13, 18, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsukamoto as applied to claim 1 above, and further in view of Wu et al. Chinese Patent Document CN 112165075 A (hereinafter “Wu”).
Regarding claim 8, Tsukamoto teaches the circuit of claim 1; however, Tsukamoto does not teach wherein the resistor is an NTC resistor, and a voltage at the second amplifier input decreases when a temperature of the NTC resistor decreases. However, Wu teaches wherein the resistor is an NTC resistor (i.e. R-NTC)(fig.1), and a voltage at the second amplifier input decreases when a temperature of the NTC resistor decreases (implicit)(refer to fig.1). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Tsukamoto to include the NTC resistor of Wu to provide the advantage of providing better performance of the overcurrent protection circuit over a wider temperature range.
Regarding claim 9, Tsukamoto and Wu teach the circuit of claim 8, wherein the voltage at the second amplifier input increases when the temperature of the NTC resistor increases (implicit)(refer to Wu fig.1).
Regarding claim 13, Tsukamoto teaches the system of claim 11, wherein the resistor is a first resistor (implicit), and the current source is a first current source (implicit); however, Tsukamoto does not teach wherein the system further comprises: a second resistor coupled in parallel with the NTC resistor. However, Wu teaches wherein the system further comprises: a second resistor (i.e. resistor R2)(fig.1) coupled in parallel with the NTC resistor (i.e. R-NTC)(fig.1). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Tsukamoto to include the second resistor and NTC resistor of Wu to provide the advantage of providing better performance of the overcurrent protection circuit over a wider temperature range.
Regarding claim 18, Tsukamoto teaches the system of claim 11; however, Tsukamoto does not teach wherein the resistor is an NTC resistor, and a voltage at the second amplifier input decreases when a temperature of the NTC resistor decreases. However, Wu teaches wherein the resistor is an NTC resistor (i.e. R-NTC)(fig.1), and a voltage at the second amplifier input decreases when a temperature of the NTC resistor decreases (implicit)(refer to fig.1). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Tsukamoto to include the NTC resistor of Wu to provide the advantage of providing better performance of the overcurrent protection circuit over a wider temperature range.
Regarding claim 19, Tsukamoto and Wu teach the system of claim 18, wherein the voltage at the second amplifier input increases when the temperature of the NTC resistor increases (implicit)(refer to Wu fig.1).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsukamoto as applied to claim 11 above, and further in view of Mao U.S. Patent No. 6,300,818 (hereinafter “Mao”).
Regarding claim 20, Tsukamoto teaches the system of claim 11; however, Tsukamoto does not teach wherein the resistor is located proximate the transistor. However, Mao teaches wherein the resistor is located proximate the transistor (refer to col. 4 lines 30-39). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Tsukamoto to include the location of the resistor of Mao to provide the advantage of compensating for the temperature of the transistor to provide better performance of the overcurrent protection circuit over a wider temperature range.
Allowable Subject Matter
Claims 3-5, 7, 14, 16, and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for the indication of allowable subject matter: Claims 3-5 and 7 are indicated as containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 3, especially wherein the current source is a first current source, and the circuit further comprises a second current source coupled between the a terminal of the second resistor and a ground terminal. Claims 4, 5, and 7 are indicated as containing allowable subject matter based on their dependency on claim 3.
Claims 14, 16, and 17 are indicated as containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 14, especially wherein the current source is a first current source, and the system is further comprising: a voltage source and a third resistor coupled between the first transistor current terminal and the first amplifier input; and a second current source coupled between a terminal of the third resistor and a ground terminal. Claims 16 and 17 are indicated as containing allowable subject matter based on their dependency on claim 14.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEVIN J COMBER whose telephone number is (571)272-6133. The examiner can normally be reached Monday - Friday, 9:00 am - 5:00 pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V. Tran can be reached at 571-270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KEVIN J COMBER/Primary Examiner, Art Unit 2838