DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office action is in response to amendment filed 11/3/2025.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 8 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Grassi (US 2022/0121577 A1) in view of Patel (US 2024/0272905 A1).
Regarding claim 1, Grassi discloses an apparatus as shown in figure 3 comprising: circuitry (figure 3, 305) configured to: receive a first vector memory access instruction and a second vector memory access instruction ([0065], a request processor that processing incoming transaction requests); send the first vector memory access instruction to a first execution pipeline, and send the second vector memory access instruction to a second execution pipeline different from the first execution pipeline, wherein the second execution pipeline has a lower access latency than a latency of the first execution pipeline ([0065], the request processor can split a transaction and initiate a first request using a fast sequential access pipeline and initiate a second request using a slow random access pipeline). Grassi differs from the claimed invention in not specifically teaching to send the first vector memory access instruction to a first execution pipeline, responsive to the first vector memory access instruction not being a vector stack access instruction; and send the second vector memory access instruction to a second execution pipeline different from the first execution pipeline, responsive to the second vector memory access instruction being a vector stack access instruction, wherein the second execution pipeline has a lower access latency than a latency of the first execution pipeline. However, Patel teaches to organize access requests into vectors and a stack such that the vectors can be organized as linear vectors or a push-pop stack, thereby memory access instruction not being a vector stack access instruction may process in one execution pipeline and memory access instruction being a vector stack access instruction may process in another one execution pipeline ([0042]-[0043]) in order to enhance performance of a processor ([0007]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Grassi to send the first vector memory access instruction to a first execution pipeline, responsive to the first vector memory access instruction not being a vector stack access instruction; and send the second vector memory access instruction to a second execution pipeline different from the first execution pipeline, responsive to the second vector memory access instruction being a vector stack access instruction, wherein the second execution pipeline has a lower access latency than a latency of the first execution pipeline, as per teaching of Patel, in order to enhance performance of a processor.
Regarding claim 8, the limitations of the claim are rejected as the same reasons as set forth in claim 1.
Regarding claim 15, the limitations of the claim are rejected as the same reasons as set forth in claim 1.
Allowable Subject Matter
Claims 2-7, 9-14, and 16-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed 11/3/2025 have been fully considered but they are not persuasive.
In response to applicant's argument that the references fail to show “responsive to the first vector memory access instruction not being a vector stack access instruction; and send the second vector memory access instruction to a second execution pipeline different from the first execution pipeline, responsive to the second vector memory access instruction being a vector stack access instruction, wherein the second execution pipeline has a lower access latency than a latency of the first execution pipeline” as recited in claims 1, 8 and 15, Examiner respectfully disagreed. It is noted that Grassi teaches the invention concept of splitting a transaction and initiating a first request using a fast sequential access pipeline, read as low latency path, and initiate a second request using a slow random access pipeline, read as high latency path (figure 3, [0011] and [0065]), wherein the fast sequential access pipeline has a low access latency than a latency of the slow random access pipeline. Thus Grassi teaches the claimed limitations of sending the second vector memory access instruction to a second execution pipeline different from the first execution pipeline, wherein the second execution pipeline has a lower access latency than a latency of the first execution pipeline. Grassi differs from the claimed invention in not specifically teaching responsive to the first vector memory access instruction not being a vector stack access instruction to send instruction to a particular pipeline. However, Patel teaches an access request organizer can organize access requests into vectors, read as vector memory access instruction, and a stack, read as a vector stack access instruction, and a bus interface can enable transferring instruction utilizing different ways ([figure 3 and [0042]-[0043]) in order to enhance performance of a processor ([0007]). Note claims 1, 8 and 15 does not explicitly define how to access data targeted by the vector stack access instruction in the local memory, or further define the novelty of first execution pipeline and second execution pipeline. Thus, the broad claimed limitations are rejected based on the combination of Grassi and Patel.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Gonion (US 20150227368 A1) discloses a completion time determination circuit may provide the completion time to an issue circuit, which may use the completion time to schedule operations dependent on the vector memory operation (abstract).
Chadha et al. (US 2014/0143523 A1) discloses a method for data processing to improve an effective memory access latency by masking access latency through selective application of posted error detection processing (abstract).
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHUO H LI whose telephone number is (571)272-4183. The examiner can normally be reached Mon. Tue. and Thurs. 8:00-4:00 PM.
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/ZHUO H LI/Primary Examiner, Art Unit 2133