DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Heijden et al. (U.S. 2011/0012682).
Regarding claim 1, Heijden et al. (hereinafter, Ref~682) discloses (please see Fig. 4 and related text for details) a circuit (Fig. 4), comprising:
a power amplifier (see amplifier from Fig. 4);
a voltage divider (resistor pair 30 of Fig. 4) coupled to the power amplifier; and
a bias voltage generator circuit (29 and/or 290 of Fig. 4 is configured to provide a voltage disposed at the gate of the cascode pair) coupled to the voltage divider and to the power amplifier;
wherein the power amplifier comprises:
a first transistor (first/left input transistor 260 of Fig. 4) including a gate terminal coupled to receive a first input signal;
a second transistor (second/right input transistor 260 of Fig. 4) including a gate terminal coupled to receive a second input signal;
a third transistor (first/left cascode transistor 262 of Fig. 4) coupled to the first transistor and coupled to the bias voltage generator circuit; and
a fourth transistor (second/right cascode transistor 262 of Fig. 4) coupled to the second transistor, the bias voltage generator circuit, and the third transistor; and
wherein the voltage divider comprises:
a first resistor (first/left resistor 30 of Fig. 4) that includes a first terminal and a second terminal; and a
second resistor (second/right resistor 30 of Fig. 4) that includes a first terminal and a second terminal;
wherein the first terminal of the first resistor is coupled to the third transistor of the power amplifier;
wherein the second terminal of the second resistor is coupled to the fourth transistor of the power amplifier; and
wherein the second terminal of the first resistor and the first terminal of the second resistor are coupled to each other and coupled to the bias voltage generator circuit as seen, meeting claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 7-11 and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Heijden et al. (U.S. 2011/0012682) in view of Lin et al. (U.S. 2016/0036393).
Regarding claim 2, Ref~682 further discloses the circuit of claim 1, wherein:
the first transistor further includes a source terminal (source of transistor 260 of Fig. 4) and a drain terminal (drain of transistor 260 of Fig. 4);
the second transistor further includes a source terminal (source of transistor 260 of Fig. 4) and a drain terminal (drain of transistor 260 of Fig. 4);
the third transistor includes a gate terminal (gate of 262 of Fig. 4), a source terminal (source of 262 of Fig. 4), and a drain terminal (drain of 262 of Fig. 4);
the fourth transistor includes a gate terminal (gate of 262 of Fig. 4), a source terminal (source of transistor 262 of Fig. 4), and a drain terminal (drain of transistor 262 of Fig. 4).
Ref~382 discloses the invention in a broad sense without showing details of a load circuit(s) that described in paragraph [0031], thus it would be obvious to one skilled in the art to employe said load circuit(s), for instance, an antenna load that required by wireless system mentioned in paragraph [0032].
With said antenna load being used, Ref~682 further supports the claimed “wherein the first terminal of the first resistor and the drain terminal of the third transistor are coupled to a balun (please note that a balun would be required to convert the differential output signals into a single-ended signal before feeding to the antenna. This requirement can be seen in the embodiment of Fig. 3 of Lin et al. being cited to support the claimed feature); and
wherein the second terminal of the second resistor and the drain terminal of the fourth transistor are coupled to the balun, meeting claim 2.
Regarding claim 7, Ref~682 discloses all features except for the claimed “input amplifier”. However, it would be obvious to employ/add said input amplifier (also known as driver or pre-stage) in order to at least obtain desirable gain level for each stage of the system, meeting claims 7-8.
Regarding claim 9, Ref~682 discloses the circuit of claim 7, wherein the first input signal and second input signal are differential signals as seen from Fig. 4, meeting claim 9.
Regarding claims 10-11 and 15-17, limitations from these claims can be rejected in the same manner as described above in claims 1-2 and 7-9, since same features with similar language are being presented here, meeting claims 10-11 and 15-17.
Allowable Subject Matter
Claims 3-6, 12-14 and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HIEU P NGUYEN whose telephone number is 571-272-8577. The examiner can normally be reached on Monday-Friday 8:30AM-6:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, YOUNGHUIE HAN (Jessica) can be reached on 571-272-2078. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306.
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/HIEU P NGUYEN/Primary Examiner, Art Unit 2843
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