DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 9 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9 recites the limitation "the first pattern" in line 11. There is insufficient antecedent basis for this limitation in the claim. Since two separate “first patterns” have been identified in this claim prior to this, “a first active pattern” and “a first via pattern”, it is unclear which is being referred to, and thus it is unclear to which side surface the rail pattern needs to be electrically connected to. Therefore, the claim is rendered indefinite. For the purpose of examining the case on the merits, this limitation was taken to mean the first via pattern.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
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Claims 1-4, 6-7, 9-11, and 13-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Na et al. (US 20220393030 A1), hereinafter referred to as "Na".
In regards to claim 1, Na discloses a semiconductor device, comprising: an active pattern extending in a first direction across an underlying substrate (fin-type patterns 110 across substrate 100 in figure 1 and 24; they extend in direction D1); a gate structure extending in a second direction (120 in figure 1, extends in direction D2), on the active pattern (120 is on 110, see figure 4); a first source/drain contact electrically connected to a source/drain region within the active pattern (185 in figure 24), on one side of the gate structure (see figure 1); a first via pattern electrically connected to an upper surface of the first source/drain contact (207 in figure 24); a rail pattern extending in the first direction (206 on the right side of figure 24; extends in D1 direction), and spaced apart from the first via pattern in the second direction (see figure 24); and a wiring pattern extending in the first direction (211 in figure 24, extends at least partially in the D1 direction), and electrically connected to an upper surface of the rail pattern (electrically connected to 206 through 212); wherein the first source/drain contact includes a first recess therein, which is more recessed downwardly relative to the upper surface of the first source/drain contact (areas between 185PP and 185LP, see annotations in figure 24); and wherein at least a portion of the first recess extends adjacent to the rail pattern (see figure 24).
In regards to claim 2, Na discloses all of the limitations of claim 1. Na further discloses that the first and second directions are orthogonal to each other (D1 and D2 are orthogonal, see figure 1); wherein the first source/drain contact includes an extension portion extending in the second direction (185LP in figure 24), and a protruding portion protruding upwardly from an upper surface of the extension portion (185PP in figure 24); wherein the upper surface of the extension portion defines a lower surface of the first recess; and wherein a side surface of the protruding portion defines a side surface of the first recess (see annotations in figure 24).
In regards to claim 3, Na discloses all of the limitations of claim 2. Na further discloses that the first via pattern is in contact with an upper surface of the protruding portion (207 is in contact with 185PP).
In regards to claim 4, Na discloses all of the limitations of claim 1. Na further discloses a filling insulating film, which fills the first recess (191 in figure 24).
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In regards to claim 6, Na discloses all of the limitations of claim 1. Na further discloses a first interlayer insulating film covering the active pattern and the gate structure, on the substrate (145 in figure 4); and an etch stop layer covering an upper surface of the first interlayer insulating film and the upper surface of the first source/drain contact (197 in figures 4 and 24); wherein the first via pattern penetrates through the etch stop layer (207 penetrates 197 in figure 24) and is electrically connected to the upper surface of the first source/drain contact (207 is in direct electrical contact with 185 in figure 24, and electrically connects 206 to 185, paragraph 0124); and wherein the rail pattern extends on the etch stop layer (rail pattern 206 is on etch stop layer 197 in figure 5).
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In regards to claim 7, Na discloses all of the limitations of claim 1. Na further discloses a second source/drain contact electrically connected to a source/drain region of the active pattern on the other side of the gate structure (186 in figure 1 and 186a in figure 23); and a second via pattern electrically connected to an upper surface of the second source/drain contact (207 in figure 23); and wherein the second via pattern is connected to a side surface of the rail pattern (sides of 206 are connected to the sides of via pattern 207 in figure 23).
In regards to claim 9, Na discloses a semiconductor device, comprising: a first active pattern extending in a first direction across an underlying substrate (fin-type patterns 110 across substrate 100 in figure 1 and 24; they extend in direction D1); a gate structure extending in a second direction intersecting the first direction (120 in figure 1, extends in direction D2, which intersects D1), on the first active pattern (120 is on 110, see figure 4); a first source/drain contact electrically connected to a first source/drain region of the first active pattern, (185 in figure 24), on one side of the gate structure (see figure 1); a first via pattern electrically connected to an upper surface of the first source/drain contact (207 on the right side of figure 24, above 185b); a rail pattern extending in the first direction (206 on right side of figure 24 above 185b, which extends in direction D1), and electrically connected to a side surface of the first pattern ([see 112b rejection above] sides of 206 are connected to the sides of via pattern 207); and a wiring pattern extending in the first direction (211 in figure 24, which extends at least partially in the first direction), and electrically connected to an upper surface of the rail pattern (211 is connected to 206 in figure 24 through 212); and wherein the first source/drain contact includes a first recess, which is recessed more downwardly than the upper surface of the first source/drain contact (areas between 185PP and 185LP, see annotations in figure 24).
In regards to claim 10, Na discloses all of the limitations of claim 9. Na further discloses that the first source/drain contact includes an extension portion extending in the second direction (185LP in figure 24, which extends in D2 direction), and a protruding portion protruding upwardly from an upper surface of the extension portion (185PP in figure 24); wherein the upper surface of the extension portion defines a lower surface of the first recess; and wherein a side surface of the protruding portion defines a side surface of the first recess (see annotations in figure 24).
In regards to claim 11, Na discloses all of the limitations of claim 10. Na further discloses that the first via pattern is in contact with an upper surface of the protruding portion (207 is in contact with top of 185PP in figure 24).
In regards to claim 13, Na discloses all of the limitations of claim 9. Na further discloses that a lower surface of the rail pattern is spaced apart from the upper surface of the first source/drain contact (rail pattern 206 is spaced apart from source/drain contact 185 by via 207).
In regards to claim 14, Na discloses all of the limitations of claim 9. Na further discloses a second source/drain contact electrically connected to a first source/drain region of the first active pattern on the other side of the gate structure (186a in figure 23. It is on the other side of the gate structure, see figure 1, and is electrically connected to source/drain region 150 on active pattern 110); and a second via pattern electrically connected to an upper surface of the second source/drain contact (207 in figure 23); and wherein the second via pattern is spaced apart from the rail pattern in the second direction (the via atop 186a is spaced apart from the rail pattern on the right side of figures 23 and 24 in direction D2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
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Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Na in view of Takahashi et al. (US 20160240476 A1), hereinafter referred to as "Takahashi".
In regards to claim 5, Na discloses all of the limitations of claim 1. Na does not disclose that an upper surface of the first via pattern and the upper surface of the rail pattern are coplanar.
Takahashi teaches vias and metal lines in which an upper surface of the first via pattern and the upper surface of the rail pattern are coplanar (Takashi figure 8A. The tops of drain contact vias 88 are coplanar with the tops of metal interconnects 91). Takahashi also teaches that this allows for them to be formed simultaneously (Takahashi paragraph 0101).
Therefore, it would have obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the via pattern and the rail pattern such that their upper surfaces are coplanar in to form them simultaneously and thus reduce the number of the manufacturing steps.
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Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Na in view of Zang et al. (US 10128187 B2), hereinafter referred to as "Zang".
In regards to claim 8, Na discloses all of the limitations of claim 7. Na does not expressly disclose that the second source/drain contact includes a recess.
Zang teaches several source/drain contacts with recesses, thus teaching that the second source/drain contact includes a second recess recessed more downwardly than the upper surface of the second source/drain contact (124 in Zang figure 13 has recess filled with insulating layer 132). Zang also teaches that the recesses are filled with a low-k dielectric, which separates the source/drain contact from a conductor (146) above it (Zang column 6, lies 60-62, and Zang column 7, lines 43-46).
Therefore, it would have obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the second source/drain contact also have a recess as in Zang, in order to electrically separate the contact from other electrical parts above the contact.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Na in view of Takahashi.
In regards to claim 12, Na discloses all of the limitations of claim 9. Na does not disclose that an upper surface of the first via pattern and the upper surface of the rail pattern are coplanar.
Takahashi teaches vias and metal lines in which an upper surface of the first via pattern and the upper surface of the rail pattern are coplanar (Takashi figure 8A. The tops of drain contact vias 88 are coplanar with the tops of metal interconnects 91). Takahashi also teaches that this allows for them to be formed simultaneously (Takahashi paragraph 0101).
Therefore, it would have obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the via pattern and the rail pattern such that their upper surfaces are coplanar in to form them simultaneously and thus reduce the number of the manufacturing steps.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Na in view of Zang.
In regards to claim 15, Na discloses all of the limitations of claim 14. Na does not expressly disclose that the second source/drain contact includes a recess.
Zang teaches several source/drain contacts with recesses, thus teaching that the second source/drain contact includes a second recess recessed more downwardly than the upper surface of the second source/drain contact (124 in Zang figure 13 has recess filled with insulating layer 132), and at least a portion of the second recess extends between the second via pattern and the rail pattern (part of the recess in Zang figure 13 is between the contact 160, which is effectively a via, and the metal line 146, which is analogous to the rail line. Furthermore, recessing the parts of the source/drain contact in Na not contacting with the via would have the right part of 186a recessed, which is between the via and the rail). Zang also teaches that the recesses are filled with a low-k dielectric, which separates the source/drain contact from a conductor (146) above it (Zang column 6, lies 60-62, and Zang column 7, lines 43-46).
Therefore, it would have obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the second source/drain contact also have a recess as in Zang, in order to electrically separate the contact from other electrical parts above the contact.
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Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Na.
In regards to claim 16, Na discloses all of the limitations of claim 9. Na further discloses a second active pattern extending in the first direction on the substrate and spaced apart from the first active pattern in the second direction (210 in Na figure 1 extends in first direction D1 and is spaced apart from 110 in second direction D2); and a second source/drain contact electrically connected to a second source/drain region of the second active pattern on one side of the gate structure (186b in Na figure 23, the lower 186 in Na figure 1);
In this embodiment, Na does not teach that the rail pattern extends between the first active pattern and the second active pattern.
In a separate embodiment, Na teaches the rail pattern that is connected to the first via pattern extends between the first active pattern and the second active pattern (206 in Na figure 27 is above the area 185c, which is between the active patterns and thus extends between the active patterns).
It would have obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to adjust the positioning of the rail pattern as needed in order to simplify connections on the device and simplify the design process. Furthermore, Na expressly notes that “The features of the various embodiments of the present invention may be partially or entirely combined with each other” (Na paragraph 0033).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Na as applied to claim 16 above, and further in view of Zang.
In regards to claim 17, Na teaches all of the limitations of claim 16. Na does not expressly disclose that the second source/drain contact includes a recess.
Zang teaches several source/drain contacts with recesses, thus teaching that the second source/drain contact includes a second recess recessed more downwardly than the upper surface of the second source/drain contact (124 in Zang figure 13 has recess filled with insulating layer 132), and at least a portion of the second recess extends adjacent to the rail pattern (part of the recess in Zang figure 13 is adjacent to the metal line 146, which is analogous to the rail line. Furthermore, recessing the parts of the source/drain contact in Na not contacting with the via would have the right part of 186a recessed, which is adjacent to the center rail above 185c). Zang also teaches that the recesses are filled with a low-k dielectric, which separates the source/drain contact from a conductor (146) above it (Zang column 6, lies 60-62, and Zang column 7, lines 43-46).
Therefore, it would have obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the second source/drain contact also have a recess as in Zang, in order to electrically separate the contact from other electrical parts above the contact.
Claims 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Na in view of Zang.
In regards to claim 18, Na discloses a semiconductor device, comprising: a first active pattern extending in a first direction across an underlying substrate (110 in Na figure 1 extends in direction D1 across substrate 100); a gate structure extending in a second direction intersecting the first direction, on the first active pattern (gate 120 is on active pattern 110 and extends in direction D2 intersecting D1); a first source/drain region in the first active pattern, on both sides of the gate structure (source/drain region 150 in Na figures 23 and 24, which are on both sides of gate 120); a first interlayer insulating film covering the gate structure and the first source/drain region, on the substrate (145 in Na figure 4 and 5); a first source/drain contact (185 in Na figure 1 and 24) that penetrates through the first interlayer insulating film (see figure 5) on one side of the gate structure (left side in figure 1), and is electrically connected to the first source/drain region (electrically connected to 150 in figure 24); a second source/drain contact that penetrates through the first interlayer insulating film on the other side of the gate structure (top 186/186a in Na figure 1 and 23), and is electrically connected to the first source/drain region (connected to 150 in Na figure 23); an etch stop layer covering an upper surface of the first interlayer insulating film, an upper surface of the first source/drain contact, and an upper surface of the second source/drain contact (197 in figures 4, 23, and 24); a second interlayer insulating film on the etch stop layer (192 in Na figure 23 and 24); a first via pattern that penetrates through the etch stop layer and the second interlayer insulating film, and is electrically connected to the upper surface of the first source/drain contact (via 207 on right side of Na figure 24); a second via pattern that penetrates through the etch stop layer and the second interlayer insulating film, and is electrically connected to the upper surface of the second source/drain contact (via 207 on top of 186a in Na figure 23); a first rail pattern extending in the first direction on the etch stop layer (206 on left side of Na figures 23 and 24); and a first power wiring that extends in the first direction on the second interlayer insulating film (211 in Na figure 24, which extends at least partially in the first direction), and is electrically connected to an upper surface of the first rail pattern (electrically connected through vias 212); wherein the first via pattern is spaced apart from the first rail pattern in the second direction (right via 207 in Na figure 24 is separated from left rail 206); wherein the second via pattern is connected to a side surface of the first rail pattern (sides of 206 in figure 23 are connected to the sides of via pattern 207); wherein the first source/drain contact includes a first recess, which is recessed more downwardly than the upper surface of the first source/drain contact (areas between 185PP and 185LP, see annotations in figure 24);
Na does not expressly disclose that the second source/drain contact includes a recess.
Zang teaches several source/drain contacts with recesses, thus teaching that the second source/drain contact includes a second recess, which is recessed more downwardly than the upper surface of the second source/drain contact (124 in Zang figure 13 has recess filled with insulating layer 132). Zang also teaches that the recesses are filled with a low-k dielectric, which separates the source/drain contact from a conductor (146) above it (Zang column 6, lies 60-62, and Zang column 7, lines 43-46).
Therefore, it would have obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the second source/drain contact also have a recess as in Zang, in order to electrically separate the contact from other electrical parts above the contact.
In regards to claim 19, Na in view of Zang teaches all of the limitations of claim 18. Na further discloses a second active pattern (210 in Na figure 1) extending in the first direction on the substrate and spaced apart from the first active pattern in the second direction (210 extends in the first direction D1 and is spaced apart from 110 in the second direction D2); a second source/drain region in the second active pattern on both sides of the gate structure (250 in Na figure 23 and 24, which is on both sides of the gate 210); a third source/drain contact that penetrates through the first interlayer insulating film on the other side of the gate structure (186b in Na figures 1 and 23), and is electrically connected to the second source/drain region (186b is connected to 250); a third via pattern that penetrates through the etch stop layer and the second interlayer insulating film, and is electrically connected to an upper surface of the third source/drain contact (207 on top of 186b in Na figure 23); a second rail pattern extending in the first direction on the etch stop layer (206 on the right side of Na figure 23 and 24, which extends in direction D1); and a second power wiring extending in the first direction on the second interlayer insulating film, and electrically connected to an upper surface of the second rail pattern (211 in Na figure 23, which extends at least partially in the first direction and is separate from the wiring 211 in figure 24); and wherein the third via pattern is electrically connected to a side surface of the second rail pattern (sides of second rail 206 are connected to the sides of third via pattern 207 above 186b).
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Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Na in view of Zang as applied to claim 19 above, and further in view of Lee et al. (US 20220393030 A1), hereinafter referred to as "Lee".
In regards to claim 20, Na in view of Zang teaches all of the limitations of claim 19. Neither Na nor Zang explicitly teaches what voltages the power wirings provide.
Lee teaches power wirings where the first power wiring is configured to provide a first power voltage (first rail 10 can provide power supply voltage Vdd, Lee paragraph 0053), and the second power wiring is configured to provide a second power voltage different from the first power voltage (second rail 20 can provide ground voltage Vss, Lee paragraph 0053). Lee also teaches that these are part of a standard cell, and provide voltages to make said cell function (Lee abstract and paragraphs 0043 -0045. Moreover, it is known in art that reference voltages are required for a standard cell).
Therefore, it would have obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the power wirings be configured to provide different voltages as in Lee in order to apply the invention to any kind of standard cell.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL K ELLIOTT whose telephone number is (571)357-4606. The examiner can normally be reached Mon-Fri 8:00 -5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at 408-918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL KURT ELLIOTT/ Examiner, Art Unit 2899
/Brent A. Fairbanks/ Supervisory Patent Examiner, Art Unit 2899
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