Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 28-March-2024 was filed on the mailing date of the instant application. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 6-7, and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Patent Publication 20160300625 (Kim).
Regarding claim 1 –
Kim teaches (a) semiconductor apparatus comprising: a data alignment circuit configured to align data input through a data input/output pad, of a plurality of data input/output pads, (Fig 2) plus “A tester 510 may be electrically coupled to either the first input/output pad array 410” (Page 2, Paragraph [0039]).
Kim also teaches and to generate a plurality of alignment data; (Fig 4, Item 235) plus “the write circuit unit 231 may include a buffer 233, an alignment section 235, an inversion section 237, and a latch section 238” (Page 3, Paragraph [0077]) plus “The alignment section 235 may align the output signal of the buffer 233, that is, serial data, as parallel data” (Page 3, Paragraph [0079]).
In addition, Kim teaches and a data pattern control circuit configured to generate preliminary write data by copying bits of a first alignment data to at least one input paths, which are electrically coupled to corresponding ones of the plurality of data input/output pads, (Fig 4, Item 238) plus “the write circuit unit 231 may include a buffer 233, an alignment section 235, an inversion section 237, and a latch section 238” (Page 3, Paragraph [0077]).
Kim also teaches and the data pattern control circuit being additionally configured to change a pattern of the plurality of preliminary write data according to remaining bits of the first alignment data, (Fig 4, Item 237) plus “The inversion section 237 may invert the output signal of the alignment section 235 and output a resultant signal, in the example where the first test mode signal TM_A is enabled.” (Page 3, Paragraph [0080]).
Regarding claim 2 –
Kim teaches all the limitations of claim 1 above.
Kim also teaches wherein the data alignment circuit is configured to output alignment data among the plurality of alignment data, which is corresponding to a first data input/output pad of the plurality of data input/output pads, as the first alignment data, “The semiconductor apparatus may include a first data processing block electrically coupled between a first input/output pad array and a first memory array. The semiconductor apparatus may include a second data processing block electrically coupled between a second input/output pad array and a second memory array” (Page 1, Paragraph [0016]).
Regarding claim 3 –
Kim teaches all the limitations of claim 1 above.
Kim also teaches wherein the data pattern control circuit is configured to generate the write data by inverting data bits of each of the preliminary write data according to remaining bits of the first alignment data in response to activation of a test mode signal, (Fig 4, Item 237) plus “The inversion section 237 may invert the output signal of the alignment section 235 and output a resultant signal, in the example where the first test mode signal TM_A is enabled.” (Page 3, Paragraph [0080]).
Regarding claim 4 –
Kim teaches all the limitations of claim 3 above.
Kim also teaches wherein the data pattern control circuit is configured to output the plurality of alignment data as the write data without changing the pattern in response to de-activation of the test mode signal, (Fig 4, Item 237) plus “The inversion section 237 may invert the output signal of the alignment section 235 and output a resultant signal, in the example where the first test mode signal TM_A is enabled.” (Page 3, Paragraph [0080]).
Regarding claim 6 –
Kim teaches all the limitations of claim 1 above.
Kim also teaches wherein the data pattern control circuit is configured to generate the plurality of write data by inverting each of the plurality of preliminary write data according to the remaining bits of the first alignment data, (Fig 4, Item 237) plus “The inversion section 237 may invert the output signal of the alignment section 235 and output a resultant signal, in the example where the first test mode signal TM_A is enabled.” (Page 3, Paragraph [0080]).
Regarding claim 7 –
Kim teaches (a) semiconductor apparatus comprising: a data alignment circuit configured to align data input through at least one of a plurality of data input/output pads to generate a plurality of alignment data; (Fig 4, Item 235) plus “the write circuit unit 231 may include a buffer 233, an alignment section 235, an inversion section 237, and a latch section 238” (Page 3, Paragraph [0077]) plus “The alignment section 235 may align the output signal of the buffer 233, that is, serial data, as parallel data” (Page 3, Paragraph [0079]).
Kim also teaches a plurality of data pattern control units configured to generate a plurality of preliminary write data, (Fig 4, Item 238) plus “the write circuit unit 231 may include a buffer 233, an alignment section 235, an inversion section 237, and a latch section 238” (Page 3, Paragraph [0077]).
In addition, Kim teaches by copying, in response to activation of a test mode signal, burst bits in order 0th to Mth (where, M is a natural number) of a first alignment data among the plurality of alignment data to a plurality of input paths coupled to the plurality of data input/output pads one bit at a time, “The copy unit 600 may copy the data transmitted through the first global input/output line group GIO<0:63> in response to a second test mode signal TM_COPY” (Page 3, Paragraph [0073]) plus “The alignment section 235 may align the output signal of the buffer 233, that is, serial data, as parallel data” (Page 3, Paragraph [0079]).
Kim also teaches configured to invert a pattern of the plurality of preliminary write data according to burst bits in order (M+1)th to Nth (where, N is a natural number)of the first alignment data to generate a plurality of write data, (Fig 4, Item 237) plus “The inversion section 237 may invert the output signal of the alignment section 235 and output a resultant signal, in the example where the first test mode signal TM_A is enabled.” (Page 3, Paragraph [0080]).
Regarding claim 10 –
Kim teaches (a) semiconductor system comprising: a host configured to output a first data; (Fig 2, Item 510 “Tester”) plus “A tester 510 may be electrically coupled to either the first input/output pad array 410 or the second input/ output pad array 420” (Page 2, Paragraph [0039]).
Kim also teaches a semiconductor apparatus configured to receive the first data through a first data input/output pad of a plurality of data input/output pads to generate a first alignment data including a test source data, “the tester 510 provides a write command, test data and the control signal DQS to the semiconductor apparatus” (Page 2, Paragraph [0044]).
In addition, Kim teaches a pattern control signal for determining whether to invert the test source data, generate a plurality of write data based on the first alignment data and write the plurality of write data in a memory region, and adjust a pattern of the plurality of write data during the generating of the plurality of write data, (Fig 4, Item 237 “Inversion section” plus GIO <0:63> outputs) plus “The inversion section 237 may invert the output signal of the alignment section 235 and output a resultant signal, in the example where the first test mode signal TM_A is enabled.” (Page 3, Paragraph [0080]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 5 is are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Publication 20160300625 (Kim), in view of U.S. Patent Publication 20210279129 (Lee et al.) [herein “Lee”].
Regarding claim 5 –
Kim teaches all the limitations of claim 1 above.
Kim does not teach wherein the data pattern control circuit is configured to generate the plurality of preliminary write data by copying the bits of the first alignment data to the plurality of input paths one bit at a time.
Lee, however teaches wherein the data pattern control circuit is configured to generate the plurality of preliminary write data by copying the bits of the first alignment data to the plurality of input paths one bit at a time, “In accordance with another embodiment of the present invention, a method for operating a memory device includes: converting parallel read data that are read from a plurality of memory cells into serial data to be provided to an input/output pad” (Page 1, Paragraph [0008]); Examiner notes that serial data is inherently processed “one bit at a time”.
Kim and Lee are analogous art because they are both directed to advanced methods of semiconductor testing in a test system environment. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the test architecture in a test environment utilizing input/output pad arrays of Kim with the teachings regarding output data format of Lee, since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, and one of the ordinary skill in the art would have recognized that the results of this combination would provide a predictable result of a semiconductor test circuitry which outputs data serially to test pads.
Claims 8-9 and 11-16 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Publication 20160300625 (Kim), in view of U.S. Patent Publication 20170140840 (Shin).
Regarding claim 8 –
Kim teaches all the limitations of claim 7 above.
Kim does not teach wherein each of the plurality of data pattern control units is configured to transmit alignment data to an input path of the plurality of input paths in response to de-activation of the test mode signal.
Shin, however teaches wherein each of the plurality of data pattern control units is configured to transmit alignment data to an input path of the plurality of input paths in response to de-activation of the test mode signal, “when the test mode signal is deactivated, the MUX outputs first to M-th data signals as the first to M-th internal data signals” (Page 7, Paragraph [0090]).
Kim and Shin are analogous art because they are both directed to advanced methods of semiconductor testing in a test system environment. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the test architecture in a test environment utilizing input/output pad arrays of Kim with the teachings control of output based on test mode signals of Shin, since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, and one of the ordinary skill in the art would have recognized that the results of this combination would provide a predictable result of a semiconductor test circuitry which outputs data selectively to test pads.
Regarding claim 9 –
Kim teaches all the limitations of claim 7 above.
Kim does not teach wherein each of the plurality of data pattern control units comprises: a first multiplexer configured to output, according to the test mode signal, one of a burst bit of alignment data corresponding thereto among the plurality of alignment data and a burst bit of the first alignment data, nor does it teach a logic gate configured to invert and output an output of the first multiplexer, a second multiplexer configured to output one of the output of the first multiplexer and an output of the logic gate according to one of the burst bits in order (M+1)th to Nth of the first alignment data; and a third multiplexer configured to output one of the output of the first multiplexer and an output of the second multiplexer according to the test mode signal.
Shin, however teaches wherein each of the plurality of data pattern control units comprises: a first multiplexer configured to output, according to the test mode signal, one of a burst bit of alignment data corresponding thereto among the plurality of alignment data and a burst bit of the first alignment data, “when the test mode signal is deactivated, the MUX outputs first to M-th data signals as the first to M-th internal data signals” (Page 7, Paragraph [0090]).
Shin also teaches a logic gate configured to invert and output an output of the first multiplexer, a second multiplexer configured to output one of the output of the first multiplexer and an output of the logic gate according to one of the burst bits in order (M+1)th to Nth of the first alignment data; and a third multiplexer configured to output one of the output of the first multiplexer and an output of the second multiplexer according to the test mode signal, “a data modifier configured to invert the (1, 1) to (M, N) deserialized signals to generate (1, 1) to (M, N) bit line signals in response to an inversion control signal and the data modifying signals” (Page 7, Paragraph [0090]).
Kim and Shin are analogous art because they are both directed to advanced methods of semiconductor testing in a test system environment. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the test architecture in a test environment utilizing input/output pad arrays of Kim with the teachings control of output based on test mode signals of Shin, since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, and one of the ordinary skill in the art would have recognized that the results of this combination would provide a predictable result of a semiconductor test circuitry which outputs data selectively to test pads.
Regarding claim 11 –
Kim teaches all the limitations of claim 10 above.
Kim also teaches wherein the semiconductor apparatus comprises: an input/output pad unit including the plurality of data input/output pads, (Fig 2) plus “A tester 510 may be electrically coupled to either the first input/output pad array 410” (Page 2, Paragraph [0039]).
In addition, Kim teaches a memory core including the memory region, Kim – (Fig 2, Items 110 “First memory array” and 120 “Second memory array”).
Kim also teaches a data alignment circuit configured to align data including the first data input through each of the plurality of data input/output pads and generate a plurality of alignment data including the first alignment data; (Fig 4, Item 235) plus “the write circuit unit 231 may include a buffer 233, an alignment section 235, an inversion section 237, and a latch section 238” (Page 3, Paragraph [0077]) plus “The alignment section 235 may align the output signal of the buffer 233, that is, serial data, as parallel data” (Page 3, Paragraph [0079]).
Additionally, Kim teaches a plurality of data pattern control units configured to generate a plurality of preliminary write data, (Fig 4, Item 238) plus “the write circuit unit 231 may include a buffer 233, an alignment section 235, an inversion section 237, and a latch section 238” (Page 3, Paragraph [0077]).
Kim also teaches by copying, in response to activation of a test mode signal, burst bits in order 0th to Mth (where, M is a natural number) corresponding to the test source data of the first alignment data to a plurality of input paths by one bit, “The copy unit 600 may copy the data transmitted through the first global input/output line group GIO<0:63> in response to a second test mode signal TM_COPY” (Page 3, Paragraph [0073]) plus “The alignment section 235 may align the output signal of the buffer 233, that is, serial data, as parallel data” (Page 3, Paragraph [0079]).
Kim does not teach invert the plurality of preliminary write data according to burst bits in order (M+1)th to Nth (where, N is a natural number) corresponding to the pattern control signal of the first alignment data to generate the plurality of write data, and write the plurality of write data to the memory core.
Shin, however teaches invert the plurality of preliminary write data according to burst bits in order (M+1)th to Nth (where, N is a natural number) corresponding to the pattern control signal of the first alignment data to generate the plurality of write data, and write the plurality of write data to the memory core, “a data modifier configured to invert the (1, 1) to (M, N) deserialized signals to generate (1, 1) to (M, N) bit line signals in response to an inversion control signal and the data modifying signals” (Page 7, Paragraph [0090]).
Kim and Shin are analogous art because they are both directed to advanced methods of semiconductor testing in a test system environment. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the test architecture in a test environment utilizing input/output pad arrays of Kim with the teachings control of output based on test mode signals of Shin, since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, and one of the ordinary skill in the art would have recognized that the results of this combination would provide a predictable result of a semiconductor test circuitry which outputs data selectively to test pads.
Regarding claim 12 –
The combination of Kim and Shin teaches all the limitations of claim 11 above.
Kim also teaches wherein the input/output pad unit further comprises a plurality of pads configured to receive commands, addresses, and clock signals, and configured to transmit and receive error detection codes, (Fig 2) plus “A tester 510 may be electrically coupled to either the first input/output pad array 410” (Page 2, Paragraph [0039]) plus “the tester 510 provides a write command, test data and the control signal DQS to the semiconductor apparatus 100 with predetermined timing” (Page 2, Paragraph [0044]) plus “The storage unit 800 may latch the output of the comparison unit 700 according to a third test mode signal TM_LAT, and output the latched output to an exterior of the semiconductor apparatus 100 through the first input/output pad array 410” Page 2, Paragraph [0042]).
Regarding claim 13 –
The combination of Kim and Shin teaches all the limitations of claim 11 above.
Kim also teaches wherein the data alignment circuit is configured to generate the plurality of alignment data according to multi-phase signals, “The shift section 930 may shift the write command signal WT_CMD by the write latency WL based on the clock signal CLK, and output the third control signal DINCLK” (Page 4, Paragraph [0101]).
Regarding claim 14 –
The combination of Kim and Shin teaches all the limitations of claim 13 above.
Kim also teaches further comprising: a clock buffer configured to receive a clock signal, and a dividing circuit configured to divide an output of the clock buffer to generate the multi-phase signals, “The shift section 930 may shift the write command signal WT_CMD by the write latency WL based on the clock signal CLK, and output the third control signal DINCLK” (Page 4, Paragraph [0101]).
Regarding claim 15 –
The combination of Kim and Shin teaches all the limitations of claim 11 above.
Shin also teaches wherein each of the plurality of data pattern control units is configured to write alignment data corresponding to thereto among the plurality of alignment data to the memory core as it is in response to de-activation of the test mode signal, “when the test mode signal is deactivated, the MUX outputs first to M-th data signals as the first to M-th internal data signals” (Page 7, Paragraph [0090]).
Regarding claim 16 –
The combination of Kim and Shin teaches all the limitations of claim 11 above.
Shin also teaches wherein each of the plurality of data pattern control units comprises: a first multiplexer configured to output, according to the test mode signal, one of burst bits of alignment data corresponding thereto among the plurality of alignment data and a burst bit of the first alignment data, “when the test mode signal is deactivated, the MUX outputs first to M-th data signals as the first to M-th internal data signals” (Page 7, Paragraph [0090]).
Additionally, Shin teaches a logic gate configured to invert and output an output of the first multiplexer, a second multiplexer configured to output one of the output of the first multiplexer and an output of the logic gate according to one of the burst bits in order (M+1)th to Nth of the first alignment data; and a third multiplexer configured to output one of the output of the first multiplexer and an output of the second multiplexer according to the test mode signal, “a data modifier configured to invert the (1, 1) to (M, N) deserialized signals to generate (1, 1) to (M, N) bit line signals in response to an inversion control signal and the data modifying signals” (Page 7, Paragraph [0090]).
Conclusion
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/M.W.W./Examiner, Art Unit 2111
/MARK D FEATHERSTONE/Supervisory Patent Examiner, Art Unit 2111