DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
2. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 4/6/26 has been entered.
Claim Rejections - 35 USC § 103
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 1, 2, 8, 9, 15, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Gittins (US Publication Number 2018/0129620) in view of Solihin (US Publication Number 2014/0281058).
5. As per claims 1, 8, 15, Gittins teaches an integrated circuit, method, and system comprising: a plurality of buffers configured to store data (plurality of buffers, paragraph 43), wherein each of the plurality of buffers (associated with MMU, paragraphs 43 and 97) is assigned to an address space of a plurality of address spaces (associated address space, paragraphs 44); and a direct memory access circuit (PDMA unit, paragraphs 8 and 55) is configured to generate a first memory request to retrieve first data from system memory (paragraphs 59, memory store request access).
Gittins does not appear to explicitly disclose a system memory different from the plurality of buffers; circuitry configured to cause the first data received from the system memory to be stored in a first buffer of the plurality of buffers, wherein the first buffer is identified based on an address space assigned to the first buffer including a target address of the first memory request.
However, Solihin discloses a system memory different from the plurality of buffers (150/154 different memory, figure 2); circuitry (162, figure 2) configured to cause the first data received from the system memory to be stored in a first buffer of the plurality of buffers (paragraphs 21 and 22), wherein the first buffer is identified (application identifier 122, figure 2, paragraph 22) based on an address space assigned to the first buffer including a target address of the first memory request (mapped region 156 comprised of 124/126, figure 2, paragraphs 21 – 24).
Gittins and Solihin are analogous art because they are from the same field of endeavor of request handling.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Gittins and Solihin before him or her, to modify the memory subsystem of Gittins to include the structured memory architecture of Solihin because it would allow for more identifiable mapping.
One of ordinary skill would be motivated to make such modification in order to enhance coherence in a memory system (paragraph 2). Therefore, it would have been obvious to combine Solihin with Gittin to obtain the invention as specified in the instant claims.
6. Gittins modified by the teachings of Solihin as seen in claim 1 above, as per claims 2, 9, 16, Gittins teaches an integrated circuit, method, and system, further comprising a plurality of processing circuits, each configured to generate memory requests targeting data stored in any of the plurality of buffers (plurality of processors, paragraph 11, buffer targets, paragraphs 56 – 61).
Allowable Subject Matter
7. Claims 3 - 7, 10 - 14, 17-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
8. Applicant’s arguments with respect to claims 1 – 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument in view of Solihin.
Conclusion
9. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Ito/Kaminski/Ginzburg/Strongin has teachings of memory management and addressing.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AURANGZEB HASSAN whose telephone number is (571)272-8625. The examiner can normally be reached 7 AM to 3 PM.
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AH
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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