DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claims 1, 2, 8, 9, 15, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Gittins (US Publication Number 2018/0129620) in view of Chen et al. (US Publication Number 2010/0023700, hereinafter “Chen”).
4. As per claims 1, 8, 15, Gittins teaches an integrated circuit, method, and system comprising: a plurality of buffers configured to store data (plurality of buffers, paragraph 43), wherein each of the plurality of buffers (associated with MMU, paragraphs 43 and 97) is assigned to an address space of a plurality of address spaces (associated address space, paragraphs 44); and a direct memory access circuit (PDMA unit, paragraphs 8 and 55) is configured to generate a first memory request to retrieve first data from system memory into a first buffer of the plurality of buffers (paragraphs 59, memory store request access), responsive to the first buffer being assigned to an address space that corresponds to an address space targeted by the first memory request (figure 3, paragraphs 76 – 79 memory request handling corresponding to memory address).
Gittins does not appear to explicitly disclose each of the plurality of buffers is assigned to a different address space; and a system memory, different from the plurality of buffers.
However, Chen discloses each of the plurality of buffers (LS 112…115, figure 1) is assigned to a different address space (LSA different direct address space associated with each buffer LS, paragraph 47, figure 1); and a system memory (global memory 150 and 202, figures 1 and 2), different from the plurality of buffers (global memory independent from the buffers, figures 1 and 2, paragraph 56).
Gittins and Chen are analogous art because they are from the same field of endeavor of DMA handling.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Gittins and Chen before him or her, to modify the memory subsystem of Gittins to include the structured memory architecture of Chen because it would allow for more identifiable mapping.
One of ordinary skill would be motivated to make such modification in order to enhance coherence in a fast memory system (paragraph 4). Therefore, it would have been obvious to combine Chen with Gittin to obtain the invention as specified in the instant claims.
5. Gittins modified by the teachings seen in claim 1 above, as per claims 2, 9, 16, Gittins teaches an integrated circuit, method, and system, further comprising a plurality of processing circuits, each configured to generate memory requests targeting data stored in any of the plurality of buffers (plurality of processors, paragraph 11, buffer targets, paragraphs 56 – 61).
Allowable Subject Matter
6. Claims 3 - 7, 10 - 14, 17-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
7. Applicant’s arguments with respect to claims 1 – 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument in view of Chen.
Conclusion
8. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Achiwa/Barnes/Cho/Danilak/Day/Gopal/Hraden/Kaminski/Lee/Michels/Roozbeh/Sarangam have teachings of DMA associated buffers directly addressing with a system memory.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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AH
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184