Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 17-20 are objected to because of the following informalities:
It is suggested including the term “non-transitory” in the preamble of claims 17-20 for consistency and clarity with independent claim 16.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 9 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9 recites the limitation "a first IO die" and “a second IO die” in line 2.
There is insufficient antecedent basis for this limitation in the claim.
For the purpose of examination it is assumed that the above listed claim elements read “the first IO die” and “the second IO die” respectively.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 7, 11-12, 14, 16-17 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bose et al., US Patent Appl. Pub. No. 2009/0199020 in view of Smith et al., US Patent Appl. Pub. No. 2009/0204835.
Regarding claim 1, Bose discloses an apparatus (FIG. 2) comprising:
a processor (microprocessor 202) comprising:
a first chiplet (chiplet 210) the first chiplet comprising a first processor core (paragraph 0034, lines 1-5) or associated with a first input/output (IO) die; and
a second chiplet (chiplet 220), the second chiplet comprising a second processor core (paragraph 0034, lines 1-5) or associated with a second IO die.
Bose further discloses selectively setting the power levels for each chiplet (Abstract, 18-19, paragraph 0032, lines 7-14), but does not specifically state the apparatus is configured to disconnect the second chiplet from power while providing power to the first chiplet.
Smith teaches a SoC with power domains and independently turning off power for the individual power domains (FIG. 1, power domains 121-123, FIG. 2, 222, paragraph 0010, lines 5-8, paragraph 0024, lines 5-10), each power domain including specific functional blocks (FIG. 2, 222, CPU 232, GPU 233, video processor 235 – i.e. cores within respective CPU, GPU, video processor), wherein only functional blocks needed are turned on and unneeded functional blocks are turned off by powering off corresponding power domain(s) (paragraph 0010, lines 7-11, paragraph 0030, paragraph 0031, lines 5-8, lines 12-13). Smith further teaches an Always On functional block 231 within domain 221, which remains powered while the rest of the SoC (including domain 222) is powered down (FIG, 2, paragraph 0040). In Smith, the above-described functionality optimizes performance verses power consumption by intelligently adjusting power consumption in relation to a requested device functionality (paragraph 0029, lines 1-4). Thus, maximizing the battery life and device usability (paragraph 0032, lines 8-11).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the independent power down for individual power domain (second chiplet), including maintain power for one of the power domains (first chiplet), as suggested by Smith with the apparatus disclosed by Bose in order to implement the apparatus is configured to disconnect the second chiplet from power while providing power to the first chiplet. One of ordinary skill in the art would be motivated to do so in order to optimizes performance verses power consumption, thus, maximizing the battery life and device usability.
Regarding claim 11, Bose discloses a method (FIG. 2) comprising:
providing power to a first chiplet (chiplet 210), the first chiplet comprising a first processor core (paragraph 0034, lines 1-5) or associated with a first input/output (IO) die in a processor, and a second chiplet (chiplet 220), the second chiplet comprising a second processor core (paragraph 0034, lines 1-5) or associated with a second IO die in the processor (providing power to the first and second chiplets is inherently disclosed – changing the power levels separately for each of the chiplets necessarily requires the chiplets being provided with power initially; Abstract, lines 18-19, paragraph 0032, lines 7-10).
Bose further discloses selectively setting the power levels for each chiplet (Abstract, 18-19, paragraph 0032, lines 7-14), but does not specifically state disconnecting the second chiplet from power while maintaining power to the first chiplet.
Smith teaches a SoC with power domains and independently turning off power for the individual power domains (FIG. 1, power domains 121-123, FIG. 2, 222, paragraph 0011, lines 5-8, paragraph 0024, lines 5-10), each power domain including specific functional blocks (FIG. 2, 222, CPU 232, GPU 233, video processor 235 – i.e. cores within respective CPU, GPU, video processor), wherein only functional blocks needed are turned on and unneeded functional blocks are turned off by powering off corresponding power domain(s) (paragraph 0010, lines 7-11, paragraph 0030, paragraph 0031, lines 5-8, lines 12-13). Smith further teaches an Always On functional block 231 within domain 221, which remains powered while the rest of the SoC (including domain 222) is powered down (FIG, 2, paragraph 0040). In Smith, the above-described functionality optimizes performance verses power consumption by intelligently adjusting power consumption in relation to a requested device functionality (paragraph 0029, lines 1-4). Thus, maximizing the battery life and device usability (paragraph 0032, lines 8-11).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the independent power down for individual power domain (second chiplet), including maintain power for one of the power domains (first chiplet), as suggested by Smith with the method disclosed by Bose in order to implement disconnecting the second chiplet from power while maintaining power to the first chiplet. One of ordinary skill in the art would be motivated to do so in order to optimizes performance verses power consumption, thus, maximizing the battery life and device usability.
Regarding claim 16, Bose further teaches a non-transitory computer readable medium embodying a set of executable instructions, the set of executable instructions to manipulate at least one processor (FIG. 1, 120, paragraphs 0025-0026) to perform all claim limitations, as addressed above for claim 11.
Regarding claim 2, Smith further teaches the apparatus, further comprising a power rail connected to the second chiplet (FIG. 2, 262), wherein disconnecting the second chiplet from power includes disconnecting the power rail from power (paragraph 0011, lines 5-8, paragraph 0039, lines 6-8, paragraph 0040, lines 13-15, paragraph 0056, lines 6-9).
Regarding claims 12 and 17, Smith further teaches the method and non-transitory computer readable medium, wherein the disconnecting includes disconnecting a power rail connected to the second chiplet from power (paragraph 0011, lines 5-8, paragraph 0039, lines 6-8, paragraph 0040, lines 13-15, paragraph 0056, lines 6-9).
Regarding claim 3, the combination of Bose with Smith, further teaches the apparatus, further comprising a hypervisor (Bose, initiating the power level change from hypervisor firmware – FIG, 308, paragraph 0056, lines 7-9) configured to initiate the disconnecting (Smith, paragraph 0010, lines 7-11, paragraph 0011, lines 5-8, paragraph 0024, lines 5-10, paragraph 0030, paragraph 0031, lines 5-8, lines 12-13, paragraph 0040).
Regarding claim 4, the combination of Bose with Smith, further teaches the apparatus, further comprising firmware (Bose, initiating the power level change from hypervisor firmware – FIG, 308, paragraph 0056, lines 7-9) configured to initiate the disconnecting (Smith, paragraph 0010, lines 7-11, paragraph 0011, lines 5-8, paragraph 0024, lines 5-10, paragraph 0030, paragraph 0031, lines 5-8, lines 12-13, paragraph 0040).
Regarding claim 5, Bose further teaches the apparatus, as per claim 4, wherein the firmware provides a hypervisor with an indication of the disconnecting (inherently disclosed – the hypervisor firmware must necessarily indicate to the hypervisor itself the action for changing the power level; paragraph 0056, lines 7-9, FIG. 8, 804-NO, 808, paragraph 0084, lines 8-15).
Regarding claims 7, 14, and 19, Smith further teaches the apparatus, method and non-transitory computer readable medium, further comprising reconnecting the second chiplet to power based on a wake condition (FIG. 2, paragraph 0040, FIG. 5, 504, paragraph 0059).
Claim(s) 6, 8, 13 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bose et al., US Patent Appl. Pub. No. 2009/0199020 in view of Smith et al., US Patent Appl. Pub. No. 2009/0204835, and further in view of Ahmad et al., US Patent Appl. Pub. No. 2014/0059548.
Regarding claims 6, 13, and 18, Bose and Smith disclose the apparatus, method, and non-transitory computer readable medium as per claims 1, 11, and 16, respectively. Regarding claim 8, Bose and Smith disclose the apparatus as per claim 7.
With respect to claims 6, 13,and 18, Bose and Smith do not specifically state migrating threads from the second processor core to the first processor core prior to the disconnecting.
With respect to claim 8, Bose and Smith do not specifically state the wake condition includes a threshold associated with a number of active processor cores or a number of active threads.
Ahmad teaches an integrated circuit (FIG. 2, 200) including multi-core cluster 205 and a single-core cluster 210, wherein upon migrating the processes/threads from a given core in the multi-core cluster to the core in the single-core cluster, the core from where the threads were migrated from is power gated (paragraph 0004, lines 23-35, FIG. 2, paragraph 0018, lines 7-12, FIG(s) 3A-B, 305, 325, 330, paragraph 0020, lines 1-3, paragraph 0021, lines 17-22, paragraph 0022, lines 1-5, lines 10-12). Ahmad further teaches initiating reverse thread migration from the core in the single-core cluster back to the original core in the multi-core cluster (after re-powering/wakeup) based on the current processing utilization (the number of active treads) of the core in the single-core cluster increasing above 80% range/threshold (paragraph 0004, FIG. 3, 335, 340, 345, 350, paragraph 0023, lines 18, paragraph 0024, lines 1-9, lines 15-20, paragraph 0025, lines 1-5, lines 10-16). Accordingly, threads executing on any one of a plurality of cores in the multi-core cluster are migrated to a core of a separate cluster without first having to transfer the processes to a predetermined core of the multi-core cluster and back (Abstract, paragraph 0002, lines 10-16). Thus, improving the processing performance (paragraph 0002, lines 16-21, paragraph 0029, lines 1-4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the above-described integrated circuit and functionality, as suggested by Ahmad with the apparatus, method, and non-transitory computer readable medium disclosed by Bose and Smith in order to implement migrating threads from the second processor core to the first processor core prior to the disconnecting and the wake condition includes a threshold associated with a number of active processor cores or a number of active threads. One of ordinary skill in the art would be motivated to do so in order to improve the processing performance.
Allowable Subject Matter
Claims 10, 15 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 9 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEFAN STOYNOV whose telephone number is (571)272-4236. The examiner can normally be reached 8AM - 4:30PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew J Jung can be reached at 571-270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/STEFAN STOYNOV/Primary Examiner, Art Unit 2175