DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Khlat et al. (US 2019/0319584).
In regard to Claim 15:
Khlat discloses, in Figure 2, an envelope tracking modulator, comprising:
a linear amplification circuit (46);
a coupling capacitor (52);
a buck circuit (66);
a circuit sensor (58); and
an offset current generation circuit (54), wherein:
an output end of the linear amplification circuit (46 output) is coupled to a first end (58 end) of the coupling capacitor (52), and a second end (60 end) of the coupling capacitor (52) is coupled to a power supply node (44);
the offset current generation circuit (54) is coupled to the first end (58 end) and the second end (60 end) of the coupling capacitor (52), and the offset current generation circuit (54) is further coupled to a control end of the buck circuit (66);
an input end of the circuit sensor (58) is coupled to a line between the output end of the linear amplification circuit (46 output) and the first end of the coupling capacitor (58 end of 52), and an output end of the circuit sensor (58) is coupled to the control end of the buck circuit (66 via 54 and 64);
an output end of the buck circuit (66) is coupled to the power supply node (44);
the offset current generation circuit (54) is configured to generate an offset current based on an amplified voltage output by the linear amplification circuit (46) and a power supply voltage output (Vcc) by the power supply node (44, ¶ 0038); and
the buck circuit (66) is configured to generate a first output voltage based on a sum of the offset current (54 output) and an induced current output by the circuit sensor (58 output, ¶ 0047), wherein:
when a difference between the power supply voltage (66) and the amplified voltage (46 output) is less than a reference voltage (Vtarget), the sum of the offset current and the induced current is greater than the induced current (¶ 0044); or
when the difference between the power supply voltage (Vcc) and the amplified voltage (46 output) is greater than the reference voltage (Vtarget), the sum of the offset current and the induced current is less than the induced current (¶ 0045-0046).
Allowable Subject Matter
Claims 16-26 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
In regard to Claim 16:
None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims:
the offset current generation circuit comprises a voltage detector and an offset current generator; a positive input end of the voltage detector is coupled to the first input end of the offset current generation circuit; a negative input end of the voltage detector is coupled to the second input end of the offset current generation circuit; an output end of the voltage detector is coupled to an input end of the offset current generator; an output end of the offset current generator is coupled to the output end of the offset current generation circuit; the voltage detector is configured to: determine a result of comparing the difference between the power supply voltage and the amplified voltage with the reference voltage; and generate an offset control voltage based on the result of the comparing.
Khlat discloses, in Figure 5, wherein: a first input end of the offset current generation circuit (54) is coupled to the first end of the coupling capacitor (58 end of 52); a second input end of the offset current generation circuit (54) is coupled to the second end of the coupling capacitor (60 end of 52); an output end of the offset current generation circuit (54) is coupled to the control end of the buck circuit (66); and the offset current generator (54) is configured to: generate the offset current based on the offset control voltage (¶ 0031).
In regard to Claim 19:
None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims:
wherein: the buck circuit comprises a driver, a third switch, a fourth switch, and an inductor; an input end of the driver is coupled to the control end of the buck circuit; a first output end of the driver is coupled to a control end of the third switch; a second output end of the driver is coupled to a control end of the fourth switch; a first end of the third switch is coupled to a battery voltage; a second end of the third switch is coupled to a first end of the fourth switch; a second end of the fourth switch is coupled to a ground; and the second end of the third switch is further coupled to the output end of the buck circuit through the inductor.
In regard to Claim 20:
None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims:
wherein: the envelope tracking modulator further comprises a current adder; the offset current generation circuit is coupled to the control end of the buck circuit through the current adder; and the output end of the circuit sensor is coupled to the control end of the buck circuit through the current adder.
In regard to Claim 26:
None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims:
the coupling capacitor is configured to: filter out a low-frequency component and a direct current component in the amplified voltage; generate a second output voltage; and transmit the second output voltage to the power supply node; and wherein the circuit sensor is configured to: detect the amplified voltage to generate; and output the induced current; and the power supply node is configured to output the power supply voltage based on the first output voltage and the second output voltage.
However, Khlat discloses, in Figure 2, wherein: to generate the amplified voltage (Vparamp), the linear amplification circuit (46) is configured to amplify an envelope signal (Vtarget) received by the envelope tracking modulator (38).
Claims 27-34 are allowed.
In regard to Claim 27:
None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims:
a processing circuit; wherein the processing circuit is configured to generate a radio frequency signal and an envelope signal of the radio frequency signal based on to-be-sent data; and the at least one envelope tracking modulator is configured to generate a power supply voltage of a power amplifier based on the envelope signal.
However, Khlat discloses, in Figure 2, an envelope tracking modulator, comprising:
a linear amplification circuit (46);
a coupling capacitor (52);
a buck circuit (66);
a circuit sensor (58); and
an offset current generation circuit (54), wherein:
an output end of the linear amplification circuit (46 output) is coupled to a first end (58 end) of the coupling capacitor (52), and a second end (60 end) of the coupling capacitor (52) is coupled to a power supply node (44);
the offset current generation circuit (54) is coupled to the first end (58 end) and the second end (60 end) of the coupling capacitor (52), and the offset current generation circuit (54) is further coupled to a control end of the buck circuit (66);
an input end of the circuit sensor (58) is coupled to a line between the output end of the linear amplification circuit (46 output) and the first end of the coupling capacitor (58 end of 52), and an output end of the circuit sensor (58) is coupled to the control end of the buck circuit (66 via 54 and 64);
an output end of the buck circuit (66) is coupled to the power supply node (44);
the offset current generation circuit (54) is configured to generate an offset current based on an amplified voltage output by the linear amplification circuit (46) and a power supply voltage output (Vcc) by the power supply node (44, ¶ 0038); and
the buck circuit (66) is configured to generate a first output voltage based on a sum of the offset current (54 output) and an induced current output by the circuit sensor (58 output, ¶ 0047), wherein:
when a difference between the power supply voltage (66) and the amplified voltage (46 output) is less than a reference voltage (Vtarget), the sum of the offset current and the induced current is greater than the induced current (¶ 0044); or
when the difference between the power supply voltage (Vcc) and the amplified voltage (46 output) is greater than the reference voltage (Vtarget), the sum of the offset current and the induced current is less than the induced current (¶ 0045-0046).
It would not have been obvious to one having ordinary skill in the art to combine any prior art to teach or fairly suggest the features not disclosed by Khlat.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Khlat (US 2020/0382066) discloses an envelope tracking integrated circuit having a tracker circuitry configured to generate a modulated supply voltage for a radio frequency power amplifier in response to an envelope of a radio frequency signal to be amplified by the radio frequency power amplifier.
Khlat (US 11,728,774) discloses an average power tracking (APT) power management integrated circuit (PMIC). The APT PMIC is configured to generate an APT voltage to a power amplifier for amplifying a high modulation bandwidth (e.g., ≥200 MHz) radio frequency (RF) signal.
Mirea et al. (US 2021/0194517) discloses an envelope tracking system includes an envelope signal generator, a supply modulator coupled to the envelope signal generator, the supply modulator comprising a switching regulator path configured to provide an output voltage at an output node to a power amplifier when in an average power tracking (APT) mode.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to John W Poos whose telephone number is (571)270-5077. The examiner can normally be reached M-Th 8-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached at 571-272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JOHN W POOS/Primary Examiner, Art Unit 2843
Prosecution Insights