DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1, 3-6, 8-9, 11-13, and 15-20 are pending.
Claims 1, 3-6, 8-9, 11-13, and 19-20 have been amended.
This action is Final.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1, 3-6, 11, 13, and 15-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Omizo et al. (hereinafter as Omizo) PGPUB 2007/0106428, and further in view of Gemini et al. (hereinafter as Gemini) PGPUB 2025/0217181.
As per claim 1, Omizo teaches a multicore processor [0014: multiprocessor unit] comprising:
a plurality of cores [0014: multiple processor cores]; and
a power controller configured to control a power of the multicore processor [0013-0017: (thermal management unit controls power to the processor core when an over-temperature is detected at a processor core)], wherein the power controller is configured to:
process temperature measurement information to identify a plurality of temperature measurements corresponding to the plurality of cores [0042: (there are a plurality of thermal sensors, each thermal sensor corresponding to one of the processor cores); 0045: (information such as the received thermal sensor signals are provided to the thermal management block to evaluate the thermal readings and make appropriate thermal management decisions)];
identify, based on the plurality of temperature measurements, one or more selected cores of the plurality of cores to be thermally-throttled [0045-0046: (thermal management block determines one of the processor cores reaches a threshold temperature, and thus needs to redirect some of the processing load to other cores)], the power controller configured to determine whether a first core of the plurality of cores is to be included in the one or more selected cores based on a comparison between a first temperature measurement corresponding to the first core and a first temperature threshold for the first core [0046: (one of the processor cores reaches a temperature threshold temperature)]; and
trigger thermal throttling of the one or more selected cores, while allowing one or more non-selected cores of the plurality of cores to remain non-thermally-throttled [0046: (if other processor cores have relatively low temperature while one of the cores have a high temperature exceeding the temperature threshold, only the processor core with the high temperature will be throttled by reducing the clock speed while the other cores remain at the normal clock speed)].
Omizo does not explicitly teach determine whether a second core of the plurality of cores is to be included in the one or more selected cores based on a comparison between a second temperature measurement corresponding to the second core and a second temperature threshold for the second core, wherein the second temperature threshold is different from the first temperature threshold. Although Omizo compares a temperature of a core to a threshold, and shows in FIG. 1, circuitry for each thermal sensing element is to be compared to a reference value corresponding to a particular threshold, Omizo does not explicitly indicate whether this reference value (and thus the temperature threshold value) is the same or different for each core.
Gemini teaches determining whether CPU cores remaining below or exceeds a temperature threshold, and take corrective action [0026 and 0033]. Gemini is thus similar to Omizo. Gemini further teaches determine whether a second core of the plurality of cores is to be included in the one or more selected cores based on a comparison between a second temperature measurement corresponding to the second core and a second temperature threshold for the second core [0026, 0033, and 0035: (determines if any CPU cores are determined to exceed a threshold temperature; thus it performs for each core, a comparison of the core temperature with the threshold temperature)], wherein the second temperature threshold is different from the first temperature threshold [0043 and FIG. 5 column 508: (Max temperature threshold for each core may be different)]. Gemini shows that each core may have a different max temperature threshold, and the comparison is performed between each core’s operating temperature and the core’s corresponding max temperature threshold.
The combination of Omizo and Gemini leads to the reference value in each core being different based on the max temperature threshold assigned for each core.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Gemini’s teachings of each core having a different temperature threshold in Omizo. One of ordinary skill in the art would have been motivated to provide a custom temperature threshold for each core instead of a generic temperature threshold for all cores because it allows for greater customization and flexibility, and allows for greater performance by allowing each core to operate up to its true maximum temperature threshold.
As per claim 3, Omizo and Gemini teaches the multicore processor of claim 1, wherein the power controller is configured to determine that the first core is to be included in the one or more selected cores based on a determination that the first temperature measurement corresponding to the first core is higher than the first temperature threshold [Omizo 0046: (determines if one of the processor cores reaches the temperature threshold; i.e. determines if one of the processor cores is at or is higher than the temperature threshold)].
As per claim 4, Omizo and Gemini teaches the multicore processor of claim 1, wherein the power controller is configured to determine that the second core is to be identified as a non-selected core to not be thermally-throttled based on a determination that the second temperature measurement corresponding to the second core is lower than the second temperature threshold [Omizo 0046: (another of the processor cores have a relatively low temperature; i.e. a lower temperature relative to the temperature threshold) and Gemini FIG. 5: (compared to the threshold temperature for a particular core)].
As per claim 5, Omizo and Gemini teaches the multicore processor of claim 1, wherein the first temperature threshold comprises a core-specific temperature threshold corresponding to the first core [Omizo FIG. 1, 0040, 0042, 0052: (temperature thresholds are for cores, and it may be considered a thermal event when a temperature detected by the thermal sensor at a core exceeds a predetermined threshold; thus the core has a core-specific temperature threshold) and Gemini FIG. 5: (Each core has a core specific threshold)].
As per claim 6, Omizo and Gemini teaches the multicore processor of claim 1, wherein the second temperature threshold comprises a multiple-core temperature threshold corresponding to two or more cores of the plurality of cores [Omizo 0052: (it may also be a thermal event when the average of temperatures detected by several thermal sensors (corresponding to several cores) exceed the predetermined threshold; thus there is a multi-core threshold temperature in the form of an average temperature across multiple cores); or Gemini FIG. 5: (some cores have the same second temperature threshold of 130 degrees for example)].
As per claim 11, Omizo and Gemini teach the multicore processor of claim 1, wherein the second temperature threshold comprises a predefined temperature threshold [Omizo 0052: (the thermal events and corresponding temperature thresholds may be predefined) or Gemini FIG. 5: (temperature are predefined in a table)].
As per claim 13, Omizo and Gemini teaches the multicore processor of claim 1, wherein the power controller is configured to: identify the first core as a selected core based on a determination that the first temperature measurement corresponding to the first core is above the first temperature threshold for the first core; identify the second core as a non-selected core based on a determination that the second temperature measurement corresponding to the second core is below the second temperature threshold for the second core; and trigger thermal throttling of the first core, while allowing the second core to remain non-thermally-throttled [Omizo 0046: (one core reached the threshold temperature while another core has a low temperature; the core with the high temperature is throttled while the remaining processor core operate at the normal clock speed)].
As per claim 15, Omizo and Gemini teach the multicore processor of claim 1, wherein the power controller is configured to trigger the thermal throttling of only the one or more selected cores [Omizo 0046: (only the core with temperature reaching the threshold has its frequency reduced while the remaining processor cores operate at normal clock speed)].
As per claim 16, Omizo and Gemini teach the multicore processor of claim 1, wherein the power controller is configured to trigger the thermal throttling of the one or more selected cores by triggering a frequency throttling of the one or more selected cores [Omizo 0046: reduce the clock speed].
As per claim 17, Omizo and Gemini teaches the multicore processor of claim 1, wherein the power controller is configured to trigger the thermal throttling of the one or more selected cores by triggering a voltage throttling of the one or more selected cores [Omizo 0017: (reducing its power supply voltage)].
As per claim 18, Omizo and Gemini teaches the multicore processor of claim 1 comprising a plurality of temperature sensors to provide the plurality of temperature measurements corresponding to the plurality of cores [Omizo FIG. 2, 0036-0040: (each functional block has a thermal sensor; functional blocks are cores)].
Claim 19 is similar in scope to claim 1 as addressed above and is thus rejected under the same rationale. Omizo further teaches at least one memory to store information processed by the multicore processor [0069].
Claim 20 is similar in scope to claim 13 as addressed above and is thus rejected under the same rationale
Claim(s) 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Omizo et al. (hereinafter as Omizo) PGPUB 2007/0106428 and Gemini et al. (hereinafter as Gemini) PGPUB 2025/0217181, and further in view of Ragland et al. (hereinafter as Ragland) PGPUB 2021/0109562.
As per claim 8, Omizo and Gemini teach the multicore processor of claim 1.
Omizo and Gemini does not teach wherein the power controller is configured to identify the first temperature threshold and the second temperature threshold based on a user input from a User Interface (UI). Omizo specifies that the threshold may be programmable [0052] but does not indicate a user interface.
Ragland teaches temperature thresholds for a processor. Ragland is thus similar to Omizo and Gemini. Ragland further teaches wherein the power controller is configured to identify the first temperature threshold and the second temperature threshold based on a user input from a User Interface (UI) [0026 and 0073: (user selected temperature thresholds based on user interface to set a temperature per core); FIG. 9 and 0073: (user can set different thresholds for different cores)].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Ragland’s teachings of user specifying a temperature threshold for cores using a user interface in Omizo and Gemini. One of ordinary skill in the art would have been motivated to allow a user to specify a temperature threshold for cores in Omizo and Gemini because it provides the user with greater control on how to implement power and performance policies in a processor such as for purposes of overclocking, which improves performance.
As per claim 9, Omizo, Gemini, and Ragland teach the multicore processor of claim 8, wherein the power controller is configured to identify, based on the user input, a user-selected threshold setting from a plurality of predefined threshold settings, and to determine the first temperature threshold for the first core based on the user-selected threshold setting [Ragland FIG. 9: (user inputted selection is used to determine thresholds per core)].
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Omizo et al. (hereinafter as Omizo) PGPUB 2007/0106428 and Gemini et al. (hereinafter as Gemini) PGPUB 2025/0217181, and further in view of Narayanaswamy et al. (hereinafter as Narayanaswamy) PGPUB 2024/0094796.
As per claim 12, Omizo and Gemini teaches the multicore processor of claim 1.
Omizo and Gemini does not teach wherein the temperature threshold comprises a maximal Thermal Junction Temperature (Tjmax). Omizo and Gemini mentions a temperature threshold or a max temperature threshold which is considered problematic (Tp), but not that it is a maximum thermal junction temperature.
Narayanaswamy teaches monitoring temperature of processors. Narayanaswamy is thus similar to Omizo and Gemini because they monitor temperatures of processing components and take corrective actions if needed. Narayanaswamy further teaches the temperature threshold comprises a maximal Thermal Junction Temperature (Tjmax) [0062: (maximum operating temperature is based on a maximum thermal junction temperature TJmax that a processor will allow prior to using internal thermal control mechanisms to reduce power and limit temperature)].
The combination of Omizo and Gemini with Narayanaswamy leads to the temperature threshold being set at the thermal junction temperature.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Narayanaswamy’s teachings of a threshold being based on the thermal junction temperature in Omizo and Gemini. One of ordinary skill in the art would have been motivated to set the thermal threshold as the thermal junction temperature in Omizo and Gemini because it is a value that represents a maximum temperature limit of the processor and operating above such temperature would reduce the lifespan of the processor.
Response to Arguments
Applicant’s arguments, see pages 9-12, filed 1/1/2026, with respect to the rejection(s) of claim(s) 1 and 19 under U.S.C. 102(a)(1) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of newly found prior art.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ignowski et al. (PGPUB 2016/0026231) teaches that cores may have corresponding thermal thresholds [0117].
Naffzigger (PGPUB 2012/0066535) teaches that cores may have respective power limits.
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/DANNY CHAN/Primary Examiner, Art Unit 2175