Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
1. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
2. Claims 1-10 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Furuya (Pub. No. US20050073344)
As per claims 1, 10, Furuya discloses a method for timing training on an a Low Voltage Differential Signaling (LVDS) interface (paragraph 57, a receiver circuit (receiver) of a LVDS circuit) comprising:
inputting a Positive-end of the Low Voltage Differential Signaling differential data signal (paragraph 67, the differential signals (a pair of positive (e.g., P-end) signals)) into a first delay chain (paragraph 12, 1st multiple delay circuits are connected in series), and converting the Positive-end of the Low Voltage Differential Signaling differential data signal into first parallel data (paragraph 10, converting the serial data into first parallel data) through serial-to-parallel conversion (paragraph 142, line 4-5, input to serial-parallel converter circuits);
inputting a Negative-end of the Low Voltage Differential Signaling (LVDS)differential data signal (paragraph 67, the differential signals (a pair of negative (e.g., n-end) signals)) into a second delay chain (paragraph 69, line 15, a second parallel circuit), and converting the Negative-end of the Low Voltage Differential Signaling differential data signal into second parallel data (paragraph 10, converting the serial data into second parallel data) through serial-to-parallel conversion (paragraph 142, line 4-5, input to one of serial-parallel converter circuits);
sampling by using the second parallel data as reference data and the first parallel data as scanning data (paragraph 10-11, converting the serial data into parallel data and used that is capable of sampling seven unit data contained in one clock unit forming the serial input data), and collecting the relative position between the sampling position corresponding to the current delay stage (paragraph 16, outputting the delay amount setting signal for causing each of the first to the last stages of the unit delay circuits to delay the phase of an output clock signal by T/2n) and the center of the scanning data window, when the sampling position corresponding to the current delay stage is located at the center of the scanning data window, the current delay stage is recorded as the first delay stage (paragraph 64, the timing resolution of T/(2n) is necessary to place the rising edges of clock signals in the center of respective data bits));
sampling by using the first parallel data as reference data and the second parallel data as scanning data (paragraph 76, The rising edge of the clock signal DL4 is the reference in comparing the phases.), and setting the initial delay stage of the second parallel data as the first delay stage, collecting the relative position between the sampling position corresponding to the current delay stage and the center of the scanning data window, when the sampling position corresponding to the current delay stage is located at the center of the scanning data window, the current first delay stage is recorded as the second delay stage (paragraph 64, generating phases (e.g., windows) that the timing resolution of T/(2n) is necessary to place the rising edges of clock signals in the center of respective data bits));
obtaining the delay stage difference according to the first delay stage and the second delay stage, (paragraph 18, generating a sampling signal that takes a first level between (2m-1)T/2n and mT/n (m is a natural number) based on two or more of the delayed clock signals.) and setting the sum of the first delay stage and half of the delay stage difference as the delay stage of the first parallel data, receiving the LVDS differential data by using the second parallel data as scanning data.(paragraph 77, phase difference)
As per claim 2, Furuya discloses wherein sampling by using the second parallel data as reference data and the first parallel data as scanning data, and collecting the relative position between the sampling position corresponding to the current delay stage and the center of the scanning data window further comprising: sampling by using the second parallel data as reference data after setting the initial delay stage of the first parallel data, and collecting the relative position corresponding to the initial delay stage, wherein the initial delay stage is less than the total delay stage of the first delay chain (paragraph 22, setting signals in accordance with the delay amount control signal and supplying the first and the second delay amount setting signals to the delay circuit);
when the sampling position corresponding to the current initial delay stage is offset to the left relative to the center of the first parallel data window, decreasing the current initial delay stage, and after updating the decreased initial delay stage to the initial delay stage, re-collecting the relative position (paragraph 64, the timing resolution of T/(2n) is necessary to place the rising edges of clock signals in the center of respective data bits));
when the sampling position corresponding to the current initial delay stage is offset to the right relative to the center of the first parallel data window, increasing the current initial delay stage, and after updating the increased initial delay stage to the initial delay stage, re-collecting the relative position(paragraph 10-11, converting the serial data into parallel data and a serial-parallel converter circuit is used that is capable of sampling seven unit data contained in one clock unit forming the serial input data);
when the sampling position corresponding to the current initial delay stage is located at the center of the first parallel data window, the initial delay stage corresponding to the sampling position is taken as the first delay stage (paragraph 88, Note that the base point of the DLL denotes a time point corresponding to an imaginary start position of the DLL).
As per claim 3, Furuya discloses wherein sampling by using the first parallel data as reference data and the second parallel data as scanning data, and setting the initial delay stage of the second parallel data as the first delay stage, collecting the relative position between the sampling position corresponding to the current delay stage and the center of the scanning data window further comprising: scanning is conducted using the first parallel data as reference data after setting the first delay stage as the initial delay stage of the second parallel data, whilst collecting the relative position corresponding to the initial delay stage(paragraph 88, Note that the base point of the DLL denotes a time point corresponding to an imaginary start position of the DLL); when the sampling position corresponding to the current initial delay stage is offset to the left relative to the center of the second parallel data window, decreasing the current initial delay stage, and after updating the decreased initial delay stage to the initial delay stage, re-collecting the relative position (paragraph 88, shifts in the sampling clock signals CK1 through CK7 output to the sampling circuit 20 from the ideal positions thereof in accordance with the frequency alteration);
when the sampling position corresponding to the current initial delay stage is offset to the right relative to the center of the first parallel data window, increasing the current initial delay stage, and after updating the increased initial delay stage to the initial delay stage, re-collecting the relative position(paragraph 10-11, converting the serial data into parallel data and a serial-parallel converter circuit is used that is capable of sampling seven unit data contained in one clock unit forming the serial input data);
when the sampling position corresponding to the current initial delay stage is located at the center of the second parallel data window, the initial delay stage corresponding to the sampling position is taken as the second delay stage (paragraph 10-11, converting the serial data into parallel data and a serial-parallel converter circuit is used that is capable of sampling seven unit data contained in one clock unit forming the serial input data).
As per claim 4, Furuya discloses wherein collecting the relative position between the sampling position corresponding to the delay stage and the center of the scanning data window further comprising: selecting one set of data between the first parallel data and the second parallel data as reference data, and the other set of data as scanning data, to collect data, and the current delay stage corresponding to the scanning data in both the first parallel data and the second parallel data is defined as the delay stage of the scanning data (paragraph 64, generating phases (e.g., windows) that the timing resolution of T/(2n) is necessary to place the rising edges of clock signals in the center of respective data bits));
decreasing the current delay stage step by step, monitoring whether the reference data and the scanning data are consistent during a specific time period (paragraph 64, the timing resolution of T/(2n) is necessary to place the rising edges of clock signals in the center of respective data bits);
if the reference data and the scanning data are consistent, and the current delay stage has not decreased to zero, repeating decreasing the current delay stage step by step and monitoring whether the reference data and the scanning data are consistent during a specific time period (paragraph 107, timing relationships of the multi-phase clock signals generated by the delay circuit 500 when the delay is corrected by the clock delay correction circuit 800);
otherwise, recording the current delay stage as the first sub-delay stage and proceeding to reload the current delay stage (paragraph 13, the amount of delay in each of the unit delay circuits changes in accordance with a control voltage and controlled so that the clock signals CK with multiple phases output form the first unit delay circuit and the last unit delay circuit);
increasing the current delay stage step by step, monitoring whether the reference data and the scanning data are consistent during a specific time period(paragraph 64, the timing resolution of T/(2n) is necessary to place the rising edges of clock signals in the center of respective data bits);
if the reference data and the scanning are consistent, and the current delay stage has not reached the maximum delay stage value, repeating increasing the current delay stage step by step and monitoring whether the reference data and the scanning data are consistent during a specific time period(paragraph 107, timing relationships of the multi-phase clock signals generated by the delay circuit 500 when the delay is corrected by the clock delay correction circuit 800);
otherwise, recording the current delay stage as the second sub-delay stage (paragraph 66, the sub-delay circuit with the delays the clock signal (with the period of T) input thereto to generate and output 2n phases of multi-phase clock signals);
based on the current delay stage, the first sub-delay stage, and the second sub-delay stage, obtaining the first sub-delay stage difference between the current delay stage and the first sub-delay stage, and the second sub-delay stage difference between the current delay stage and the second sub-delay stage(paragraph 13, the amount of delay in each of the unit delay circuits changes in accordance with a control voltage and controlled so that the clock signals CK with multiple phases output form the first unit delay circuit and the last unit delay circuit); comparison of the first sub-delay stage difference and the second sub-delay stage difference, obtaining the relative position between the sampling position corresponding to the current delay stage and the center of the scanning data window(paragraph 21, an output of the sub-delay circuit is input and generates and outputs 2n phases of the delayed clock signals).
As per claim 5, Furuya discloses wherein comparison of the first sub-delay stage difference and the second sub-delay stage difference, obtaining the relative position between the sampling position corresponding to the current delay stage and the center of the scanning data window further comprising: the difference between the current delay stage and the first sub-delay stage is defined as the first sub-delay stage difference (paragraph 142, the difference between both of the signals is calculated to output a single end signal), and the difference between the second sub-delay stage and the current delay stage is defined as the second sub-delay stage difference (paragraph 21, an output of the sub-delay circuit is input and generates and outputs 2n phases of the delayed clock signals);
if the first sub-delay stage difference is greater than the second sub-delay stage, then the current sampling position corresponding to the current delay stage is offset to the left relative to the center of the scanning data window in both the first parallel data and the second parallel data(paragraph 64, generating phases (e.g., windows) that the timing resolution of T/(2n) is necessary to place the rising edges of clock signals in the center of respective data bits));
if the first sub-delay stage difference is less than the second sub-delay stage, then the current sampling position corresponding to the current delay stage is offset to the right relative to the center of the scanning data window in both the first parallel data and the second parallel data (paragraph 90, configuration of the clock delay correction circuit 800 in which the input clock signal CK is corrected in the delay by passing through the current control type clock delay correction circuit 800 to output to the delay circuit 500 as the delay corrected clock signal CK0);
if the first sub-delay stage difference equals to the second sub-delay stage, then the current sampling position corresponding to the current delay stage is at the center of the scanning data window in both the first parallel data and the second parallel data (paragraph 142, the difference between both of the signals is calculated to output a single end signal),
As per claim 6, Furuya discloses wherein the total delay of the first delay chain and the second delay chain is greater than the width of the serial data window. (paragraph 112, a high level duration of a sampling clock signal CKm that is the mth of n-phase sampling clock signals)
As per claim 7, Furuya discloses the method prior to inputting the P-end of the LVDS differential data signal into a first delay chain, and converting them into first parallel data through serial-to-parallel conversion, further comprising: scrambling the LVDS differential data, converting them into serial data through parallel-to-serial conversion, and inputting them into delay chain(paragraph 18, generating a sampling signal that takes a first level between (2m-1)T/2n and mT/n (m is a natural number) based on two or more of the delayed clock signals.); after receiving the LVDS differential data by using the second parallel data as scanning data, further comprising: descrambling and restoring the received LVDS differential data (paragraph 113, correcting the delay of the input clock signal CK by the clock delay correction circuit 800.)
As per claim 8, Furuya discloses wherein the initial delay stage is half of the total delay stage of the first delay chain (paragraph 88, Note that the base point of the DLL denotes a time point corresponding to an imaginary start position of the DLL.)
As per claim 9, Furuya discloses wherein the smaller the delay stage difference, the smaller the discrepancy in errors on the same chip and the difference in delay stages caused by asymmetry in the P-end and N-end slopes of LVDS differential data. (paragraph 90, the clock delay correction circuit 800 in which the input clock signal CK is corrected in the delay by passing through the current control type clock delay correction circuit 800)
Response to Amendment
3. Applicant's amendment filed on 3/3/2026 have been fully considered but does not place the application in condition for allowance.
a. In response to Applicant’s argument that Furuya fails to disclose separate processing of the P-end and N-end, inputting the P-end of the LVDS differential data signal into a first delay chain and converting it into first parallel data and inputting the N-end into a second delay chain and converting it into second parallel data. Examiner respectfully disagrees. As Furuya notes at paragraph 67, differential signals (a pair of positive and negative signals) having opposite phases to each other differentially transmitted and are detected as a difference signal (i.e., one of the signals of the opposite phases being inverted and added to the other to be output) by a differential circuit. In addition, (paragraph 142, Examiner further cited for clarification), Furuya discloses Note that in the differential circuit, the positive signal of the differential transmission signals is input to the plus (abbreviated to P) terminal and the negative signal of the differential transmission signals is input to the minus (abbreviated to M) terminal, and the difference between both of the signals is calculated to output a single end signal. This is equivalent as Applicant recites separate processing of the P-end and N-end. Thus, the prior art teaches the invention as claimed and the amended claims do not distinguish over the prior art as applied.
Applicant' s arguments are thus not persuasive towards patentability of the claims as presented and the rejections of record are maintained.
4. The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Querbach et al. [Pub. No. US20060265161] disclose based on the communication, regulating a timing between a strobe signal and a signal that propagates over the data bit line.
Whetsel et al. [Pub. No. US 20070103205] The serial data output from scan path 1802 to driver 100 is response test data loaded in parallel 1814 to the scan register from the circuit under test outputs.
Conclusion
5. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Conclusion
6. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIM T HUYNH whose telephone number is (571)272-3635 or via e-mail addressed to [kim.huynh3@uspto.gov]. The examiner can normally be reached on M-F 7.00AM- 4:00PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tsai Henry can be reached at (571)272-4176 or via e-mail addressed to [Henry.Tsai@USPTO.GOV].
The fax phone numbers for the organization where this application or proceeding is assigned are (571)273-8300 for regular communications and After Final communications. Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-2100.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/K. T. H./
Examiner, Art Unit 2184
/HENRY TSAI/ Supervisory Patent Examiner, Art Unit 2184
Prosecution Insights