Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 11, 13-14, 16, and 18-20are rejected under 35 U.S.C. 102(a)(1) as being unpatentable by Zhao et al. (US 2022/0037464 A1; hereinafter Zhao).
Regarding Claim 11. Zhao (Fig.1A) discloses a method of manufacturing an integrated circuit (IC) package, comprising:
providing a laminate (176) having a surface and defining a cavity ([0084]), wherein the cavity has an opening at the surface of the laminate;
mounting a semiconductor die (110) in the cavity;
electrically connecting the semiconductor die (110) to the laminate (176); and
closing the opening with a lid (178).
Regarding Claim 13. The method of claim 11, Zhao (Fig.1A) discloses wherein the laminate (176) comprises a laminate body and a conductive structure integrated into the laminate body ([0076]), wherein the opening is formed through the laminate body and the conductive structure and wherein electrically connecting the semiconductor die (110) to the laminate (176) comprises wirebonding (182/183) the semiconductor die (110) to the conductive structure of the laminate (176).
Regarding Claim 14. The method of claim 13, wherein: Zhao (Fig.1A) discloses the semiconductor die (110) is electrically connected to the conductive structure of the laminate ([0076]).
Regarding Claim 16. The method of claim 11, wherein: Zhao (Fig.1A; [0076]) discloses a heat sink is provided at a bottom of the cavity while the opening is at a top of the cavity; and the semiconductor die is mounted on the heat sink ([0076] discloses that 176 includes a heat sink since 176 is below die 110).
Regarding Claim 18. The method of claim 11, Zhao (Fig.1A; [0079]) discloses wherein the cavity is filled with air after the cavity is closed with the lid.
Regarding Claim 19. Zhao (Fig.1A; [0076]) discloses an integrated circuit (IC) package, comprising:
a laminate (176) having a surface and defining a cavity, wherein the cavity has an opening at the surface of the laminate (176);
a semiconductor die (110) mounted in the cavity and being electrically connected to the laminate (176); and
a lid (178) that closes the opening at the surface of the laminate (176).
Regarding Claim 20. The IC package of claim 19, wherein: Zhao (Fig.1A; [0076]) discloses the laminate (176) comprises a laminate body and a conductive structure integrated into the laminate body; the opening is formed through the laminate body and the conductive structure; and the semiconductor die (110) is electrically connected to the conductive structure of the laminate (176).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7, and 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Zhao et al. (US 2022/0037464 A1; hereinafter Zhao) in view of Dresser (US 2019/0311962 A1; Hereinafter Dresser).
Regarding Claim 1. Zhao (Fig.1A) discloses an integrated circuit (IC) package, comprising:
a laminate (176, [0076]) having a surface and defining a cavity ([0084]), wherein the cavity has an opening at the surface of the laminate (176; see Fig.1D);
a semiconductor die (110; [0085]) mounted in the cavity and being electrically connected to the laminate (176);
a lid (178, [0076]) that closes the opening at the surface of the laminate (176).
Zhao does not particularly disclose an overmold formed over the lid.
Dresser (Fig.3; [0042]) in a related art discloses a packaging including forming an overmold (360; [0042]) over the lid (310; [0039]).
Therefore, it would have been obvious in the art before the effective filling date of the application to use overmold on the lid since it provides robust environmental protection without having to accommodate critical RF fields
Regarding Claim 2. The IC package of claim 1, wherein: Zhao (Fig.1A) discloses the laminate (176) comprises a laminate body and a conductive structure integrated into the laminate body ([0076]);
the opening is formed through the laminate body and the conductive structure (Fig.1A); and
the semiconductor die (110) is electrically connected to the conductive structure of the laminate (176).
Regarding Claim 3. The IC package of claim 1, Zhao (Fig.1A; [0076]) discloses a heat sink, wherein: the heat sink is provided at a bottom of the cavity while the opening is at a top of the cavity; and the semiconductor die is mounted on the heat sink ([0076] discloses that 176 includes a heat sink since 176 is below die 110).
Regarding Claim 4. The IC package of claim 1, Dresser (Fig.3; [0040]) wherein the lid (310; [0048]) is formed from Silicon or glass.
Regarding Claim 5. The IC package of claim 1, Zhao (Fig.1A) discloses wherein the surface is a top surface of the laminate (176) and the opening is aligned with the top surface of the laminate.
Regarding Claim 6. The IC package of claim 5, Zhao (Fig.1A) discloses wherein the top surface is provided by a solder mask (120; [0077]) formed as a top layer of the laminate.
Regarding Claim 7. The IC package of claim 1, Zhao (Fig.1A) discloses wherein the laminate (176) comprises a laminate body, wherein the laminate body defines a bottom surface.
Regarding Claim 9. The IC package of claim 1, Zhao (Fig.1A; [0075], [0076]) discloses wherein the cavity is filled with air.
Regarding Claim 10. The IC package of claim 1, Zhao (Fig.1A) discloses wherein the semiconductor die (110) is wirebonded (182/183) to the laminate (176).
Claim(s) 1-7, and 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Zhao in view of Dresser in view of Minervini (US 2007/0201715 A1; Hereinafter Minervini)
Regarding Claim 8. The IC package of claim 7, Zhao does not particularly disclose wherein the bottom surface is formed by a solder mask formed from a bottom layer of the laminate.
Minervini (Fig.10) discloses in a related art a package wherein the bottom surface is formed by a solder mask (70; [0062]) formed from a bottom layer of the laminate.
Therefore, it would have been obvious in the art before the effective filling date of the application to have solder mask from a bottom layer of laminate in order to be able to electrically connect the device to an end user’s board.
Claim(s) 12, 15, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Zhao in view of Dresser.
Regarding Claim 12. The method of claim 11, Zhao does not particularly disclose forming an overmold over the lid.
Dresser (Fig.3; [0042]) in a related art discloses a packaging including forming an overmold (360; [0042]) over the lid (310; [0039]).
Therefore, it would have been obvious in the art before the effective filling date of the application to use overmold on the lid since it provides robust environmental protection without having to accommodate critical RF fields.
Regarding Claim 15. The method of claim 11, Zhao does not particularly disclose an epoxy for mounting the semiconductor die in the cavity.
Dresser (Fig.3; [0040]) in a related art discloses a packaging wherein an epoxy (315) is used for mounting the semiconductor die in the cavity (305).
Therefore, it would have been obvious in the art before the effective filling date of the application to use an epoxy for mounting the die in the cavity since it gives the package high mechanical strength, excellent adaptability for mismatched materials, and cost-effective, and high-throughput manufacturing.
Regarding Claim 17. The method of claim 11, Zhao does not particularly disclose wherein the lid is formed from Silicon or glass.
Dresser (Fig.3; [0040]) in a related art discloses a packaging wherein the lid (310; [0048]) is formed from Silicon or glass
Therefore, it would have been obvious in the art before the effective filling date of the application to use lid made of glass or silicon since it provides optical transparency, hermetic sealing, and excellent radio frequency (RF) properties.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAJAR KOLAHDOUZAN whose telephone number is (571)270-5842.
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/HAJAR KOLAHDOUZAN/ Examiner, Art Unit 2898
/Leonard Chang/ Supervisory Patent Examiner, Art Unit 2898
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