DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-20 are pending, of which all pending claims are rejected.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6, 9-14 and 17-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lim et el. (US 2025/0036520 A1), (Hereinafter Lim).
Regarding claim 1, Lim teaches, an error sampling and decoding system, comprising: a reference circuit configured to generate first and second reference values (Lim: ‘the reference value generator 420 generates first and second reference values’ [0083]); a comparator configured to receive a first error symbol, and to generate serial error data representing the first error symbol based on successive comparisons of the first error symbol with the first and second reference values (Lim: ‘RS signal compared with first and second reference values’ [0060] & [Fig.3C]); and a deserializer circuit configured to generate parallel data corresponding with the first error symbol based on the serial error data (Lim: “The analog-to-digital converter 411 may be configured to convert the voltage level of the analog signal RS into the reception digital value DRS. The hard decision circuit 412 may generate the plurality of reception data bits RB by comparing the reception digital value DRS with the plurality of hard decision reference values REF” [0085]; ‘data serialization and deserialization between transmitters and receivers’ [0112]).
Regarding claim 2, Lim teaches, the error sampling and decoding system of claim 1, wherein the comparator is configured to compare the first error symbol to a selected one of the first reference value and the second reference value (Lim: “The hard decision circuit 412 may generate the plurality of reception data bits RB by comparing the reception digital value DRS with the plurality of hard decision reference values REF” [0085]).
Regarding claim 3, Lim teaches, the error sampling and decoding system of claim 2, wherein the comparator is configured to select the selected one of the first reference value and the second reference value for use in a current compare operation based on a result of a previous compare operation (Lim: “[0070] Referring to FIG. 4, the hard decision (HD) may be performed to determine the value of the reception data bits RB by comparing the reception digital value DRS corresponding to a voltage level of the analog signal RS with the hard decision reference values REF1, REF2 and REF3. See also [Figs.4, 7 and corresponding descriptions] for comparison details between the reception signal with the reference values).
Regarding claim 4, Lim teaches, the error sampling and decoding system of claim 3, wherein the comparator is configured to select a higher of the first reference value and the second reference value for use in a current compare operation in response to the result of the previous compare operation indicating that the first error symbol was greater than the previously selected first or second reference value (Lim: “[0070] Referring to FIG. 4, the hard decision (HD) may be performed to determine the value of the reception data bits RB by comparing the reception digital value DRS corresponding to a voltage level of the analog signal RS with the hard decision reference values REF1, REF2 and REF3. See also [Figs.4, 7 and corresponding descriptions] for comparison details between the reception signal with the reference values).
Regarding claim 5, Lim teaches, the error sampling and decoding system of claim 2, further comprising a multiplexer configured to select the selected one of the first reference value and the second reference value for use in a current compare operation based on a result of a previous compare operation (Lim: “[0070] Referring to FIG. 4, the hard decision (HD) may be performed to determine the value of the reception data bits RB by comparing the reception digital value DRS corresponding to a voltage level of the analog signal RS with the hard decision reference values REF1, REF2 and REF3. See also [Figs.4, 7 and corresponding descriptions] for comparison details between the reception signal with the reference values).
Regarding claim 6, Lim teaches, the error sampling and decoding system of claim 5, wherein the multiplexer is configured to select a higher of the first reference value and the second reference value for use in a current compare operation in response to the result of the previous compare operation indicating that the first error symbol was greater than the previously selected first or second reference value (Lim: “[0070] Referring to FIG. 4, the hard decision (HD) may be performed to determine the value of the reception data bits RB by comparing the reception digital value DRS corresponding to a voltage level of the analog signal RS with the hard decision reference values REF1, REF2 and REF3. See also [Figs.4, 7 and corresponding descriptions] for comparison details between the reception signal with the reference values).
Regarding claim 9, Lim teaches, the error sampling and decoding system of claim 1, wherein the comparator is configured to receive a second error symbol, and to generate additional serial error data representing the second error symbol based on successive comparisons of the second error symbol with the first and second reference values, and wherein the deserializer circuit is configured to generate the parallel data corresponding with both the first error symbol and the second error symbol based on the serial error data representing the first error symbol and based on the additional serial error data representing the second error symbol (Lim: ‘data serialization and deserialization between transmitters and receivers’ [0112]).
Regarding claim 10, Lim teaches, a comparator sampler circuit (Lim: ‘comparator sampler circuit 410’ [0082] & [Fig.6]), comprising a comparator stage configured to generate serial error data representing a first error symbol based on successive comparisons of the first error symbol with selected first and second reference values (Lim: “The hard decision circuit 412 may generate the plurality of reception data bits RB by comparing the reception digital value DRS with the plurality of hard decision reference values REF.” [0085]) wherein the selected first and second reference values are selected based on a result of a previous compare operation (Lim: “Referring to FIG. 4, the hard decision (HD) may be performed to determine the value of the reception data bits RB by comparing the reception digital value DRS corresponding to a voltage level of the analog signal RS with the hard decision reference values REF1, REF2 and REF3” [0070]. See also [Figs.4, 7 and corresponding descriptions] for comparison details between the reception signal with the reference values).
Regarding claim 11, Lim teaches, the comparator sampler circuit of claim 10, wherein the comparator stage is configured to select the selected first and second reference values (Lim: “[0070] Referring to FIG. 4, the hard decision (HD) may be performed to determine the value of the reception data bits RB by comparing the reception digital value DRS corresponding to a voltage level of the analog signal RS with the hard decision reference values REF1, REF2 and REF3. See also [Figs.4, 7 and corresponding descriptions] for comparison details between the reception signal with the reference values).
Regarding claim 12, Lim teaches, the comparator sampler circuit of claim 11, wherein the comparator stage is configured to select a higher of the first and second reference values for use in a current compare operation in response to a result of a previous compare operation indicating that the first error symbol was greater than the previously selected first or second reference value (Lim: “[0070] Referring to FIG. 4, the hard decision (HD) may be performed to determine the value of the reception data bits RB by comparing the reception digital value DRS corresponding to a voltage level of the analog signal RS with the hard decision reference values REF1, REF2 and REF3. See also [Figs.4, 7 and corresponding descriptions] for comparison details between the reception signal with the reference values).
Regarding claim 13, Lim teaches, the comparator sampler circuit of claim 10, wherein the first and second reference values selected are selected by a multiplexer circuit (Lim: “[0070] Referring to FIG. 4, the hard decision (HD) may be performed to determine the value of the reception data bits RB by comparing the reception digital value DRS corresponding to a voltage level of the analog signal RS with the hard decision reference values REF1, REF2 and REF3. See also [Figs.4, 7 and corresponding descriptions] for comparison details between the reception signal with the reference values).
Regarding claim 14, Lim teaches, the comparator sampler circuit of claim 13, wherein the multiplexer circuit is configured to select a higher of the first and second reference values for use in a current compare operation in response to a result of a previous compare operation indicating that the first error symbol was greater than the previously selected first or second reference value (Lim: “[0070] Referring to FIG. 4, the hard decision (HD) may be performed to determine the value of the reception data bits RB by comparing the reception digital value DRS corresponding to a voltage level of the analog signal RS with the hard decision reference values REF1, REF2 and REF3. See also [Figs.4, 7 and corresponding descriptions] for comparison details between the reception signal with the reference values).
Regarding claim 17, Lim teaches, a method of using comparator sampler circuit (Lim: ‘comparator sampler circuit 410’ [0082] & [Fig.6]), the method comprising: generating serial error data representing a first error symbol based on successive comparisons of the first error symbol with selected first and second reference values (Lim: “The hard decision circuit 412 may generate the plurality of reception data bits RB by comparing the reception digital value DRS with the plurality of hard decision reference values REF.” [0085]); and successively selecting the first and second reference values based on a result of a previous compare operation (Lim: “Referring to FIG. 4, the hard decision (HD) may be performed to determine the value of the reception data bits RB by comparing the reception digital value DRS corresponding to a voltage level of the analog signal RS with the hard decision reference values REF1, REF2 and REF3” [0070]. See also [Figs.4, 7 and corresponding descriptions] for comparison details between the reception signal with the reference values).
Regarding claim 18, Lim teaches, The method of claim 17, wherein successively selecting the first and second reference values comprises selecting a higher of the first and second reference values for use in a current compare operation in response to a result of a previous compare operation indicating that the first error symbol was greater than the previously selected first or second reference value (Lim: “[0070] Referring to FIG. 4, the hard decision (HD) may be performed to determine the value of the reception data bits RB by comparing the reception digital value DRS corresponding to a voltage level of the analog signal RS with the hard decision reference values REF1, REF2 and REF3. See also [Figs.4, 7 and corresponding descriptions] for comparison details between the reception signal with the reference values).
Regarding claim 19, Lim teaches, The method of claim 17, wherein the first and second reference values selected are selected by a multiplexer circuit (Lim: “[0070] Referring to FIG. 4, the hard decision (HD) may be performed to determine the value of the reception data bits RB by comparing the reception digital value DRS corresponding to a voltage level of the analog signal RS with the hard decision reference values REF1, REF2 and REF3. See also [Figs.4, 7 and corresponding descriptions] for comparison details between the reception signal with the reference values).
Regarding claim 20, Lim teaches, The method of claim 17, wherein the first and second reference values selected are selected by a comparator/sampler circuit (Lim: “[0070] Referring to FIG. 4, the hard decision (HD) may be performed to determine the value of the reception data bits RB by comparing the reception digital value DRS corresponding to a voltage level of the analog signal RS with the hard decision reference values REF1, REF2 and REF3. See also [Figs.4, 7 and corresponding descriptions] for comparison details between the reception signal with the reference values).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 7-8 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Lim et el. (US 2025/0036520 A1) in view of Saraswat et al. (US 2023/0236996 A1), (Hereinafter Lim-Saraswat).
Regarding claim 7, Lim teaches, a PAM-4 signaling of four-level format. Lim does not explicitly disclose, the error sampling and decoding system of claim 1, wherein the first error symbol has a three-level format.
However, Saraswat et al. teaches in an analogous art, [0027] One specific application of PAM signaling is the transition of graphics memory (e.g., graphics double data rate (GDDR) memory) away from non-return to zero (NRZ) signaling to PAM3 signaling, where PAM3 refers to pulse amplitude modulation with three (3) signal voltage levels and two (2) data eyes. Reference throughout is primarily to PAM3 signaling, but it will be understood that PAM4 (pulse amplitude modulation with four (4) signal voltage levels and three (3) data eyes)) signaling can apply the same techniques to separately train the 3 data eyes.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the four-level format of PAM-4 signaling taught by Lim and the three-level format of PAM-3 signaling as taught by Saraswat can equally be used since both the techniques make improvement of the data eye, doing so would improves the bit error rate (BER) performance of the signal decoder.
Regarding claim 8, Lim-Saraswat teaches, the error sampling and decoding system of claim 1, wherein the system conforms with a graphics double data rate 7 (GDDR7) standard (Saraswat: “One specific application of PAM signaling is the transition of graphics memory (e.g., graphics double data rate (GDDR) memory) away from non-return to zero (NRZ) signaling to PAM3 signaling, where PAM3 refers to pulse amplitude modulation with three (3) signal voltage levels and two (2) data eyes. Reference throughout is primarily to PAM3 signaling, but it will be understood that PAM4 (pulse amplitude modulation with four (4) signal voltage levels and three (3) data eyes)) signaling can apply the same techniques to separately train the 3 data eyes.” [0027]).
Regarding claim 15, Lim-Saraswat teaches, the comparator sampler circuit of claim 10, the first error symbol has a three-level format (Saraswat: “One specific application of PAM signaling is the transition of graphics memory (e.g., graphics double data rate (GDDR) memory) away from non-return to zero (NRZ) signaling to PAM3 signaling, where PAM3 refers to pulse amplitude modulation with three (3) signal voltage levels and two (2) data eyes. Reference throughout is primarily to PAM3 signaling, but it will be understood that PAM4 (pulse amplitude modulation with four (4) signal voltage levels and three (3) data eyes)) signaling can apply the same techniques to separately train the 3 data eyes.” [0027]).
Regarding claim 16, Lim-Saraswat teaches, the comparator sampler circuit of claim 10, wherein the system conforms with a graphics double data rate 7 (GDDR7) standard (Saraswat: “One specific application of PAM signaling is the transition of graphics memory (e.g., graphics double data rate (GDDR) memory) away from non-return to zero (NRZ) signaling to PAM3 signaling, where PAM3 refers to pulse amplitude modulation with three (3) signal voltage levels and two (2) data eyes. Reference throughout is primarily to PAM3 signaling, but it will be understood that PAM4 (pulse amplitude modulation with four (4) signal voltage levels and three (3) data eyes)) signaling can apply the same techniques to separately train the 3 data eyes.” [0027]).
Citation of Pertinent Prior Art
It is noted that any citations to specific, pages, columns, lines, or figures in the prior art references and any interpretation of the reference should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. See MPEP 2123.
Conclusion
The following prior arts made of record, listed on form PTO-892, and not relied upon, if any, are considered pertinent to applicant's disclosure:
Van Ierssel (US 2021/0385060 A1) teaches a baud-rate phase detector uses two error samplers. One error sampler is used to determine whether the sampling time is too early error detection. The other is used to determine whether sampling time is too late. The early error sampler is configured to use a first threshold voltage. The late error sampler is configured to use a second threshold voltage. By adjusting the voltage difference between the first threshold voltage and the second threshold voltage, the phase difference between the local timing reference clock and the transitions of the data signal may be adjusted. The phase difference between the local timing reference clock and the transitions of the data signal may be adjusted to improve or optimize a desired receiver characteristic such as bit error rate or signal eye opening.
When amending the claims, Applicants are respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ENAMUL MD KABIR whose telephone number is (571)270-7256. The examiner can normally be reached on 10:00-6:30 pm.
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/ENAMUL M KABIR/
Examiner, Art Unit 2112
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112