Prosecution Insights
Last updated: October 27, 2026
Application No. 18/620,284

MULTI-TILE ARCHITECTURE FOR GRAPHICS OPERATIONS

Non-Final OA §103
Filed
Mar 28, 2024
Priority
Mar 15, 2019 — provisional 62/819,435 +4 more
Examiner
TSENG, CHENG YUAN
Art Unit
2615
Tech Center
2600 — Communications
Assignee
Intel Corporation
OA Round
3 (Non-Final)
84%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allowance Rate
722 granted / 858 resolved
+22.1% vs TC avg
Strong +15% interview lift
Without
With
+15.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
31 currently pending
Career history
899
Total Applications
across all art units

Statute-Specific Performance

§101
5.6%
-34.4% vs TC avg
§103
29.8%
-10.2% vs TC avg
§102
37.4%
-2.6% vs TC avg
§112
15.9%
-24.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 858 resolved cases

Office Action

§103
DETAILED ACTION Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 20-40 are rejected under 35 U.S.C. 103 as being unpatentable over Dash (US 11,367,160) in view of Zhao (10,360,063). Referring to claims 21, 28 and 34, Dash discloses an apparatus (fig. 1) comprising: a multi-tile architecture (fig. 1, parallel processing unit 102) for graphics operations including a graphics processing unit GPU (fig. 1, GPU 102), the GPU including: a plurality of processing core tiles (fig. 1, processing unit 104; fig. 4A, data processing cluster DPC 420) installed on one dice (18:15-30, die or chip); and a plurality of fixed function unit (fig. 4, pre-raster operation unit PROP 415, raster engine 425) installed on the dice, each fixed function unit being a unit (12:1-8, fixed function hardware) dedicated to perform one fixed processing function (12:9-20, raster) for operations of the GPU; wherein the apparatus is to: receive one application (fig. 1, application 122) for processing by the GPU; analyze processing requirements (fig. 1, scheduler 110; fig. 2A, such as priority) for the application; determine a preferred assignment (figs. 2B/2C, graphics wraps and compute wraps in SM over time). Zhao discloses determine a preferred assignment (fig. 4A, work items 402 to be reassigned 420) of the plurality of fixed function units (fig. 2A, work-ready processor queues 240a/240b/240c/240d) to the plurality of processing core tiles (fig. 2A, CPU 102/112/122/132) based on the processing requirements (17:32-40, CPU 112/GPU122 readiness) for the application and on performance characteristics (17:25-32, power consumption) of the plurality of fixed function units; and provide a dynamic exclusive assignment (fig. 4A, assign work items to work-ready processor 420) of the plurality of fixed function units (fig. 4A, work-ready processors 410) to one of the plurality of processing core tiles (fig. 4A, victim processor 410) according to the determined preferred assignment. Dash and Zhao are analogous art because they are from the same field of endeavor in processing systems. Before the time of the filing, it would have been obvious to a person of ordinary skill in the art, having the teaching of Dash and Zhao before him or her to modify the parallel processing unit 300 of Dash to include the work-ready processors of Zhao, thereafter work-ready processors are available for processing graphics wraps. The suggestion and/or motivation for doing so would be obtaining the advantage of improved load balancing (1:56-2:2) as suggested by Zhao. Therefore, it would have been obvious to combine Dash with Zhao to obtain the invention as specified in the instant application claims. As to claims 22, 29 and 35, Zhao discloses the apparatus of claim 21, wherein determining the preferred assignment of the plurality of fixed function units to the plurality of processing core tiles includes optimizing power consumption (2:36-44, power consumption) and performance (2:36-44, frequency) for processing of the application by the GPU. (See TSM analysis above) As to claims 23, 30 and 36, Zhao discloses the apparatus of claim 21, wherein a first fixed function unit of the plurality of fixed function unit includes one performance characteristic (2:36-44, power consumption) that differ from one performance characteristic (2:36-44, frequency) of a second fixed function unit (fig. 2A, work-ready processing queue 240a/240b/240c/240d) of the plurality of fixed function units. (See TSM analysis above) As to claims 24, 31 and 37, Zhao discloses the apparatus of claim 23, wherein the performance characteristic includes performance speed or power consumption (2:36-44, power consumption). (See TSM analysis above) As to claims 25, 32 and 38, Zhao discloses the apparatus of claim 21, wherein the apparatus is to modify the dynamic exclusive assignment of the plurality of fixed function units to the plurality of processing core tiles in response to a change (fig. 4A, dynamic characteristics data 410) in processing requirement for the GPU. (See TSM analysis above) As to claims 26 and 39, Dash discloses the apparatus of claim 21, wherein the GPU includes a structure (fig. 3, XBar 370) to interconnect the plurality of processing core tiles with the plurality of fixed function units. As to claims 27, 33 and 40, Dash discloses the apparatus of claim 21, wherein the application includes shader program (fig. 4A, raster engine 425). Contact Information Any inquiry concerning this communication or earlier communications from the examiner should be directed to examiner Cheng-Yuan Tseng whose telephone number is (571)272-9772, and fax number is (571)273-9772. The examiner can normally be reached on Monday through Friday from 09:00 to 17:30 Eastern Time. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alicia Harrington can be reached on (571)272-2330. The fax phone number for the organization where this application or proceeding is assigned is (571)273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at (866)217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call (800)786-9199 (IN USA OR CANADA) or (571)272-1000. /CHENG YUAN TSENG/Primary Examiner, Art Unit 2615
Read full office action

Prosecution Timeline

Mar 28, 2024
Application Filed
Feb 18, 2026
Non-Final Rejection mailed — §103
May 18, 2026
Response Filed
Jun 05, 2026
Final Rejection mailed — §103
Aug 05, 2026
Response after Non-Final Action
Sep 08, 2026
Request for Continued Examination
Sep 09, 2026
Response after Non-Final Action
Oct 06, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
84%
Grant Probability
99%
With Interview (+15.3%)
2y 5m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 858 resolved cases by this examiner. Grant probability derived from career allowance rate.

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