DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 21-40 are rejected under 35 U.S.C. 103 as being unpatentable over Sutardja (US 2008/0,263,324) in view of Kim (US 9,311,157).
Referring to claims 21, 28 and 34, Sutardja discloses an apparatus (fig. 2, asymmetric multi-processing system 10) comprising:
a multi-tile architecture (fig. 2, LP processor 12, HP processor 16) for graphics operations (para.0008, 3D graphics) including a graphics processing unit GPU (para.0319, video, mobile device control module 990), the GPU including:
a plurality of processing core tiles (fig. 5, LP core 200, HP core 204) installed on a dice (paras.0212, IC, SoC), and
wherein the apparatus is to:
receive an application (fig. 3A, applications) for processing by the GPU;
analyze processing requirements (fig. 6, LP core loading 252, HP processor speed and parameters 288) for the application;
determine a preferred assignment (fig. 6, need to switch to HP core? 256, need to switch to LP processor? 292) of the plurality of fixed function units (fig. 2, LP processor 12, HP processor 16) to the plurality of processing core tiles based on the processing requirements (fig. 6, LP core loading 252, HP processor speed and parameters 288) for the application and on performance characteristics (fig. 7, system loading 348, 360) of the plurality of fixed function units (fig. 7, LP processor speed 334, HP processor speed 356); and
provide a dynamic exclusive assignment (fig. 6, transition to HP processor 364, transition to LP processor 376) of the plurality of fixed function units to one of the plurality of processing core tiles according to the determined preferred assignment (fig. 7, flowchart).
Kim discloses an architecture for graphics operations (4:18-20, graphics operation) including a graphics processing unit GPU (fig. 1, GPU 120), the GPU including:
a plurality of processing core tiles (fig. 1, cores 115 of CPU 110) installed on a dice (fig. 1, configuration), and
a plurality of fixed function units (fig. 1, PE 125) to perform certain processing functions (fig. 2, ALU; 1:50-56).
Sutardja and Kim are analogous art because they are from the same field of endeavor in optimizing multi-core processor operations. Before the time of the filing, it would have been obvious to a person of ordinary skill in the art, having the teaching of Sutardja and Kim before him or her to modify the asymmetric processor cores of Sutardja to include the GPU with core tiles and plurality of function units of Kim, thereafter the asymmetric processor cores include GPU. The suggestion and/or motivation for doing so would be the advantage of improved execution performance and resource management (2:27-3:12) as suggested by Kim. Therefore, it would have been obvious to combine Sutardja with Kim to obtain the invention as specified in the instant application claims.
As to claims 22, 29 and 35, Sutardja discloses the apparatus of claim 21, wherein determining the preferred assignment of the plurality of fixed function units to the plurality of processing core tiles includes optimizing power consumption (fig. 4, transfer running to LP core 318) and performance (fig. 4, transfer running to HP core 338) for processing of the application by the GPU.
As to claims 23, 30 and 36, Sutardja discloses the apparatus of claim 21, wherein a first fixed function unit (fig. 2, LP processor 12) of the plurality of fixed function units includes a performance characteristic (para.0212, high-speed high-power, low-speed low-power) that differ from a performance characteristic of a second fixed function unit (fig. 2, HP processor 16) of the plurality of fixed function units.
As to claims 24, 31 and 37, Sutardja discloses the apparatus of claim 23, wherein the performance characteristic includes performance speed (para.0212, low-speed, high-speed).
As to claims 25, 32 and 38, Sutardja discloses the apparatus of claim 21, wherein the apparatus is to modify the dynamic exclusive assignment (fig. 6, transition to HP processor 352/364, transition to LP processor 376) of the plurality of fixed function units to the plurality of processing core tiles in response to a change in processing requirements (fig. 6, system loading 348, 360) for the multi-tile GPU.
As to claims 26 and 39, Kim discloses the apparatus of claim 21, wherein the GPU includes a structure to interconnect (fig. 2, busses) the plurality of processing core tiles with the plurality of fixed function units (See TSM analysis as above).
As to claims 27, 33 and 40, Kim discloses the apparatus of claim 21, wherein the application includes a shader program (4:18-20, graphics operations) (See TSM analysis as above).
Conclusion
Applicant’s amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, this action is made final. See MPEP §706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire in THREE MONTHS from the mailing date of this action. In the event a first reply is filled within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date of the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136 (a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than six months from the date of this final action.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to examiner Cheng-Yuan Tseng whose telephone number is (571)272-9772, and fax number is (571)273-9772. The examiner can normally be reached on Monday through Friday from 09:00 to 17:30 Eastern Time. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alicia Harrington can be reached on (571)272-2330. The fax phone number for the organization where this application or proceeding is assigned is (571)273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at (866)217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call (800)786-9199 (IN USA OR CANADA) or (571)272-1000.
/CHENG YUAN TSENG/Primary Examiner, Art Unit 2615
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