DETAILED ACTION
This Office action is in response to the amendment filed on 07 April 2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Response to Arguments
Applicant's arguments filed 07 April 2026 with respect to the rejection over Yao (US 2020/0336069) have been fully considered but they are not persuasive.
Applicant argues that Yao fails to disclose the feature in which the valley current limit circuit is arranged to switch a connection of the sample and hold capacitor to ground to provide a negative reference voltage from the sample and hold capacitor when the low-side switch is ON because the previous Office action indicated this to be allowable subject matter.
However, the argument is not found persuasive because the previous Office action did not state that the feature as it appears in amended claim 1 was allowable subject matter. Rather, the Office action indicated that claim 6 as well as claim 7, both taken as a whole, would be allowable if amended to include all of the limitations of their base claim and any intervening claims. Applicant has not amended either of claims 6 or 7 in this manner, and Yao anticipates claim 1 as it has been amended—see the explanation below in this Office action.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5 and 12-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yao (US 2020/0336069).
In re claims 1 and 13, Yao discloses a switching regulator (Fig. 3) comprising:
a high-side switch (HS);
a low-side switch (LS);
a switch node (SW) in between the high-side switch and the low-side switch (see Fig. 3);
an inductor (L) connected to the SW, the inductor providing an output voltage (Vout) depending on the high-side switch being turned ON or the low-side switch being turned ON (see, e.g., [0013], [0016], [0023]); and
a valley current limit circuit (Fig. 3: Iref, V2 (see detail Figs. 7-8), cmpr, S1, LSs) comprising:
a sample and hold capacitor (Fig. 7: C1);
wherein the valley current limit circuit is arranged to charge the sample and hold capacitor when a low-side switch of the switching regulator is OFF (Fig. 7 and [0036]: “Switches S2 and S3 may be controlled to be turned on when the power transistor to be sensed is turned off, such that capacitor C1 is charged”; it is noted that in Fig. 3 as cited above, the low-side switch LS is the transistor to be sensed) and to switch a connection of the sample and hold capacitor to ground to provide a negative reference voltage (VREF_NEG) from the sample and hold capacitor when the low-side switch is ON (Figs. 3, 7 and [0020]-[0022]: when the low-side switch LS is ON, the switch LSs is also turned ON and hence the negative connection terminal of capacitor C1 within V2 is switched to ground; at this time, the auxiliary source V2 with capacitor C1 may provide the negative voltage to comparator cmpr for a reverse current reference Iref); and
wherein the valley current limit circuit comprises a comparator (Fig. 3: cmpr) arranged to provide a current limit reference (ILIM) (Vctrl) for regulating a high-side control signal (HSON) for controlling switching of the high-side switch (see [0024]) by comparing the VREF_NEG (produced by auxiliary voltage source V2 and capacitor C1 as explained above, and appearing as part of voltage VA at the cmpr input terminal) against a switch node voltage (VSW) of the switching regulator when the low-side switch is ON (Fig. 3: switch S1 is ON when low-side switch LS is ON to provide the switch node voltage as VB to the comparator cmpr: see [0027]).
In re claims 2 and 14, Yao discloses wherein the switching regulator is a buck converter (Fig. 3 and [0016], noting that Figs. 1 and 3 both show the same buck topology for the switching regulator).
In re claims 3 and 4, Yao discloses a sense field-effect transistor (FET) (Fig. 3: LSs);
wherein the sense FET has a drain that is connected to a reference voltage (VDD) (any of VA, Vbias (Fig. 7), or the unlabeled voltage supplying Iref (Fig. 3));
wherein the sense FET has a gate that is connected to the VDD (indirectly, through various pathways as shown in Figs. 3, 7; or directly, when low-side gate signal GL is set to logic high, understood as VDD);
wherein the sense FET has a source that is connected to ground (see Fig. 3); and
wherein one side of the sample and hold capacitor is connected to the drain of the sense FET (at voltage node VA, when switches S2/S3 within auxiliary source V2 (see Fig. 7) are turned ON; see [0036]) for charging the sample and hold capacitor using a reference current (IREF) (Fig. 3: Iref; see [0036]), and wherein IREF is a result of the VDD on the sense FET (that is, VDD as a supply voltage provides the operating power of the circuit and thus enables its functionalities).
In re claims 5 and 15-18, Yao discloses wherein the sense FET and the low-side switch are proportional, so that Rds_low_side_switch: Rds_sense_FET= 1:K (see [0024]: the on-resistance of LSs is N times the on-resistance of LS); and
wherein the high-side switch (Fig. 3: HS) and the low-side switch (LS) are metal–oxide–semiconductor field-effect transistors (MOSFETs) (see Fig. 3 and [0017]).
In re claim 12, Yao discloses wherein the comparator is an auto zero comparator (that is, the term auto-zero comparator as it is understood to the person of ordinary skill in the art reasonably corresponds to the comparator functionality disclosed in Yao; see footnote 1).
Allowable Subject Matter
Claims 6-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
In general, the closest prior art to Applicant’s invention is considered to be either or both of the cited reference to Yao, applied in the anticipation rejections, above, as well as the additionally cited US 2015/0145495 to Tournatory.
Notably, Tournatory and Yao teach nearly the same current mode control circuits for a switching buck regulator, utilizing a replica device of the low-side transistor and a switched-capacitor or charge pump to enable a comparator to apply a negative reference and accurately detect a moment that the inductor current reaches a valley current limit while the low-side switch is on.
Regarding claims 6 and 7, Yao and Tournatory both teach a valley current limit circuit with first and second switches (Yao: Fig. 3: S1 and Fig. 7, S2, S3; Tournatory: Fig. 1, S1-S3), and further teach the operation whereby the capacitor (C1 in Yao; Csample in Tournatory) is charged when the low-side switch is OFF by connecting the capacitor between a reference signal and ground (Yao: see claim 1 citations, above; Tournatory: [0015] description for switches S1, S2).
However, due to a structural difference between the circuits disclosed by the prior art and that of Applicant’s disclosed invention, neither Yao nor Tournatory teach opening the first switches and closing the second switches when the low-side switch is on, thereby connecting the one side of the sample and hold capacitor to ground and connecting the other side of the sample and hold capacitor to the comparator, as recited in claims 6 and 7.
That is, in Yao, when the low-side switch is ON, the “one side” of capacitor C1 (positive end of auxiliary source V2: see Figs. 3 and 7), is disconnected from the voltage source Vbias by opening S2, but is notably not connected to ground as the claims at issue recite. Instead, the negative end of V2 and C1 are connected to ground via LSs. Similarly, Tournatory discloses identical function to Yao, whereby the “one-side” of Csample is disconnected from voltage VCM by opening S3, but is not connected to ground.
In addition, the prior art on record fails to suggest an appropriate modification to these disclosures in Yao and/or Trournatory that would result in the functional operations required in both of claims 6 and 7, particularly when considering the scope of these claims as a whole.
Claims 8-11 each depend, either directly or indirectly, from claim 6, and therefore would be allowable for the same reasons as explained above.
Conclusion
THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/FRED E FINCH III/Primary Examiner, Art Unit 2838
1 In Fig. 3 of Yao, the voltage VB at the negative comparator input is the switch node voltage when LS is ON, and is understood to actually be equal to -iL*Rdson, due to the voltage drop across LS when it is conducting current iL in the direction indicated by the arrow in Fig. 3. The same value is also subtracted out of the positive input terminal of the comparator as disclosed in eq. (1) of [0023]-[0024], thus providing the auto-zero functionality.
Prosecution Insights