DETAILED ACTION
Claims 1-20 are pending in this application.
Claims 6 and 11 are objected to.
Claims 1-5, 7-10 and 12-20 are rejected.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 3/4/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Magro et al. (U.S. PGPub No. 2022/0058141) hereinafter Magro’141 in view of Takano et al. (U.S. PGPub No. 2020/0026466) in view of Zhang et al. (U.S. PGPub No. 2024/0053898).
Claim 1
Magro (2022/0058141) teaches:
A memory controller, comprising: a command queue stage for storing decoded memory access requests; P. 0052 and FIG. 5 decoded addresses of received memory access requests are stored in command sub-queue 520
an arbitration stage operable to select first and second memory commands from the command queue stage for first and second pseudo-channels, respectively, using a first dedicated sub-arbiter for the first pseudo-channel, a second dedicated sub-arbiter for the second pseudo-channel, […] FIG. 5 and P. 0059 the decoded memory access request includes a decoded sub-channel number, decoded requests are stored in command sub-queues 520 and 521; P. 0060 arbiter 538 is connected to command sub-queue 520, similarly arbiter 539 is connected to command sub-queue 521. The arbiters pick eligible memory access requests from their respective command sub-queues 520 and 521 according to predetermined criteria
a dispatch queue having a downstream port […] P. 0045 arbiter 538 picks a memory access request stored in command queue 520 and provides it to dispatch queue 514
Magro’141 does not explicitly teach the arbitration stage having a shared sub-arbiter for both the first and second pseudo-channels.
Takano (2020/0026466) teaches:
an arbitration stage operable to select first and second memory commands from the command queue stage for first and second pseudo-channels, respectively, FIG. 5 and P. 0063 NAND controller 140-0 includes the four queue blocks 150-0 to 150-3 [pseudo-channels], each queue block 150 has the same configuration using a first dedicated sub-arbiter for the first pseudo-channel, FIG. 5 and P. 0066 queue block 150-0 includes a sub-bank arbiter 155 a second dedicated sub-arbiter for the second pseudo-channel, FIG. 5 and P. 0066 queue block 150-1 includes a sub-bank arbiter 155 and a shared sub- arbiter for both the first pseudo-channel and the second pseudo-channel FIG. 5 and P. 0065 bank arbiter 160 implements the bank arbitration by sequentially selecting the four queue blocks 150 [pseudo-channels]
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Magro’141 with the arbitration stage having a shared sub-arbiter for both the first and second pseudo-channels taught by Takano
The motivation being to switch execution and non-execution of the sub-bank arbitration (see Takano P. 0084)
The systems of Magro’141 and Takano do not explicitly teach the dispatch queue sending data of the first and second memory commands in a time-multiplexed manner.
Zhang (2024/0053898) teaches:
a dispatch queue having a downstream port for conducting first data of the first memory commands that is time-multiplexed with second data of the second memory commands. P. 0062 when the register and divided clock driver receives a read command (RD), it sends the read command (referred to CMD PC0 for pseudo channel PC0 and CMD PC1 for pseudo channel PC1) to pseudo channels PC0 and PC1 separately, and pseudo channels PC0 and PC1 send the data to the combined data buffer separately; P. 0057 high-bandwidth DDR DIMM 100 further includes a combined data buffer configured to interleave data of pseudo channels PC0 and PC1
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Magro’141 and Takano with the dispatch queue sending data of the first and second memory commands in a time-multiplexed manner taught by Zhang
The motivation being data can be read faster and more effectively (see Zhang P. 0070)
The systems of Magro’141, Takano and Zhang are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Magro’141 and Takano with Zhang to obtain the invention as recited in claims 1-11.
Claim 2
Magro (2022/0058141) teaches:
The memory controller of claim 1, further comprising: an address decoder having an upstream port for receiving memory access requests, and P. 0052 and FIG. 5 Address generator 522 decodes addresses of memory access requests received from data fabric 250 over the AXI4 bus
a downstream port coupled to the command queue stage for providing the decoded memory access requests including a pseudo-channel number. P. 0059 Address generator 522 sends the decoded memory access request including the decoded sub-channel number to command sub-queues 520 and 521
Claim 3
Magro (2022/0058141) teaches:
The memory controller of claim 1, wherein the command queue stage comprises: a first command queue having an upstream port for receiving decoded memory access requests for the first pseudo-channel, and a downstream port; and FIG. 5 and P. 0059 Address generator 522 sends the decoded memory access request including the decoded sub-channel number to command sub-queues 520, 521 [command queue stage]; FIG. 8 and P. 0070 read and write queues are employed for each sub-channel such that each command sub-queues 800, 802 [first command queue] store both read and write memory access requests; P. 0058 selector 541 selects and dispatches a preferred memory access request 543 from among the provided memory access requests from the command sub-queues (e.g. queues 800 and 802)
a second command queue having an upstream port for receiving decoded memory access requests for the second pseudo-channel, and a downstream port. FIG. 8 and P. 0070 command sub-queues queues 804, 806 [second command queue] include similar components to receive decoded commands and dispatch a selected command
Claim 4
Magro (2022/0058141) teaches:
The memory controller of claim 1, wherein the arbitration stage comprises: a first plurality of dedicated sub-arbiters including the first dedicated sub-arbiter for selecting decoded memory access requests of the first pseudo-channel; and FIG. 5 and P. 0056 selector 541 picks the corresponding write access from either of the command sub-queues 520, 521 based on the command selected by each respective arbiter 538, 539 for dispatch to the memory channel; FIG. 8 and P. 0070 command sub-queues 800, 802 (analogous to sub-queues 520, 521) correspond to a first sub-channel
a dedicated second plurality of sub-arbiters including the second dedicated sub-arbiter for selecting decoded memory access requests of the second pseudo-channel. FIG. 5 and P. 0056 selector 541 picks the corresponding write access from either of the command sub-queue 520 or command sub-queue 521 based on the command selected by each respective arbiter 538 or arbiter 539 for dispatch to the memory channel; FIG. 8 and P. 0070 command sub-queues 804, 806 (analogous to sub-queues 520, 521) correspond to a second sub-channel
Claim 5
Magro (2022/0058141) teaches:
The memory controller of claim 4, wherein the first plurality of dedicated sub-arbiters comprises: a first page hit sub-arbiter for selecting decoded memory access requests to open pages of the first pseudo-channel; and P. 0063-64 Each arbiter 538, 539 (e.g. corresponding to sub-queues 800, 802 in FIG. 8) evaluate page table (PGT) information 600 to select a winning memory access request 606 and 608 that is provided to the selector 541. PGT information 600 represents whether a DRAM page is open. Page hit (PH) means that the page that is needed is already “ACTIVE”
a first page miss sub-arbiter for selecting decoded memory access requests to closed pages of precharged banks of the first pseudo-channel. P. 0063-64 PGT information 600 represents whether a DRAM page is in the closed state (i.e. meaning it was pre-charged) and thus no page on a bank is opened. Page Miss (PM) means that the page needed is not open in the DRAM
Claim 7
Magro (2022/0058141) teaches:
The memory controller of claim 1, wherein the command queue stage comprises: a common command queue having an upstream port for receiving memory access requests for a selected one of the first pseudo-channel and the second pseudo-channel, and a downstream port. FIG. 6 and P. 0059 Address generator 522 sends the decoded memory access request including the decoded sub-channel number to command queue 520; P. 0068 selector 708 and sends the selected memory access request to one or more sub-channels
Claim 8
Magro (2022/0058141) teaches:
The memory controller of claim 7, wherein the arbitration stage comprises: a plurality of sub-arbiters including the first dedicated sub-arbiter, the second dedicated sub-arbiter […] each having an upstream port coupled to the command queue stage, and FIG. 5 and P. 0055 arbiters 538 and 539 select a command from command sub-queues 520 and 421 respectively
a downstream port coupled to the dispatch queue, for selecting decoded memory access requests of the first pseudo-channel and the second pseudo-channel. FIG. 5 and P. 0056 selector 541 picks the corresponding write access from either of the command sub-queues 520, 521 based on the command selected by each respective arbiter 538, 539 for dispatch to the memory channel
Takano (2020/0026466) teaches:
wherein the arbitration stage comprises: a plurality of sub-arbiters including the first dedicated sub-arbiter, the second dedicated sub-arbiter, and the shared sub-arbiter, each having an upstream port coupled to the command queue stage, and FIG. 5 and P. 0064 each queue block 150 (e.g. queue block 150-0 [first pseudo-channel]) receives a command from command generator 111 for its corresponding bank, and retains the command in a main queue 151 or a plurality of sub-queues 154; P. 0079 sub-bank arbiter 155 includes four input terminals [upstream port] connected to the four sub-queues 154; P. 0162 the input terminals of bank arbiter 160 are connected to the queue blocks
a downstream port coupled to the dispatch queue, for selecting decoded memory access requests of the first pseudo-channel and the second pseudo-channel. P. 0079 output terminal [downstream port] of the sub-bank arbiter 155 is connected to multiplexer 156; P. 0065 bank arbiter 160 enables the transmission of a command from the selected queue block 150
Claim 10
Magro (2022/0058141) teaches:
The memory controller of claim 8, wherein the at least one dedicated sub-arbiter for each of the first and second pseudo-channels comprises: a page hit sub-arbiter for selecting decoded memory access requests to open pages of a respective pseudo-channel. P. 0063-64 Each arbiter 538, 539 (e.g. corresponding to sub-queues 800, 802 in FIG. 8) evaluate page table (PGT) information 600 to select a winning memory access request 606 and 608 that is provided to the selector 541. PGT information 600 represents whether a DRAM page is open. Page hit (PH) means that the page that is needed is already “ACTIVE”
Claim 12
Magro (2022/0058141) teaches:
A data processing system, comprising:
a plurality of data processor cores each for generating memory access requests; FIG. 2 and P. 0039 CPU cores 212, 214 send memory access requests
a data fabric; and FIG. 2 and P. 0038 data fabric 250
at least one memory controller, FIG. 2 and P. 0038 memory controllers 290 (292, 294)
wherein the data fabric selectively routes the memory access requests and memory access responses between the plurality of data processor cores and the at least one memory controller, FIG. 2 and P. 0039 CPU cores 212, 214 provide memory access requests to data fabric 250; P. 0034 memory access requests are received from data fabric 250
wherein each of the at least one memory controller comprises:
a command queue stage for storing decoded memory access requests; P. 0052 and FIG. 5 decoded addresses of received memory access requests are stored in command sub-queue 520
an arbitration stage operable to select first and second memory commands from the command queue stage for first and second pseudo-channels using a first dedicated sub-arbiter for the first pseudo-channel, a second dedicated sub-arbiter for the second pseudo- channel […] FIG. 6 and P. 0042 Command queue 520 stores the decoded memory access request in an entry 610 in command queue 520, which has a first field 612 for storing the decoded sub-channel number; P. 0043 and FIG. 6 Arbiter 538 picks eligible memory access requests for issuance independently for each sub-channel from command queue 520, and uses timing block 534
Magro’141 does not explicitly teach the arbitration stage having a shared sub-arbiter for both the first and second pseudo-channels.
Takano (2020/0026466) teaches:
an arbitration stage operable to select first and second memory commands from the command queue stage for first and second pseudo-channels FIG. 5 and P. 0063 NAND controller 140-0 includes the four queue blocks 150-0 to 150-3 [pseudo-channels], each queue block 150 has the same configuration using a first dedicated sub-arbiter for the first pseudo-channel, FIG. 5 and P. 0066 queue block 150-0 includes a sub-bank arbiter 155 a second dedicated sub-arbiter for the second pseudo- channel, and FIG. 5 and P. 0066 queue block 150-1 includes a sub-bank arbiter 155 a shared sub-arbiter for both the first pseudo-channel and the second pseudo-channel; and FIG. 5 and P. 0065 bank arbiter 160 implements the bank arbitration by sequentially selecting the four queue blocks 150 [pseudo-channels]
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Magro’141 with the arbitration stage having a shared sub-arbiter for both the first and second pseudo-channels taught by Takano
The motivation being to switch execution and non-execution of the sub-bank arbitration (see Takano P. 0084)
The systems of Magro’141 and Takano do not explicitly teach the dispatch queue sending data of the first and second memory commands in a time-multiplexed manner.
Zhang (2024/0053898) teaches:
a dispatch queue having first and second upstream ports for receiving the first memory commands and the second memory commands, and a downstream port for conducting first data of the first memory commands time-multiplexed with second data of the second memory commands. P. 0062 when the register and divided clock driver receives a read command (RD), it sends the read command (referred to CMD PC0 for pseudo channel PC0 and CMD PC1 for pseudo channel PC1) to pseudo channels PC0 and PC1 separately, and pseudo channels PC0 and PC1 send the data to the combined data buffer separately; P. 0057 high-bandwidth DDR DIMM 100 further includes a combined data buffer configured to interleave data of pseudo channels PC0 and PC1
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Magro’141 and Takano with the dispatch queue sending data of the first and second memory commands in a time-multiplexed manner taught by Zhang
The motivation being data can be read faster and more effectively (see Zhang P. 0070)
The systems of Magro’141, Takano and Zhang are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Magro’141 and Takano with Zhang to obtain the invention as recited in claims 12-15.
Claim 13
Magro (2022/0058141) teaches:
The data processing system of claim 12, wherein: the command queue stage comprises:
a first command queue having an upstream port for receiving decoded memory access requests for the first pseudo-channel, and a downstream port; and FIG. 5 and P. 0059 Address generator 522 sends the decoded memory access request including the decoded sub-channel number to command sub-queues 520, 521 [command queue stage]; FIG. 8 and P. 0070 read and write queues are employed for each sub-channel such that each command sub-queues 800, 802 [first command queue] store both read and write memory access requests; P. 0058 selector 541 selects and dispatches a preferred memory access request 543 from among the provided memory access requests from the command sub-queues (e.g. queues 800 and 802)
a second command queue having an upstream port for receiving decoded memory access requests for the second pseudo-channel, and a downstream port. FIG. 8 and P. 0070 command sub-queues queues 804, 806 [second command queue] include similar components to receive decoded commands and dispatch a selected command
Claim 14
Magro (2022/0058141) teaches:
The data processing system of claim 12, wherein: the command queue stage comprises:
a common command queue having an upstream port for receiving memory access requests for a selected one of the first pseudo-channel and the second pseudo-channel, and a downstream port, and FIG. 6 and P. 0042 Address generator 522 sends the decoded memory access request including the decoded sub-channel number to command queue 520; P. 0043 Arbiter 538 picks eligible memory access requests independently for each sub-channel from command queue 520
Claim 15
Magro (2022/0058141) teaches:
The data processing system of claim 12, further comprising: a physical interface circuit coupled to an output of the dispatch queue; and FIG. 3 and P. 0047 physical interface 316 connects memory channel controller 314 (which contains dispatch queue 514, see FIG. 5) to PHY 330
a memory coupled to the physical interface circuit comprising a multiplexed-rank dual inline memory module (MRDIMM). P. 0033 and FIG. 1 Memory channel 130 includes a set of dual inline memory modules (DIMMs) connected to a DDRx bus 132
Claim 16
Magro (2022/0058141) teaches:
A method for accessing a memory, comprising: storing memory access requests in a command queue stage, wherein each memory access request accesses one of a first pseudo-channel and a second pseudo-channel of the memory; P. 0052 and FIG. 5 decoded addresses of received memory access requests are stored in command sub-queue 520; P. 0059 the decoded memory access request includes a decoded sub-channel number, decoded requests are stored in command sub-queues 520 and 521
arbitrating among the memory access requests in an arbitration stage to obtain first arbitration winners for the first pseudo-channel and second arbitration winners for the second pseudo-channel using […] at least one dedicated resource for each of the first and second pseudo-channels; wherein the arbitrating comprises using a first dedicated sub-arbiter for the first pseudo-channel, a second dedicated sub-arbiter for the second pseudo-channel P. 0060 arbiter 538 is connected to command sub-queue 520, similarly arbiter 539 is connected to command sub-queue 521. The arbiters pick eligible memory access requests from their respective command sub-queues 520 and 521 according to predetermined criteria
Magro’141 does not explicitly teach the arbitration stage having a shared sub-arbiter for both the first and second pseudo-channels.
Takano (2020/0026466) teaches:
arbitrating among the memory access requests in an arbitration stage to obtain first arbitration winners for the first pseudo-channel and second arbitration winners for the second pseudo-channel using a shared resource FIG. 5 and P. 0065 bank arbiter 160 implements the bank arbitration by sequentially selecting the four queue blocks 150 [pseudo-channels] and at least one dedicated resource for each of the first and second pseudo-channels; FIG. 5 and P. 0063 NAND controller 140-0 includes the four queue blocks 150-0 to 150-3 [pseudo-channels]; P. 0082 sub-bank arbiter 155 selects a command from one of the sub-queues 154
wherein the arbitrating comprises using a first dedicated sub-arbiter for the first pseudo-channel, a second dedicated sub-arbiter for the second pseudo-channel FIG. 5 and P. 0066 queue block 150-0 includes a sub-bank arbiter 155; FIG. 5 and P. 0066 queue block 150-1 includes a sub-bank arbiter 155; P. 0063 each queue block 150 has the same configuration
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Magro’141 with the arbitration stage having a shared sub-arbiter for both the first and second pseudo-channels taught by Takano
The motivation being to switch execution and non-execution of the sub-bank arbitration (see Takano P. 0084)
The systems of Magro’141 and Takano do not explicitly teach the dispatch queue sending data of the first and second memory commands in a time-multiplexed manner.
Zhang (2024/0053898) teaches:
overlapping first memory access requests of the first pseudo-channel and second memory access requests of the second pseudo-channel on a command and address bus by a dispatch queue stage; and P. 0062 the first pseudo channel PC0 and the second pseudo channel PC1 send data associated with a host command to the combined data buffer separately; P. 0064 and FIG. 3 when data of both pseudo channel PC0 and pseudo channel PC1 arrive, the data D2 and D3 of pseudo channel PC0 is interleaved with the data D0 and D1 of pseudo channel PC
time-division multiplexing first data of the first memory access requests and second data of the second memory access requests by the dispatch queue stage. P. 0062 when the register and divided clock driver receives a read command (RD), it sends the read command (referred to CMD PC0 for pseudo channel PC0 and CMD PC1 for pseudo channel PC1) to pseudo channels PC0 and PC1 separately, and pseudo channels PC0 and PC1 send the data to the combined data buffer separately; P. 0057 high-bandwidth DDR DIMM 100 further includes a combined data buffer configured to interleave data of pseudo channels PC0 and PC1
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Magro’141 and Takano with the dispatch queue sending data of the first and second memory commands in a time-multiplexed manner taught by Zhang
The motivation being data can be read faster and more effectively (see Zhang P. 0070)
The systems of Magro’141, Takano and Zhang are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Magro’141 and Takano with Zhang to obtain the invention as recited in claims 16-20.
Claim 17
Magro (2022/0058141) teaches:
The method of claim 16, wherein the storing comprises: storing memory access requests for both the first pseudo-channel and the second pseudo-channel in a common command queue. FIG. 6 and P. 0059 Address generator 522 sends the decoded memory access request including the decoded sub-channel number to command queue 520; P. 0068 selector 708 and sends the selected memory access request to one or more sub-channels
Claim 18
Takano (2020/0026466) teaches:
The method of claim 16, wherein the arbitrating comprises: arbitrating among the memory access requests using an arbitration stage having a sub-arbiter common to both the first pseudo-channel and the second pseudo-channel. FIG. 5 and P. 0063 NAND controller 140-0 includes the four queue blocks 150-0 to 150-3 [pseudo-channels]; P. 0065 bank arbiter 160 implements the bank arbitration by sequentially selecting the four queue blocks 150 [pseudo-channels]
Claim 19
Zhang (2024/0053898) teaches:
The method of claim 16, wherein the overlapping and time-division multiplexing comprises: overlapping and time-division multiplexing using a dispatch queue common to both the first pseudo-channel and the second pseudo-channel. P. 0057 each group of pseudo channels PC0 and PC1 correspond to one combined data buffer
Claim 20
Magro (2022/0058141) teaches:
The method of claim 16, further comprising: receiving memory access requests by an address decoder circuit; P. 0052 and FIG. 5 Address generator 522 decodes addresses of memory access requests received from data fabric 250 over the AXI4 bus
decoding a corresponding pseudo-channel for each of the memory access requests; and P. 0059 address generator 522 decodes the address of each memory access request into a sub-channel number
sending a decoded memory access request with a decoded pseudo-channel to the command queue stage. P. 0059 Address generator 522 sends the decoded memory access request including the decoded sub-channel number to command sub-queues 520 and 521
Allowable Subject Matter
Claims 6 and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
Claim 6 recites the limitation “wherein the shared sub-arbiter comprises a page conflict sub-arbiter for selecting decoded memory access requests to closed pages in banks with another page that is open in the first and second pseudo-channels”
Said limitation is taught by the specification of the instant application as originally filed at least at [P. 0046 and FIG. 4]. Said limitations, in combination with the other recited limitations of claim 6, are not taught or suggested by the prior art of record.
The closest prior art of record includes: Magro (2018/0018105) which teaches arbitrating requests from a plurality of sub-channels; Magro (2022/0058141) which teaches a plurality of sub-channels, each sub-channel having a plurality of command sub-queues, each of the sub-channels having multiple stages of arbitration, the final level of arbitration selecting requests based on page hit information that determines whether a page in DRAM is in an open or closed state; Zhang (2024/0053898); and Takano (2020/0026466) which teaches a plurality of queue blocks corresponding to each bank, each queue block including a plurality of sub-queues and arbitration between the sub queues, and a bank arbiter selecting requests from each of the queue blocks for output over a channel. None of the references teach an arbiter shared between first and second pseudo-channels, each of which have their own dedicated arbiters, having a page conflict mechanism that selects requests to closed pages in a bank that has an open page in one of the first or second pseudo-channels.
Claim 11 contains similar limitations to claim 6, and is considered allowable for at least the same reasons as claim 6.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant’s arguments, see pages 8-9, filed 3/4/2026, with respect to amended claim 1 have been fully considered and are persuasive. The 103 rejection of claim 1 under Magro’104, Magro’141 and Zhang has been withdrawn. The claims are now rejected under Magro’141, Takano and Zhang.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Magro et al (U.S. Patent No. 10684969) teaches multiple arbitration stages for selecting a command from a command queue
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEPHANIE WU whose telephone number is (571)272-0257. The examiner can normally be reached 1pm to 6pm, and 10pm to 1am Eastern time (10am to 3pm, and 7pm to 10pm Pacific time).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rocio Del Mar Perez-Velez can be reached at (571) 270-5935. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STEPHANIE WU/Primary Examiner, Art Unit 2133
