DETAILED ACTION
Claims 1-20 are pending in this application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Magro et al. (U.S. PGPub No. 2018/0018105) hereinafter Magro’105 in view of Magro et al. (U.S. PGPub No. 2022/0058141) hereinafter Magro’141 in view of Zhang et al. (U.S. PGPub No. 2024/0053898).
Claim 1
Magro (2018/0018105) teaches:
A memory controller, comprising: a command queue stage for storing decoded memory access requests; P. 0034 and FIG. 5 Command queue 520 is a queue of memory access requests received, and stores the address fields decoded by address generator 522
an arbitration stage operable to select first and second memory commands from the command queue stage for first and second pseudo-channels, respectively, using a shared resource […] FIG. 6 and P. 0042 Command queue 520 stores the decoded memory access request in an entry 610 in command queue 520, which has a first field 612 for storing the decoded sub-channel number; P. 0043 and FIG. 6 Arbiter 538 picks eligible memory access requests for issuance independently for each sub-channel from command queue 520, and uses timing block 534
a dispatch queue having a downstream port […] P. 0045 arbiter 538 picks a memory access request stored in command queue 520 and provides it to dispatch queue 514
Magro’105 does not explicitly teach the arbitration stage having a shared resource and dedicated resources for each of the first and second pseudo-channels.
Magro (2022/0058141) teaches:
an arbitration stage operable to select first and second memory commands from the command queue stage for first and second pseudo-channels, respectively, using a shared resource and at least one dedicated resource for each of the first and second pseudo-channels FIG. 5 and P. 0056 selector 541 picks the corresponding write access from either of the command sub-queues 520, 521 based on the command selected by each respective arbiter 538, 539 for dispatch to the memory channel; FIG. 8 and P. 0070 command sub-queues 800, 802 (analogous to sub-queues 520, 521) correspond to a first sub-channel, command sub-queues 804, 806 (analogous to sub-queues 520, 521) correspond to a second sub-channel
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Magro’105 with the arbitration stage having a shared resource and dedicated resources for each of the first and second pseudo-channels taught by Magro’141
The motivation being a single controller may run two separate channels independently (see Magro’141 P. 0033)
The systems of Magro’105 and Magro’141 do not explicitly teach the dispatch queue sending data of the first and second memory commands in a time-multiplexed manner.
Zhang (2024/0053898) teaches:
a dispatch queue having a downstream port for conducting first data of the first memory commands that is time-multiplexed with second data of the second memory commands. P. 0062 when the register and divided clock driver receives a read command (RD), it sends the read command (referred to CMD PC0 for pseudo channel PC0 and CMD PC1 for pseudo channel PC1) to pseudo channels PC0 and PC1 separately, and pseudo channels PC0 and PC1 send the data to the combined data buffer separately; P. 0057 high-bandwidth DDR DIMM 100 further includes a combined data buffer configured to interleave data of pseudo channels PC0 and PC1
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Magro’105 and Magro’141 with the dispatch queue sending data of the first and second memory commands in a time-multiplexed manner taught by Zhang
The motivation being data can be read faster and more effectively (see Zhang P. 0070)
The systems of Magro’105, Magro’141 and Zhang are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Magro’105 and Magro’141 with Zhang to obtain the invention as recited in claims 1-11.
Claim 2
Magro (2018/0018105) teaches:
The memory controller of claim 1, further comprising: an address decoder having an upstream port for receiving memory access requests, and P. 0034 and FIG. 5 Address generator 522 decodes addresses of memory access requests received from data fabric 250
a downstream port coupled to the command queue stage for providing the decoded memory access requests including a pseudo-channel number. P. 0042 Address generator 522 sends the decoded memory access request including the decoded sub-channel number to command queue 520
Claim 3
The systems of Magro’105 and Zhang do not explicitly teach the command queue stage having separate command queues for each pseudo-channel.
Magro (2022/0058141) teaches:
The memory controller of claim 1, wherein the command queue stage comprises: a first command queue having an upstream port for receiving decoded memory access requests for the first pseudo-channel, and a downstream port; and FIG. 5 and P. 0059 Address generator 522 sends the decoded memory access request including the decoded sub-channel number to command sub-queues 520, 521 [command queue stage]; FIG. 8 and P. 0070 read and write queues are employed for each sub-channel such that each command sub-queues 800, 802 [first command queue] store both read and write memory access requests; P. 0058 selector 541 selects and dispatches a preferred memory access request 543 from among the provided memory access requests from the command sub-queues (e.g. queues 800 and 802)
a second command queue having an upstream port for receiving decoded memory access requests for the second pseudo-channel, and a downstream port. FIG. 8 and P. 0070 command sub-queues queues 804, 806 [second command queue] include similar components to receive decoded commands and dispatch a selected command
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Magro’105 and Zhang with the command queue stage having separate command queues for each pseudo-channel taught by Magro’141
The motivation being a single controller may run two separate channels independently (see Magro’141 P. 0033)
The systems of Magro’105, Zhang and Magro’141 are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Magro’105 and Zhang with Magro’141 to obtain the invention as recited in claim 3.
Claim 4
Magro (2022/0058141) teaches:
The memory controller of claim 1, wherein the at least one dedicated resource for each of the first and second pseudo-channels the arbitration stage comprises: a first plurality of sub-arbiters for selecting decoded memory access requests of the first pseudo-channel; and FIG. 5 and P. 0056 selector 541 picks the corresponding write access from either of the command sub-queues 520, 521 based on the command selected by each respective arbiter 538, 539 for dispatch to the memory channel; FIG. 8 and P. 0070 command sub-queues 800, 802 (analogous to sub-queues 520, 521) correspond to a first sub-channel
a second plurality of sub-arbiters for selecting decoded memory access requests of the second pseudo-channel. FIG. 5 and P. 0056 selector 541 picks the corresponding write access from either of the command sub-queue 520 or command sub-queue 521 based on the command selected by each respective arbiter 538 or arbiter 539 for dispatch to the memory channel; FIG. 8 and P. 0070 command sub-queues 804, 806 (analogous to sub-queues 520, 521) correspond to a second sub-channel
Claim 5
Magro (2022/0058141) teaches:
The memory controller of claim 4, wherein the first plurality of sub-arbiters comprises: a first page hit sub-arbiter for selecting decoded memory access requests to open pages of the first pseudo-channel; and P. 0063-64 Each arbiter 538, 539 (e.g. corresponding to sub-queues 800, 802 in FIG. 8) evaluate page table (PGT) information 600 to select a winning memory access request 606 and 608 that is provided to the selector 541. PGT information 600 represents whether a DRAM page is open. Page hit (PH) means that the page that is needed is already “ACTIVE”
a first page miss sub-arbiter for selecting decoded memory access requests to closed pages of precharged banks of the first pseudo-channel. P. 0063-64 PGT information 600 represents whether a DRAM page is in the closed state (i.e. meaning it was pre-charged) and thus no page on a bank is opened. Page Miss (PM) means that the page needed is not open in the DRAM
Claim 6
Magro (2022/0058141) teaches:
The memory controller of claim 5, wherein the second plurality of sub-arbiters comprises: a second page hit sub-arbiter for selecting decoded memory access requests to open pages of the second pseudo-channel; and P. 0063-64 Each arbiter 538, 539 (e.g. corresponding to sub-queues 804, 806 in FIG. 8) evaluate page table (PGT) information 600 to select a winning memory access request 606 and 608 that is provided to the selector 541. PGT information 600 represents whether a DRAM page is open. Page hit (PH) means that the page that is needed is already “ACTIVE”
a second page miss sub-arbiter for selecting decoded memory access requests to closed pages of precharged banks of the second pseudo-channel, P. 0063-64 PGT information 600 represents whether a DRAM page is in the closed state (i.e. meaning it was pre-charged) and thus no page on a bank is opened. Page Miss (PM) means that the page needed is not open in the DRAM
wherein the shared resource comprises a page conflict sub-arbiter for selecting decoded memory access requests to closed pages in banks with another page that is open in the first and second pseudo-channels. P. 0065 The first level arbitration is performed by arbiters 538 and 539 to select a winning entry to pass to the second level arbitration logic 612 [shared resource]; P. 0066 second level arbitration logic 612 picks one winner from arbiters 538 and 539 based on criteria such as page hit information. For example, page hits are favored over page misses.
Claim 7
Magro (2018/0018105) teaches:
The memory controller of claim 1, wherein the command queue stage comprises: a common command queue having an upstream port for receiving memory access requests for a selected one of the first pseudo-channel and the second pseudo-channel, and a downstream port. FIG. 6 and P. 0042 Address generator 522 sends the decoded memory access request including the decoded sub-channel number to command queue 520; P. 0043 Arbiter 538 picks eligible memory access requests independently for each sub-channel from command queue 520
Claim 8
Magro (2022/0058141) teaches:
The memory controller of claim 7, wherein the arbitration stage comprises: a plurality of sub-arbiters having an upstream port coupled to the command queue stage, and FIG. 5 and P. 0055 arbiters 538 and 539 select a command from command sub-queues 520 and 421 respectively
a downstream port coupled to the dispatch queue, for selecting decoded memory access requests of the first pseudo-channel and the second pseudo-channel. FIG. 5 and P. 0056 selector 541 picks the corresponding write access from either of the command sub-queues 520, 521 based on the command selected by each respective arbiter 538, 539 for dispatch to the memory channel
Claim 9
Magro (2022/0058141) teaches:
The memory controller of claim 8, wherein the plurality of sub-arbiters comprises: at least one dedicated sub-arbiter for each of the first and second pseudo-channels; and FIG. 5 and P. 0055 arbiters 538 and 539 select a command from command sub-queues 520 and 421 respectively; FIG. 8 and P. 0070 command sub-queues 800, 802 (analogous to sub-queues 520, 521) correspond to a first sub-channel and command sub-queues 804, 806 (e.g. a second instance of sub-queues 520, 521) correspond to a second sub-channel
Magro (2018/0018105) teaches:
at least one shared sub-arbiter for both the first pseudo-channel and the second pseudo-channel. P. 0043 and FIG. 5 Arbiter 538 picks eligible memory access requests independently for each sub-channel from command queue 520
Claim 10
Magro (2022/0058141) teaches:
The memory controller of claim 9, wherein the at least one dedicated sub-arbiter for each of the first and second pseudo-channels comprises: a page hit sub-arbiter for selecting decoded memory access requests to open pages of a respective pseudo-channel. P. 0063-64 Each arbiter 538, 539 (e.g. corresponding to sub-queues 800, 802 in FIG. 8) evaluate page table (PGT) information 600 to select a winning memory access request 606 and 608 that is provided to the selector 541. PGT information 600 represents whether a DRAM page is open. Page hit (PH) means that the page that is needed is already “ACTIVE”
Claim 11
Magro (2022/0058141) teaches:
The memory controller of claim 9, wherein the at least one shared sub-arbiter for both the first pseudo-channel and the second pseudo-channel comprises: a page conflict sub-arbiter for selecting decoded memory access requests to closed pages in banks with another page that is open in a respective pseudo-channel. P. 0065 The first level arbitration is performed by arbiters 538 and 539 to select a winning entry to pass to the second level arbitration logic 612 [shared resource]; P. 0066 second level arbitration logic 612 picks one winner from arbiters 538 and 539 based on criteria such as page hit information. For example, page hits are favored over page misses.
Claim 12
Magro (2018/0018105) teaches:
A data processing system, comprising:
a plurality of data processor cores each for generating memory access requests; FIG. 2 and P. 0034 CPU cores 212, 214 send memory access requests
a data fabric; and FIG. 2 and P. 0022 data fabric 250
at least one memory controller, FIG. 2 and P. 0025 memory controllers 290 (292, 294)
wherein the data fabric selectively routes the memory access requests and memory access responses between the plurality of data processor cores and the at least one memory controller, FIG. 2 and P. 0022 CPU cores 212, 214 provide memory access requests to data fabric 250; P. 0034 memory access requests are received from data fabric 250
wherein each of the at least one memory controller comprises:
a command queue stage for storing decoded memory access requests; P. 0025 and FIG. 2 Data fabric 250 routes memory access requests between any memory accessing agent (e.g. cores 212, 214) and memory controllers 290
an arbitration stage operable to select first and second memory commands from the command queue stage for first and second pseudo-channels using a shared resource […] FIG. 6 and P. 0042 Command queue 520 stores the decoded memory access request in an entry 610 in command queue 520, which has a first field 612 for storing the decoded sub-channel number; P. 0043 and FIG. 6 Arbiter 538 picks eligible memory access requests for issuance independently for each sub-channel from command queue 520, and uses timing block 534
a dispatch queue […] P. 0045 arbiter 538 picks a memory access request stored in command queue 520 and provides it to dispatch queue 514
Magro’105 does not explicitly teach the arbitration stage having a shared resource and dedicated resources for each of the first and second pseudo-channels.
Magro (2022/0058141) teaches:
an arbitration stage operable to select first and second memory commands from the command queue stage for first and second pseudo-channels using a shared resource and at least one dedicated resource for each of the first and second pseudo-channels; and FIG. 5 and P. 0056 selector 541 picks the corresponding write access from either of the command sub-queues 520, 521 based on the command selected by each respective arbiter 538, 539 for dispatch to the memory channel; FIG. 8 and P. 0070 command sub-queues 800, 802 (analogous to sub-queues 520, 521) correspond to a first sub-channel, command sub-queues 804, 806 (analogous to sub-queues 520, 521) correspond to a second sub-channel
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Magro’105 with the arbitration stage having a shared resource and dedicated resources for each of the first and second pseudo-channels taught by Magro’141
The motivation being a single controller may run two separate channels independently (see Magro’141 P. 0033)
The systems of Magro’105 and Magro’141 do not explicitly teach the dispatch queue sending data of the first and second memory commands in a time-multiplexed manner.
Zhang (2024/0053898) teaches:
a dispatch queue having first and second upstream ports for receiving the first memory commands and the second memory commands, and a downstream port for conducting first data of the first memory commands time-multiplexed with second data of the second memory commands. P. 0062 when the register and divided clock driver receives a read command (RD), it sends the read command (referred to CMD PC0 for pseudo channel PC0 and CMD PC1 for pseudo channel PC1) to pseudo channels PC0 and PC1 separately, and pseudo channels PC0 and PC1 send the data to the combined data buffer separately; P. 0057 high-bandwidth DDR DIMM 100 further includes a combined data buffer configured to interleave data of pseudo channels PC0 and PC1
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Magro’105 and Magro’141 with the dispatch queue sending data of the first and second memory commands in a time-multiplexed manner taught by Zhang
The motivation being data can be read faster and more effectively (see Zhang P. 0070)
The systems of Magro’105, Magro’141 and Zhang are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Magro’105 and Magro’141 with Zhang to obtain the invention as recited in claims 12-15.
Claim 13
Magro (2022/0058141) teaches:
The data processing system of claim 12, wherein: the command queue stage comprises:
a first command queue having an upstream port for receiving decoded memory access requests for the first pseudo-channel, and a downstream port; and FIG. 5 and P. 0059 Address generator 522 sends the decoded memory access request including the decoded sub-channel number to command sub-queues 520, 521 [command queue stage]; FIG. 8 and P. 0070 read and write queues are employed for each sub-channel such that each command sub-queues 800, 802 [first command queue] store both read and write memory access requests; P. 0058 selector 541 selects and dispatches a preferred memory access request 543 from among the provided memory access requests from the command sub-queues (e.g. queues 800 and 802)
a second command queue having an upstream port for receiving decoded memory access requests for the second pseudo-channel, and a downstream port, and the arbitration stage comprises: FIG. 8 and P. 0070 command sub-queues queues 804, 806 [second command queue] include similar components to receive decoded commands and dispatch a selected command
a first plurality of sub-arbiters for selecting decoded memory access requests of the first pseudo-channel; and FIG. 5 and P. 0056 selector 541 picks the corresponding write access from either of the command sub-queues 520, 521 based on the command selected by each respective arbiter 538, 539 for dispatch to the memory channel; FIG. 8 and P. 0070 command sub-queues 800, 802 (analogous to sub-queues 520, 521) correspond to a first sub-channel
a second plurality of sub-arbiters for selecting decoded memory access requests of the second pseudo-channel. FIG. 5 and P. 0056 selector 541 picks the corresponding write access from either of the command sub-queue 520 or command sub-queue 521 based on the command selected by each respective arbiter 538 or arbiter 539 for dispatch to the memory channel; FIG. 8 and P. 0070 command sub-queues 804, 806 (analogous to sub-queues 520, 521) correspond to a second sub-channel
Claim 14
Magro (2018/0018105) teaches:
The data processing system of claim 12, wherein: the command queue stage comprises:
a common command queue having an upstream port for receiving memory access requests for a selected one of the first pseudo-channel and the second pseudo-channel, and a downstream port, and FIG. 6 and P. 0042 Address generator 522 sends the decoded memory access request including the decoded sub-channel number to command queue 520; P. 0043 Arbiter 538 picks eligible memory access requests independently for each sub-channel from command queue 520
Magro (2022/0058141) teaches:
the arbitration stage comprises: a plurality of sub-arbiters having an upstream port coupled to the command queue stage, and FIG. 5 and P. 0055 arbiters 538 and 539 select a command from command sub-queues 520 and 421 respectively
a downstream port coupled to the dispatch queue, for selecting decoded memory access requests of the first pseudo-channel and the second pseudo-channel. FIG. 5 and P. 0056 selector 541 picks the corresponding write access from either of the command sub-queues 520, 521 based on the command selected by each respective arbiter 538, 539 for dispatch to the memory channel
Claim 15
Magro (2018/0018105) teaches:
The data processing system of claim 12, further comprising: a physical interface circuit coupled to an output of the dispatch queue; and FIG. 3 and P. 0030 Physical interface 316 connects memory channel controller 314 (which contains dispatch queue 514, see FIG. 5) to PHY 330 over a bus that conforms to the DDR-PHY
a memory coupled to the physical interface circuit comprising a multiplexed-rank dual inline memory module (MRDIMM). P. 0016 and FIG. 1 Memory channel 130 includes a set of dual inline memory modules (DIMMs) connected to a DDRx bus 132
Claim 16
Magro (2018/0018105) teaches:
A method for accessing a memory, comprising: storing memory access requests in a command queue stage, wherein each memory access request accesses one of a first pseudo-channel and a second pseudo-channel of the memory; P. 0034 and FIG. 5 Command queue 520 is a queue of memory access requests received, and stores the address fields decoded by address generator 522; FIG. 6 and P. 0042 a decoded memory access request has a first field 612 for storing the decoded sub-channel number
arbitrating among the memory access requests in an arbitration stage to obtain first arbitration winners for the first pseudo-channel and second arbitration winners for the second pseudo-channel using a shared resource […] P. 0043 and FIG. 6 Arbiter 538 picks eligible memory access requests for issuance independently for each sub-channel from command queue 520, and uses timing block 534
Magro’105 does not explicitly teach the arbitration stage having a shared resource and dedicated resources for each of the first and second pseudo-channels.
Magro (2022/0058141) teaches:
arbitrating among the memory access requests in an arbitration stage to obtain first arbitration winners for the first pseudo-channel and second arbitration winners for the second pseudo-channel using a shared resource and at least one dedicated resource for each of the first and second pseudo-channels; FIG. 5 and P. 0056 selector 541 picks the corresponding write access from either of the command sub-queues 520, 521 based on the command selected by each respective arbiter 538, 539 for dispatch to the memory channel; FIG. 8 and P. 0070 command sub-queues 800, 802 (analogous to sub-queues 520, 521) correspond to a first sub-channel, command sub-queues 804, 806 (analogous to sub-queues 520, 521) correspond to a second sub-channel
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Magro’105 with the arbitration stage having a shared resource and dedicated resources for each of the first and second pseudo-channels taught by Magro’141
The motivation being a single controller may run two separate channels independently (see Magro’141 P. 0033)
The systems of Magro’105 and Magro’141 do not explicitly teach the dispatch queue sending data of the first and second memory commands in a time-multiplexed manner.
Zhang (2024/0053898) teaches:
overlapping first memory access requests of the first pseudo-channel and second memory access requests of the second pseudo-channel on a command and address bus by a dispatch queue stage; and P. 0062 the first pseudo channel PC0 and the second pseudo channel PC1 send data associated with a host command to the combined data buffer separately; P. 0064 and FIG. 3 when data of both pseudo channel PC0 and pseudo channel PC1 arrive, the data D2 and D3 of pseudo channel PC0 is interleaved with the data D0 and D1 of pseudo channel PC
time-division multiplexing first data of the first memory access requests and second data of the second memory access requests by the dispatch queue stage. P. 0062 when the register and divided clock driver receives a read command (RD), it sends the read command (referred to CMD PC0 for pseudo channel PC0 and CMD PC1 for pseudo channel PC1) to pseudo channels PC0 and PC1 separately, and pseudo channels PC0 and PC1 send the data to the combined data buffer separately; P. 0057 high-bandwidth DDR DIMM 100 further includes a combined data buffer configured to interleave data of pseudo channels PC0 and PC1
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Magro’105 and Magro’141 with the dispatch queue sending data of the first and second memory commands in a time-multiplexed manner taught by Zhang
The motivation being data can be read faster and more effectively (see Zhang P. 0070)
The systems of Magro’105, Magro’141 and Zhang are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Magro’105 and Magro’141 with Zhang to obtain the invention as recited in claims 16-20.
Claim 17
Magro (2018/0018105) teaches:
The method of claim 16, wherein the storing comprises: storing memory access requests for both the first pseudo-channel and the second pseudo-channel in a common command queue. FIG. 6 and P. 0042 Address generator 522 sends the decoded memory access request including the decoded sub-channel number to command queue 520; P. 0043 Arbiter 538 picks eligible memory access requests independently for each sub-channel from command queue 520
Claim 18
Magro (2018/0018105) teaches:
The method of claim 16, wherein the arbitrating comprises: arbitrating among the memory access requests using an arbitration stage having a sub-arbiter common to both the first pseudo-channel and the second pseudo-channel. P. 0043 and FIG. 5 Arbiter 538 picks eligible memory access requests independently for each sub-channel from command queue 520
Claim 19
Zhang (2024/0053898) teaches:
The method of claim 16, wherein the overlapping and time-division multiplexing comprises: overlapping and time-division multiplexing using a dispatch queue common to both the first pseudo-channel and the second pseudo-channel. P. 0057 each group of pseudo channels PC0 and PC1 correspond to one combined data buffer
Claim 20
Magro (2018/0018105) teaches:
The method of claim 16, further comprising: receiving memory access requests by an address decoder circuit; P. 0034 and FIG. 5 Address generator 522 decodes addresses of memory access requests received from data fabric 250
decoding a corresponding pseudo-channel for each of the memory access requests; and P. 0041 address generator 522 decodes the address of each memory access request into a sub-channel number “SC”
sending a decoded memory access request with a decoded pseudo-channel to the command queue stage. P. 0042 Address generator 522 sends the decoded memory access request including the decoded sub-channel number to command queue 520
Response to Arguments
Applicant's arguments filed 10/16/2025 have been fully considered but they are not persuasive.
The arguments regarding claims 3-6, 8-11, 13 and 14 mention Magro’141 teaching an arbiter architecture that sorts commands by sub-channel in FIG. 8, but states the architecture does not time-multiplex data from both pseudo-channels.
The examiner respectfully notes the claims require the arbitration stage to 1) select first and second memory commands for first and second pseudo-channels, and 2) contain a shared resource and at least one dedicated resource per pseudo-channel. The arbitration state is not required to time-multiplex data for both the first and second commands. Further, the rejection is in view of Magro’105, Magro’141 and Zhang. Zhang P. 0062 teaches the first and second pseudo channels PC0 and PC1 sending their data to a combined data buffer separately, where the data from PC0 and PC1 are interleaved by the combined data buffer in P. 0064.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Takano et al (U.S. Patent No. 10949121) teaches a queue block for each bank including a sub-queue for each plane, where each of the queues store associated commands
Magro et al (U.S. Patent No. 10684969) teaches multiple arbitration stages for selecting a command from a command queue
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEPHANIE WU whose telephone number is (571)272-0257. The examiner can normally be reached 1pm to 6pm, and 10pm to 1am Eastern time (10am to 3pm, and 7pm to 10pm Pacific time).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rocio Del Mar Perez-Velez can be reached at (571) 270-5935. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STEPHANIE WU/Primary Examiner, Art Unit 2133
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