DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of claims 1-8 in the reply filed on 07/08/2026 is acknowledged. The traversal is on the ground(s) that the three claim groups all recite the same
Elements, are obvious variants, and capable of use together. This is not found persuasive because even though the claims may recite a few similar elements, each of the claim groups operate to have a different and distinct circuit design, a different/distinct mode of operation, and a different output that require different classification search areas and different search queries. Therefore, the requirement is still deemed proper and is therefore made final.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Pramanik et al (US 2005/0,112,597; hereinafter Pramanik) in view of Mirabella et al (US 2015/0,236,683; hereinafter Mirabella).
Regarding claim 1, Pramanik disclose an apparatus (300; Fig. 3) comprising:
voltage buffer circuitry (dynamic voltage bias circuit 320 to output the common terminal (CT) voltage at node 322) including: source follower circuitry (M11, 330) having a terminal; and a resistor (R3) having a first terminal (left side terminal of R3) and a second terminal (right side terminal of R3 at node 322), the first terminal of the resistor coupled to the terminal of the source follower circuitry (M11); and
driver circuitry (M13, M14, 362) including: a transconductance amplifier (M13, M14, 362); ¶ [0041]) having a terminal coupled to the second/right terminal of the resistor (R3) at node 322 (the voltage output by the dynamic biasing circuitry 140 is at a common terminal (CT) or first terminals of the input transistor pair of the transconductance amplifier stage 110 in Fig. 1, i.e. the CT or first terminals of the transistors M13 and M14 in Fig. 3, the right side terminal of resistor R3 coupled at node 322 is coupled to the first terminals of the transistors M13 and M14 of the transconductance amplifier, wherein the transconductance amplifier convert the input voltage from voltage follower circuit 140 to an output current); paragraphs [0027], [0045], [0002]). Pramanik do not explicitly disclose the dynamic voltage bias circuit is a voltage buffer circuit. In the same field of endeavor, Mirabella disclose a voltage buffer circuit (4) comprising a source follower (P12) and a resistor (R1) (Figs. 2, 3; ¶ [0027], clm. 6). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to do so in order to provide unity gain where the same voltage level is passed forward without boosting/cutting the signal strength and to prevent a weak signal source from being overloaded by matching impedance using low output resistance to drive the next stage of the circuit.
Regarding claim 6, Pramanik and Mirabella disclose apparatus of claim 1, wherein the transconductance amplifier (M13, M14, 362) includes: a first transistor (M13) having a first terminal (source terminal) and a second terminal (drain terminal/body terminal), the first terminal (source terminal) of the first transistor (M13) coupled to the second terminal (right terminal) of the resistor (R3) (¶ [0045]) and a second transistor (M25/M24/M14) having a terminal (source/source/body terminal respectively) coupled to the second terminal (drain/drain/body terminal respectively) of the first transistor (M13) (Pramanik; Figs. 3, 5; paras. [0042], [0063]).
Claims 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Pramanik et al (US 2005/0,112,597) in view of Mirabella et al (US 2015/0,236,683) further in view of Oishi (US 2008/0,197,926).
Regarding claim 2, Pramanik and Mirabella disclose the apparatus of claim 1, wherein the source follower circuitry (M11, 330) includes: current source circuitry (330) having a terminal (334); and a transistor (M11) having a terminal coupled to the first terminal (left terminal) of the resistor (R3) and a terminal coupled to the terminal (334) of the current source circuitry (330) (Pramanik, Fig. 3; ¶ [0043]). Pramanik and Mirabella do not disclose the transistor having a terminal coupled to the first terminal of the resistor and the terminal of the current source circuitry. In the same field of endeavor, Oishi disclose source follower circuitry including a transistor (21) having a terminal coupled to a first terminal of a resistor (23) and a terminal of a current source circuitry (24) (paras. [0046]-[0047]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to do so in order to provide an alternative design/configuration of a source follower circuit having stable voltage level of an output direct current component (Oishi; ¶ [0035]).
Regarding claim 3, Pramanik, Mirabella, and Oishi disclose the apparatus of claim 2, wherein the current source circuitry (330) further has a second terminal (332), and the apparatus further comprising a supply terminal (Vdd) coupled to the second terminal (332) of the current source circuitry (330) (Pramanik; paras. [0043]-[0044]).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Pramanik et al (US 2005/0,112,597) in view of Mirabella et al (US 2015/0,236,683) further in view of Alexandersen et al (WO 98/05,119).
Regarding claim 8, Pramanik and Mirabella disclose the apparatus of claim 1, wherein they do not disclose the apparatus further comprising power amplifier circuitry having a terminal coupled to the second terminal of the resistor and the terminal of transconductance amplifier. In the same field of endeavor, Alexandersen disclose an apparatus comprising power amplifier circuitry (PA1, PA2) having a terminal coupled to the second terminal of the resistor (e.g. 8 ohm load, resistor R) and the terminal of transconductance amplifier (A2, A1) (pg. 3, lines 8-10; pg. 5, lines 1-2, pg. 7, lines 25-27). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to do so in order to deliver high power to the load and provide high linearity and power efficiency by removing the effects of non-linearities in the amplifier stage (Alexandersen; abstract).
Allowable Subject Matter
Claims 4, 5 and 7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 4, Pramanik, Mirabella, and Oishi disclose the apparatus of claim 2, wherein the resistor (R3) is a first resistor, the terminal (gate terminal) of the transistor (M11) is a first terminal, the transistor further having a control terminal (drain terminal), and a capacitor (C1) having a terminal coupled to the control terminal of the transistor (M11) (Pramanik; Fig. 3). However, the cited prior art fails to further disclose or fairly suggest: the apparatus further comprising: a second resistor having a terminal; and the capacitor having a terminal coupled to the control terminal of the transistor and the terminal of the second resistor.
Regarding claim 5, Pramanik, Mirabella and Oishi disclose the apparatus of claim 2, wherein the resistor (23) is a first resistor, the transistor (21) is a first transistor, the terminal of the first transistor (21) is a first terminal, the first transistor (21) further having a control terminal, the apparatus further comprising: a second resistor (13) having a terminal, a second transistor (11) having a first terminal and a second terminal, the first terminal of the second transistor (11) coupled to the control terminal of the first transistor (21) (Oishi; Fig. 2). However, the cited prior art fails to further disclose or fairly suggest: the first terminal of the second transistor coupled to the control terminal of the first transistor and the terminal of the second resistor, and a third transistor having a terminal coupled to the second terminal of the second transistor.
Regarding claim 7, Pramanik and Mirabella disclose the apparatus of claim 6, wherein the terminal of the source follower circuitry (M11, 330) is a first terminal (control terminal of M11), the source follower circuitry (M11, 330) further having a second terminal (drain/source terminal), the terminal (source/source/body terminal) of the second transistor (M25/M24/M14 respectively) is a first terminal, the second transistor further having a control terminal (control terminal) (Figs. 3, 5; paragraphs [0042], [0063]). However, the cited prior art fails to further disclose or fairly suggest the apparatus further comprising a digital to analog converter (DAC) having a first terminal and a second terminal, the first terminal of the DAC coupled to the second terminal of the source follower circuitry, the second terminal of the DAC coupled to the control terminal of the second transistor.
Conclusion
5. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
- Bargroff et al (US 2024/0,348,211) disclose an amplifier bias circuit having a source follower transistor connected with a current source and a resistor that is responsive to variations in voltage and/or current in the circuit to output an adjustment gate bias voltage.
- Inohana (US 5,179,352) disclose an amplifier device for sufficiently reducing distortion comprising an amplifier circuit, a differential amplifier comprising a voltage to current converter having a predetermined mutual conductance.
- Hattori (US 2002/0,015,272) disclose a switch device having a digital to converter whose output is supplied to a terminal of a field effect transistor of the switch device through a voltage follower buffer circuit.
6. Any inquiry concerning this communication or earlier communications from the examiner should be directed to LANA N LE whose telephone number is (571) 272-7891. The examiner can normally be reached M-F 9:00am-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wesley Kim can be reached at (571) 272-7867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/LANA N LE/Primary Examiner, Art Unit 2648
Prosecution Insights