Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3-8, 10, 12-17, and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Drabinski et al. (U.S. PGPUB 20230215091).
With respect to claim 1, Drabinski et al. disclose a method for performing ray tracing operations, the method comprising:
storing a first shader context for a first ray associated with a first candidate hit (paragraph 516, Within the ray tracing acceleration circuitry 5110, call stacks 5121 and associated ray tracing data 4902 may be stored within a local ray tracing cache (RTC) 5107 or other local storage device for efficient access by the traversal circuitry 5102 and intersection circuitry 5103);
continuing traversal of a bounding volume hierarchy (“BVH”) without executing a shader for the first candidate hit (paragraph 461, the ray traversal circuitry 4005 defers shader invocations by accumulating multiple potential invocations and dispatching them in a larger batch, paragraph 463, At a given time during traversal each entry in the list may be used to generate a shader invocation. For example, the k-nearest intersection points can be accumulated on the traversal hardware 4005 and/or in the traversal state 4601 in memory, and hit shaders can be invoked for each element if the traversal is complete); and
in response to a first deferred shader execution trigger, executing a first shader based on the first shader context (paragraph 471, FIG. 47 illustrates how shader deferral/aggregator circuitry 4706 within the scheduler 4007 can defer scheduling of shaders associated with a particular SIMD/SIMT thread/lane until a specified triggering event has occurred. Upon detecting the triggering event, the scheduler 4007 dispatches the multiple aggregated shaders in a single SIMD/SIMT batch to the cores/EUs 4001).
With respect to claim 3, Drabinski et al. disclose the method of claim 1, wherein the first shader context stores an indication of which shader to execute (paragraph 515, various shaders can be referenced using a shader record which may include one or more pointers, vendor-specific metadata, and global arguments. In one embodiment, shader records are identified by shader record identifiers (SRI). In one embodiment, each executing instance of a shader is associated with a call stack 5203 which stores arguments passed between a parent shader and child shader, paragraph 516, Within the ray tracing acceleration circuitry 5110, call stacks 5121 and associated ray tracing data 4902 may be stored within a local ray tracing cache (RTC) 5107).
With respect to claim 4, Drabinski et al. disclose the method of claim 2, wherein the first shader context and the second shader context specify the same shader for different rays (paragraph 464, For the nearest-k use case the benefit of this approach is that instead of k-1 roundtrips to the SIMD core/EU 4001 and k-1 new ray spawn messages, all hit shaders are invoked from the same traversal thread during a single traversal operation on the traversal circuitry 4005, paragraph 516, Ray traversal circuitry 5102 traverses each ray through nodes of a BVH, working down the hierarchy of the BVH (e.g., through parent nodes, child nodes, and leaf nodes) to identify nodes/primitives traversed by the ray. Ray-BVH intersection circuitry 5103 performs intersection testing of rays, determining hit points on primitives, and generates results in response to the hits. The traversal circuitry 5102 and intersection circuitry 5103 may retrieve work from the one or more call stacks 5121. Within the ray tracing acceleration circuitry 5110, call stacks 5121 and associated ray tracing data 4902 may be stored within a local ray tracing cache (RTC) 5107).
With respect to claim 5, Drabinski et al. disclose the method of claim 1, wherein the first candidate hit comprises a hit detected for non-opaque geometry (paragraph 524, if a non-opaque object is hit or a procedural texture, the traversal circuitry 5002 saves the stack 5203-5204 to memory and executes the required shader).
With respect to claim 6, Drabinski et al. disclose the method of claim 1, further comprising: culling a second shader context based on a confirmed hit (paragraph 461, First, the ray traversal circuitry 4005 defers shader invocations by accumulating multiple potential invocations and dispatching them in a larger batch. In addition, certain invocations that turn out to be unnecessary may be culled at this stage).
With respect to claim 7, Drabinski et al. disclose the method of claim 6, wherein the confirmed hit has a time to intersection that is shorter than the time to intersection of the second shader context (paragraph 470, FIGS. 47-48 illustrate examples of a deferred model which invokes a single shader invocation on the SIMD cores/execution units 4001 with three shaders 4701. When preserved, all intersection tests are evaluated within the same SIMD/SIMT group). Fig. 47 shows time t=1, which is shorter than time t=2.
With respect to claim 8, Drabinski et al. disclose the method of claim 1, further comprising continuing traversal of the BVH for the first ray while executing an any hit shader (paragraph 455, When a leaf node is reached, the traversal circuitry calls the intersection circuitry at 4503 which, upon identifying a ray-triangle intersection, invokes an any hit shader at 4504).
With respect to claim 10, Drabinski et al. disclose a device (paragraph 111, FIG. 1 is a block diagram of a processing system 100) for performing ray tracing operations, the device comprising: a memory (paragraph 116, The memory device 120 can be a dynamic random-access memory (DRAM) device, a static random-access memory (SRAM) device, flash memory device, phase-change memory device, or some other memory device having suitable performance to serve as process memory. In one embodiment the memory device 120 can operate as system memory for the system 100, to store data 122 and instructions 121 for use when the one or more processors 102 executes an application or process); and a processor (paragraph 111, System 100 may be used in a single processor desktop system, a multiprocessor workstation system, or a server system having a large number of processors 102 or processor cores 107) configured to execute the method of claim 1; see rationale for rejection of claim 1.
With respect to claim 12, Drabinski et al. disclose the device of claim 10 for executing the method of claim 3; see rationale for rejection of claim 3.
With respect to claim 13, Drabinski et al. disclose the device of claim 11 for executing the method of claim 4; see rationale for rejection of claim 4.
With respect to claim 14, Drabinski et al. disclose the device of claim 10 for executing the method of claim 5; see rationale for rejection of claim 5.
With respect to claim 15, Drabinski et al. disclose the device of claim 10 for executing the method of claim 6; see rationale for rejection of claim 6.
With respect to claim 16, Drabinski et al. disclose the device of claim 15 for executing the method of claim 7; see rationale for rejection of claim 7.
With respect to claim 17, Drabinski et al. disclose the device of claim 10 for executing the method of claim 8; see rationale for rejection of claim 8.
With respect to claim 19, Drabinski et al. disclose a non-transitory computer-readable medium storing instructions that, when executed by a processor (paragraph 245, One or more aspects of at least one embodiment may be implemented by representative code stored on a machine-readable medium which represents and/or defines logic within an integrated circuit such as a processor), cause the processor to perform operations comprising the method of claim 1; see rationale for rejection of claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 11, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Drabinski et al. (U.S. PGPUB 20230215091) in view of Goudie et al. (U.S. PGPUB 20220114016).
With respect to claim 2, Drabinski et al. disclose the method of claim 1, wherein the first shader context and the second shader context are for different rays (paragraph 516, Ray traversal circuitry 5102 traverses each ray through nodes of a BVH, working down the hierarchy of the BVH (e.g., through parent nodes, child nodes, and leaf nodes) to identify nodes/primitives traversed by the ray. Ray-BVH intersection circuitry 5103 performs intersection testing of rays, determining hit points on primitives, and generates results in response to the hits. The traversal circuitry 5102 and intersection circuitry 5103 may retrieve work from the one or more call stacks 5121. Within the ray tracing acceleration circuitry 5110, call stacks 5121 and associated ray tracing data 4902 may be stored within a local ray tracing cache (RTC) 5107 or other local storage device for efficient access by the traversal circuitry 5102 and intersection circuitry 5103). However, Drabinski et al. do not expressly disclose the first shader is executed in parallel with a second shader associated with a second shader context.
Goudie et al., who also deal with ray tracing, disclose a method wherein the first shader is executed in parallel with a second shader associated with a second shader context (paragraph 10, To exploit the availability of parallel processing resources such as parallel SIMD lanes in a SIMD processor, different rays to be processed may be grouped together into tasks, where a given task may comprise multiple rays which are to be processed by the same shader program, and different tasks are processed by different shader programs).
Drabinski et al. and Goudie et al. are in the same field of endeavor, namely computer graphics.
Before the effective filing date of the claimed invention, it would have been obvious to apply the method wherein the first shader is executed in parallel with a second shader associated with a second shader context, as taught by Goudie et al., to the Drabinski et al. system, because by using a linked list, this provides a disjoint between the task builder (producer) and task scheduler (consumer), enabling the task scheduler to run independently from the task builder and thus mitigating the issue of stalling at this interface (paragraph 16 of Goudie et al.).
With respect to claim 11, Drabinski et al. as modified by Goudie et al. disclose the device of claim 10 for executing the method of claim 2; see rationale for rejection of claim 2.
With respect to claim 20, Drabinski et al. as modified by Goudie et al. disclose the non-transitory computer-readable medium of claim 19 for implementing the method of claim 2; see rationale for rejection of claim 2.
Claim(s) 9 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Drabinski et al. (U.S. PGPUB 20230215091) in view of Barnard et al. (U.S. PGPUB 20230023323).
With respect to claim 9, Drabinski et al. disclose the method of claim 1. However, Drabinski et al. do not expressly disclose adhering to an application programming interface determinism requirement based on a configuration switch.
Barnard et al., who also deal with ray tracing, disclose a method for adhering to an application programming interface determinism requirement based on a configuration switch (paragraph 170, This maintains a deterministic order of shader execution. It is the determinism of the order of shader execution, rather than a specific order itself, which is required by the ray tracing standards mentioned above).
Drabinski et al. and Barnard et al. are in the same field of endeavor, namely computer graphics.
Before the effective filing date of the claimed invention, it would have been obvious to apply the method of adhering to an application programming interface determinism requirement based on a configuration switch, as taught by Barnard et al., to the Drabinski et al. system, because determinism makes programming and debugging the system easier (paragraph 7 of Barnard et al.).
With respect to claim 18, Drabinski et al. as modified by Barnard et al. disclose the device of claim 10, wherein the processor is further configured to execute the method of claim 9; see rationale for rejection of claim 9.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. PGPUB 20220036639 to Rabbani Rankouhi et al. for a method of executing a ray tracing intersection instruction
U.S. PGPUB 20120133660 to Jang et al. for a method of including shader context data.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW GUS YANG whose telephone number is (571)272-5514. The examiner can normally be reached M-F 9 AM - 5:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kent Chang can be reached at (571)272-7667. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANDREW G YANG/Primary Examiner, Art Unit 2614
1/23/26