DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
2. The information disclosure statement (IDS) submitted on 09/30/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Amendment
3. Acknowledgement is made of amendment filed on December 16, 2025, in which claims 1, 10 and 19 are amended, and claims 1-20 are still pending.
Response to Arguments
4. Applicant's arguments, filed on December 16, 2025, with respect to Claims 1-20 have been fully considered and they are not persuasive.
5. With regards to arguments for independent claims 1, 10 and 19, applicants argue that Molnar et al. (US 2011/0090220 A1) and Jiao et al. (US 2007/0091088 A1) fail to disclose specifies which render target tiles are assigned to which screen space processors; modifying an active assignment configuration to replace the first assignment configuration with a second assignment configuration, wherein the modifying changes which render target tiles are associated to which screen space processors; The examiner respectfully agrees and moots in view of the new grounds of rejections regarding claims 1, 10 and 19, since in Ellis et al. (US 2013/0076761 A1) teaches (“In an embodiment the same set of paths, starting tiles, etc., is used for each render target (e.g. of a given sequence rendering targets (e.g. frames)) that is being rendered,” [0058] “Alternatively, it would, for example, be possible to explicitly construct lists of the sequences of tiles to be processed by each rendering processor (following their respective traversal paths) and then modify those lists as tiles are processed. This could be done, for example, by using m parallel doubly-linked lists (where m is the number of rendering processors) and then unlinking the relevant node from each list when a given tile is processed.” [0060] “Initially, all processors are inactive, so the tiles (the command lists for the tiles) are assigned to them by the tile allocator 23 in their order following their defined traversal paths. … This is illustrated in the sequence below, in which the tiles currently being processed are shown in bold and tiles that have been allocated are crossed out. Similarly, in the diagrams currently active tiles are shown in bold and dark gray, completed tiles in light gray, and the subscript for the tiles shows the processor that worked (or is working) on them.” [0140-0141] “In this embodiment the starting point, initial, tiles for each processor are assigned to the processors by distributing them as evenly as possible within the tile traversal order (sequence). Formally, processor p is assigned sequence index (pm)/n, expressed as an integer, where n is the number of processors, and m the number of tiles.” [0163] “When processor A completes its current tile, then it cannot simply be assigned the next slot in the sequence (as that tile is already completed). Instead, a free tile is chosen from one of the other free regions.” [0171] “the next processor with free slots ahead of it is found, and the middlemost free slot from that group chosen as the slot to allocate to processor A. The index and free slots for processor A are then updated, as are the free slots for the processor that processor A is "stealing" its new tiles from.” [0173]) Ellis teaches the tiles are assigned in the processors' order following their defined traversal path, and modify the lists as tiles are processed. Therefore, Ellis the arguments of the limitations for claims 1, 10 and 19 as it is recited.
Claim Rejections - 35 USC § 103
6. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
7. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
8. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
9. Claim(s) 1-6, 8-15 and17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Molnar et al. (US 2011/0090220 A1) in view of Ellis et al. (US 2013/0076761 A1).
10. With reference to claim 1, Molnar teaches A method for operating a graphics processing pipeline, (“FIG. 4 is a conceptual diagram of a graphics processing pipeline 400, that one or more of the PPUs 202 of FIG. 2 can be configured to implement, according to one embodiment of the present invention.” [0070]) Molnar also teaches the method comprising: distributing primitives to a set of screen space processors based on a first assignment configuration; (“The functions of the primitive distributer 420 may be performed by the primitive distribution unit 200.” [0071] “The primitive distribution unit 200 distributes processing tasks to each TPC 310 within the GPCs 208 via crossbar unit 210. In particular the primitive distribution unit 200 distributes primitives for object-space (geometry) processing by the TPCs 310. A pipeline manager 305 within each GPC 208 distributes the object-space processing tasks to streaming multiprocessors within each of the TPCs 310. Pipeline manager 305 may also be configured to control a work distribution crossbar interface 330 to distribute state parameters and commands to the TPCs 310 for object-space processing and screen-space processing.” [0036] “The series of instructions transmitted to a particular GPC 208 constitutes a thread, as previously defined herein, and the collection of a certain number of concurrently executing threads across the parallel processing engines (not shown) within an TPC 310 is referred to herein as a "warp" or "thread group." As used herein, a "thread group" refers to a group of threads concurrently executing the same program on different input data, with one thread of the group being assigned to a different processing engine within a TPC 310. A thread group may include fewer threads than the number of processing engines within the TPC 310, in which case some processing engines will be idle during cycles when that thread group is being processed.” [0038] “The primitive distribution unit 200 groups the primitives represented by the indices of vertices into batches for distribution to the TPCs 310. The batch encodes a number of sequential primitives represented as a set of vertex indices and primitive topology information, e.g., a list of primitives (either points, lines, triangles, or patches) that reference indices in the set of vertex indices. Batches may include 32 vertex pointers, which is large enough to benefit from vertex reuse, but small enough to balance the parallel geometry processing workload across the TPCs 310 while minimizing buffering needed to store the primitives for processing. The batches may be assigned to the TPCs 310 in the system in a round-robin fashion, e.g., TPCs 310 in a first GPC 208, TPCs 310 in a second GPC 208, and so on or a first TPC 310 in each of the GPCs 208, a second TPC 310 in each of the GPCs 208, and so on, or based on the current loading conditions for object-space primitive processing.” [0047] “A different GPC 208 is assigned to each screen tile set. In some embodiments each screen tile set includes statically mapped 16.times.16-pixel regions and GPC 208 performs setup and rasterization for up to one triangle per clock. A given GPC 208 is configured to rasterize each primitive that covers at least one pixel within the portion of the screen-space assigned to the given GPC 208. Large primitives may be rasterized by every GPC 208 while a small primitive may only be rasterized by one GPC 208.” [0050] “Each screen-space unit 336 has a GPC reorder buffer 344 that receives and stores the primitive data (excluding the GPC mask) output by the work distribution crossbar fabric 334.” [0067]) Molnar further teaches distributing the primitives to the set of screen space processors based on the second assignment configuration. (“The primitive distribution unit 200 distributes processing tasks to each TPC 310 within the GPCs 208 via crossbar unit 210. In particular the primitive distribution unit 200 distributes primitives for object-space (geometry) processing by the TPCs 310. A pipeline manager 305 within each GPC 208 distributes the object-space processing tasks to streaming multiprocessors within each of the TPCs 310. Pipeline manager 305 may also be configured to control a work distribution crossbar interface 330 to distribute state parameters and commands to the TPCs 310 for object-space processing and screen-space processing.” [0036] “The object-space processed primitive descriptors are routed through the work distribution crossbar fabric to GPCs 208 by the work distribution crossbar interface 330 based on the portion of the image that each object-space processed primitive affects. To make this assignment, the image, called the render target, is subdivided into small "screen tiles," and the screen tiles are partitioned into non-overlapping sets that cover the image. A different GPC 208 is assigned to each screen tile set. In some embodiments each screen tile set includes statically mapped 16.times.16-pixel regions and GPC 208 performs setup and rasterization for up to one triangle per clock. A given GPC 208 is configured to rasterize each primitive that covers at least one pixel within the portion of the screen-space assigned to the given GPC 208. Large primitives may be rasterized by every GPC 208 while a small primitive may only be rasterized by one GPC 208.” [0050] “The combination of the work distribution crossbar interface 330 and work distribution crossbar fabric 334 implements a distributed sorting structure that routes primitive data between the GPCs 208. The work distribution crossbar interface 330 routes the parallel streams of object-space processed primitive descriptors from the TPCs 310 performing object-space processing into parallel, ordered streams of primitive descriptors for the GPCs 208 performing screen-space processing via the work distribution crossbar fabric 334. Multiple work distribution crossbar interfaces 330 are coupled together through the work distribution crossbar fabric 334 in order to support multiple GPCs 208. Each work distribution crossbar interface 330 receives a stream of object-space processed primitive descriptors from each TPC 310 that performs object-space processing and routes each object-space processed primitive descriptor to one or more GPCs 208 for screen-space primitive processing via the work distribution crossbar fabric 334. Each work distribution crossbar interface 330 then reorders the primitive descriptors received by each GPC 208 that will perform the screen-space processing to match the API primitive ordering.” [0052] “Each screen-space unit 336 has a GPC reorder buffer 344 that receives and stores the primitive data (excluding the GPC mask) output by the work distribution crossbar fabric 334.” [0067])
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Molnar does not explicitly teach specifies which render target tiles are assigned to which screen space processors; modifying an active assignment configuration to replace the first assignment configuration with a second assignment configuration, wherein the modifying changes which render target tiles are associated to which screen space processors; This is what Ellis teaches (“In an embodiment the same set of paths, starting tiles, etc., is used for each render target (e.g. of a given sequence rendering targets (e.g. frames)) that is being rendered,” [0058] “Alternatively, it would, for example, be possible to explicitly construct lists of the sequences of tiles to be processed by each rendering processor (following their respective traversal paths) and then modify those lists as tiles are processed. This could be done, for example, by using m parallel doubly-linked lists (where m is the number of rendering processors) and then unlinking the relevant node from each list when a given tile is processed.” [0060] “Initially, all processors are inactive, so the tiles (the command lists for the tiles) are assigned to them by the tile allocator 23 in their order following their defined traversal paths. … This is illustrated in the sequence below, in which the tiles currently being processed are shown in bold and tiles that have been allocated are crossed out. Similarly, in the diagrams currently active tiles are shown in bold and dark gray, completed tiles in light gray, and the subscript for the tiles shows the processor that worked (or is working) on them.” [0140-0141] “In this embodiment the starting point, initial, tiles for each processor are assigned to the processors by distributing them as evenly as possible within the tile traversal order (sequence). Formally, processor p is assigned sequence index (pm)/n, expressed as an integer, where n is the number of processors, and m the number of tiles.” [0163] “When processor A completes its current tile, then it cannot simply be assigned the next slot in the sequence (as that tile is already completed). Instead, a free tile is chosen from one of the other free regions.” [0171] “the next processor with free slots ahead of it is found, and the middlemost free slot from that group chosen as the slot to allocate to processor A. The index and free slots for processor A are then updated, as are the free slots for the processor that processor A is "stealing" its new tiles from.” [0173]) Ellis teaches the tiles are assigned in the processors' order following their defined traversal path, and modify the lists as tiles are processed. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Ellis into Molnar, in order to improve tile allocation strategies in multi-processor, tile-based, graphics processing systems.
11. With reference to claim 2, Molnar teaches the first assignment configuration comprises a set of correlations between render target tiles and the screen space processors. (“The primitive distribution unit 200 distributes processing tasks to each TPC 310 within the GPCs 208 via crossbar unit 210. In particular the primitive distribution unit 200 distributes primitives for object-space (geometry) processing by the TPCs 310. A pipeline manager 305 within each GPC 208 distributes the object-space processing tasks to streaming multiprocessors within each of the TPCs 310. Pipeline manager 305 may also be configured to control a work distribution crossbar interface 330 to distribute state parameters and commands to the TPCs 310 for object-space processing and screen-space processing.” [0036] “The object-space processed primitive descriptors are routed through the work distribution crossbar fabric to GPCs 208 by the work distribution crossbar interface 330 based on the portion of the image that each object-space processed primitive affects. To make this assignment, the image, called the render target, is subdivided into small "screen tiles," and the screen tiles are partitioned into non-overlapping sets that cover the image. A different GPC 208 is assigned to each screen tile set. In some embodiments each screen tile set includes statically mapped 16.times.16-pixel regions and GPC 208 performs setup and rasterization for up to one triangle per clock. A given GPC 208 is configured to rasterize each primitive that covers at least one pixel within the portion of the screen-space assigned to the given GPC 208. Large primitives may be rasterized by every GPC 208 while a small primitive may only be rasterized by one GPC 208.” [0050])
12. With reference to claim 3, Molnar does not explicitly teach modifying the assignment configuration comprises changing a correlation of the set of correlations. This is what Ellis teaches (“Alternatively, it would, for example, be possible to explicitly construct lists of the sequences of tiles to be processed by each rendering processor (following their respective traversal paths) and then modify those lists as tiles are processed. This could be done, for example, by using m parallel doubly-linked lists (where m is the number of rendering processors) and then unlinking the relevant node from each list when a given tile is processed.” [0060] “In this embodiment the starting point, initial, tiles for each processor are assigned to the processors by distributing them as evenly as possible within the tile traversal order (sequence). Formally, processor p is assigned sequence index (pm)/n, expressed as an integer, where n is the number of processors, and m the number of tiles.” [0163] “When processor A completes its current tile, then it cannot simply be assigned the next slot in the sequence (as that tile is already completed). Instead, a free tile is chosen from one of the other free regions.” [0171] “the next processor with free slots ahead of it is found, and the middlemost free slot from that group chosen as the slot to allocate to processor A. The index and free slots for processor A are then updated, as are the free slots for the processor that processor A is "stealing" its new tiles from.” [0173]) Ellis teaches the tiles are assigned in the processors' order following their defined traversal path, and modify the lists as tiles are processed. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Ellis into Molnar, in order to improve tile allocation strategies in multi-processor, tile-based, graphics processing systems.
13. With reference to claim 4, Molnar teaches modifying the assignment configuration comprises changing a render target tile size. (“To make this assignment, the image, called the render target, is subdivided into small "screen tiles," and the screen tiles are partitioned into non-overlapping sets that cover the image. A different GPC 208 is assigned to each screen tile set. In some embodiments each screen tile set includes statically mapped 16.times.16-pixel regions and GPC 208 performs setup and rasterization for up to one triangle per clock. A given GPC 208 is configured to rasterize each primitive that covers at least one pixel within the portion of the screen-space assigned to the given GPC 208. Large primitives may be rasterized by every GPC 208 while a small primitive may only be rasterized by one GPC 208.” [0050] “The combination of the work distribution crossbar interface 330 and work distribution crossbar fabric 334 implements a distributed sorting structure that routes primitive data between the GPCs 208. The work distribution crossbar interface 330 routes the parallel streams of object-space processed primitive descriptors from the TPCs 310 performing object-space processing into parallel, ordered streams of primitive descriptors for the GPCs 208 performing screen-space processing via the work distribution crossbar fabric 334. Multiple work distribution crossbar interfaces 330 are coupled together through the work distribution crossbar fabric 334 in order to support multiple GPCs 208. Each work distribution crossbar interface 330 receives a stream of object-space processed primitive descriptors from each TPC 310 that performs object-space processing and routes each object-space processed primitive descriptor to one or more GPCs 208 for screen-space primitive processing via the work distribution crossbar fabric 334. Each work distribution crossbar interface 330 then reorders the primitive descriptors received by each GPC 208 that will perform the screen-space processing to match the API primitive ordering.” [0052] “The assignment of screen tile sets to the rasterizers distributes the rasterization workload. The screen tiles are N.times.M rectangles of samples within the render target. The choice of tile size is a tradeoff between load balancing, which improves with smaller screen tiles, and overhead, which improves with larger screen tiles. Overhead can take the form of primitives that need to be processed by multiple GPCs 208 because the tile size is too small or reduced texture locality. In one embodiment, the tile size is 16.times.16 pixels. The screen tiles are assigned to rasterizers 322 in an interleaved fashion to balance the workload across the rasterizers 322. For example, the upper-left corner tiles of the render target might be assigned to four rasterizers 322 corresponding to digits 0, 1, 2, and 3,” [0069])
14. With reference to claim 5, Molnar teaches modifying the assignment configuration is performed at a configuration boundary. (“The combination of the work distribution crossbar interface 330 and work distribution crossbar fabric 334 implements a distributed sorting structure that routes primitive data between the GPCs 208. The work distribution crossbar interface 330 routes the parallel streams of object-space processed primitive descriptors from the TPCs 310 performing object-space processing into parallel, ordered streams of primitive descriptors for the GPCs 208 performing screen-space processing via the work distribution crossbar fabric 334. Multiple work distribution crossbar interfaces 330 are coupled together through the work distribution crossbar fabric 334 in order to support multiple GPCs 208. Each work distribution crossbar interface 330 receives a stream of object-space processed primitive descriptors from each TPC 310 that performs object-space processing and routes each object-space processed primitive descriptor to one or more GPCs 208 for screen-space primitive processing via the work distribution crossbar fabric 334. Each work distribution crossbar interface 330 then reorders the primitive descriptors received by each GPC 208 that will perform the screen-space processing to match the API primitive ordering.” [0052] “The work distribution unit 330 includes a set of WWDXes 340 which each are coupled to one of the TPCs 310 to receive the object-space primitive descriptors, primitive bounding boxes, attribute buffer addresses, and end of batch flags from the TPCs 310 within a GPC 208. The TPC 310 computes a primitive bounding box for each primitive descriptor and the WWDX 340 receiving the bounding box compares it with the screen-space tiled mapping of the GPCs 208. A primitive bounding box contains the minimum and maximum X and Y screen-space dimensions for the smallest rectangle that completely contains the primitive. Based on the bounding box size and position, the WWDX 340 determines which GPCs 208 might need to process the primitive by intersecting the screen tile set for each GPC 208 with the bounding box. The WWDX 340 sets bits corresponding to the particular GPCs 208 that should receive the primitive in a GPC (distribution) mask. Small primitives (i.e., primitives that affect only one or a few pixels) will generally affect only one screen tile, and thus will be sent to a single GPC 208. Larger primitives, which affect several screen tiles, will be sent to multiple GPCs 208. In the limit, with small primitives, when there are C GPCs 208, the system can process C different primitives concurrently.” [0060])
15. With reference to claim 6, Molnar teaches the configuration boundary comprises a draw call or a command buffer execution. (“The work distribution unit 330 includes a set of WWDXes 340 which each are coupled to one of the TPCs 310 to receive the object-space primitive descriptors, primitive bounding boxes, attribute buffer addresses, and end of batch flags from the TPCs 310 within a GPC 208. The TPC 310 computes a primitive bounding box for each primitive descriptor and the WWDX 340 receiving the bounding box compares it with the screen-space tiled mapping of the GPCs 208. A primitive bounding box contains the minimum and maximum X and Y screen-space dimensions for the smallest rectangle that completely contains the primitive. Based on the bounding box size and position, the WWDX 340 determines which GPCs 208 might need to process the primitive by intersecting the screen tile set for each GPC 208 with the bounding box. The WWDX 340 sets bits corresponding to the particular GPCs 208 that should receive the primitive in a GPC (distribution) mask. Small primitives (i.e., primitives that affect only one or a few pixels) will generally affect only one screen tile, and thus will be sent to a single GPC 208. Larger primitives, which affect several screen tiles, will be sent to multiple GPCs 208. In the limit, with small primitives, when there are C GPCs 208, the system can process C different primitives concurrently.” [0060] “The functions of the primitive distributer 420 may be performed by the primitive distribution unit 200. Primitive distributer 420 receives pointers to primitive index lists stored in memory. The entries in these index lists point into lists of vertex attributes (vertex buffers), also stored in memory. Because primitives are stored compactly and many primitives can be passed to the primitive distributer 420 in a single draw call, indexed primitive lists and vertex buffers are the most efficient way to convey geometry to the graphics pipeline 400.” [0071])
16. With reference to claim 8, Molnar teaches rendering geometry based on the first assignment configuration and rendering geometry based on the second assignment configuration. (“The primitive distribution unit 200 groups the primitives represented by the indices of vertices into batches for distribution to the TPCs 310. The batch encodes a number of sequential primitives represented as a set of vertex indices and primitive topology information, e.g., a list of primitives (either points, lines, triangles, or patches) that reference indices in the set of vertex indices. Batches may include 32 vertex pointers, which is large enough to benefit from vertex reuse, but small enough to balance the parallel geometry processing workload across the TPCs 310 while minimizing buffering needed to store the primitives for processing. The batches may be assigned to the TPCs 310 in the system in a round-robin fashion, e.g., TPCs 310 in a first GPC 208, TPCs 310 in a second GPC 208, and so on or a first TPC 310 in each of the GPCs 208, a second TPC 310 in each of the GPCs 208, and so on, or based on the current loading conditions for object-space primitive processing. The object-space primitive processing comprises geometry processing, including world-to-screen-space transformation, clipping, culling, and vertex shading operations. The result of the parallel object-space primitive processing performed by the TPCs 310 is batches of graphics primitive descriptors that encode transformed vertices defining points, lines, and triangles. The primitive descriptor contains information about the geometric primitive necessary for rendering the pixels covered by the primitives: type of primitive (point, line, triangle), vertex indices that point to buffers storing the vertex attributes, control flags.” [0047] “To make this assignment, the image, called the render target, is subdivided into small "screen tiles," and the screen tiles are partitioned into non-overlapping sets that cover the image. A different GPC 208 is assigned to each screen tile set. In some embodiments each screen tile set includes statically mapped 16.times.16-pixel regions and GPC 208 performs setup and rasterization for up to one triangle per clock. A given GPC 208 is configured to rasterize each primitive that covers at least one pixel within the portion of the screen-space assigned to the given GPC 208. Large primitives may be rasterized by every GPC 208 while a small primitive may only be rasterized by one GPC 208.” [0050] “The combination of the work distribution crossbar interface 330 and work distribution crossbar fabric 334 implements a distributed sorting structure that routes primitive data between the GPCs 208. The work distribution crossbar interface 330 routes the parallel streams of object-space processed primitive descriptors from the TPCs 310 performing object-space processing into parallel, ordered streams of primitive descriptors for the GPCs 208 performing screen-space processing via the work distribution crossbar fabric 334. Multiple work distribution crossbar interfaces 330 are coupled together through the work distribution crossbar fabric 334 in order to support multiple GPCs 208. Each work distribution crossbar interface 330 receives a stream of object-space processed primitive descriptors from each TPC 310 that performs object-space processing and routes each object-space processed primitive descriptor to one or more GPCs 208 for screen-space primitive processing via the work distribution crossbar fabric 334. Each work distribution crossbar interface 330 then reorders the primitive descriptors received by each GPC 208 that will perform the screen-space processing to match the API primitive ordering.” [0052] “Overhead can take the form of primitives that need to be processed by multiple GPCs 208 because the tile size is too small or reduced texture locality. In one embodiment, the tile size is 16.times.16 pixels. The screen tiles are assigned to rasterizers 322 in an interleaved fashion to balance the workload across the rasterizers 322. For example, the upper-left corner tiles of the render target might be assigned to four rasterizers 322 corresponding to digits 0, 1, 2, and 3,” [0069])
17. With reference to claim 9, Molnar teaches distributing the primitives to the set of screen space processors based on the first assignment configuration includes distributing a primitive to each screen space processor that is associated with a render target overlapped by the primitive. (“The primitive distribution unit 200 distributes processing tasks to each TPC 310 within the GPCs 208 via crossbar unit 210. In particular the primitive distribution unit 200 distributes primitives for object-space (geometry) processing by the TPCs 310. A pipeline manager 305 within each GPC 208 distributes the object-space processing tasks to streaming multiprocessors within each of the TPCs 310. Pipeline manager 305 may also be configured to control a work distribution crossbar interface 330 to distribute state parameters and commands to the TPCs 310 for object-space processing and screen-space processing.” [0036] “The object-space processed primitive descriptors are routed through the work distribution crossbar fabric to GPCs 208 by the work distribution crossbar interface 330 based on the portion of the image that each object-space processed primitive affects. To make this assignment, the image, called the render target, is subdivided into small "screen tiles," and the screen tiles are partitioned into non-overlapping sets that cover the image. A different GPC 208 is assigned to each screen tile set. In some embodiments each screen tile set includes statically mapped 16.times.16-pixel regions and GPC 208 performs setup and rasterization for up to one triangle per clock. A given GPC 208 is configured to rasterize each primitive that covers at least one pixel within the portion of the screen-space assigned to the given GPC 208. Large primitives may be rasterized by every GPC 208 while a small primitive may only be rasterized by one GPC 208.” [0050] “Each screen-space unit 336 has a GPC reorder buffer 344 that receives and stores the primitive data (excluding the GPC mask) output by the work distribution crossbar fabric 334.” [0067])
18. Claim 10 is similar in scope to claim 1, and thus is rejected under similar rationale. Molnar additionally teaches A system comprising: a set of screen space processors; and a redistributor processor (“Various embodiments of the invention include a system for rendering primitives in parallel. The system includes a processor that is configured to receive primitives in a first order where the primitives are encoded as a list of vertex indices, and distribute primitive descriptors that represent the primitives for parallel processing in object-space to produce multiple streams, each stream including object-space processed primitive descriptors. The processor is configured to route the multiple streams of object-space processed primitives based on screen-space positions to produce a first stream of processed primitive descriptors representing primitives that intersect a first portion of a screen and a second stream of processed primitive descriptors representing primitives that intersect a second portion of the screen. The processor is configured to reorder the object-space processed primitive descriptors in the first stream to match the first order, producing a reordered first stream of object-space processed primitive descriptors and reorder the object-space processed primitive descriptors in the second stream to match the first order, producing a reordered second stream of object-space processed primitive descriptors.” [0009] “some or all of PPUs 202 in parallel processing subsystem 112 are graphics processors with rendering pipelines that can be configured to perform various tasks related to generating pixel data from graphics data supplied by CPU 102 and/or system memory 104 via memory bridge 105 and bus 113, interacting with local parallel processing memory 204 (which can be used as graphics memory including, e.g., a conventional frame buffer) to store and update pixel data, delivering pixel data to display device 110, and the like. In some embodiments, parallel processing subsystem 112 may include one or more PPUs 202 that operate as graphics processors and one or more other PPUs 202 that are used for general-purpose computations.” [0023] “The primitive distribution unit 200 distributes processing tasks to each TPC 310 within the GPCs 208 via crossbar unit 210. In particular the primitive distribution unit 200 distributes primitives for object-space (geometry) processing by the TPCs 310. A pipeline manager 305 within each GPC 208 distributes the object-space processing tasks to streaming multiprocessors within each of the TPCs 310.” [0036] “Each screen-space unit 336 has a GPC reorder buffer 344 that receives and stores the primitive data (excluding the GPC mask) output by the work distribution crossbar fabric 334.” [0067])
19. Claims 11-15 are similar in scope to claims 2-6, and they are rejected under similar rationale.
20. Claims 17 and 18 are similar in scope to claims 8 and 9, and they are rejected under similar rationale.
21. Claim 19 is similar in scope to claim 1, and thus is rejected under similar rationale. Molnar additionally teaches A non-transitory computer-readable medium storing instructions that, when executed by a processor, cause the processor to perform operations (“The program(s) of the program product define functions of the embodiments (including the methods described herein) and can be contained on a variety of computer-readable storage media.” [0096] “A computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to render primitives in parallel, by performing the steps” claim 11)
22. Claim 20 is similar in scope to claim 2, and thus is rejected under similar rationale.
23. Claim(s) 7 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Molnar et al. (US 2011/0090220 A1) and Ellis et al. (US 2013/0076761 A1), as applied to claims 1 and 10 above, and further in view of Jiao et al. (US 2007/0091088 A1).
24. With reference to claim 7, the combination of Molnar and Ellis does not explicitly teach modifying the assignment configuration is performed at a request of a driver or an application. This is what Jiao teaches (“In dynamic scheduling configuration, the driver may still provide the initial assignment (otherwise, if none is specified, the hardware will choose the hardware default assignment and start from there), and send commands to notify the hardware to re-evaluate the assignment under certain circumstances, or force an assignment and change back to static configuration. … as the graphics processor undergoes state changes, then the various shader units may be completely reassigned anew, to perform operations in the new graphics state. For example, a change of shading characteristics on different rending objects with different shading characteristics, lighting conditions may change, a new object in a graphics scene may be rendered, as well as a variety of other events may occur that lead to a change in the state of the graphics processor, such that the processing essentially begins anew.” [0070-0071] “The scheduler 300 further includes logic 364 for reassigning execution units to a different shader. As should be appreciated, such a reassignment would include the execution of steps necessary to stop assigning any new tasks that belong to previous shader stage assigned to the EU and start draining the EU for the existing tasks/threads. Since the EU hardware support two shader contexts, it allows the tasks that belong to the new shader stage assigned to the EU to start coming in before the previous shader context ends. (This is for preventing pipeline stall due to shader stage change). For example, assume that execution unit 1 302 and execution unit 2 304 are presently assigned to the vertex shader 320. Assume further that the pixel shader 340 is determined by the scheduler 300 to be in a bottlenecked condition, and further that the scheduler 300 seeks to reassign execution unit 2 304 to the pixel shader 340. Before sending tasks from the pixel shader 340 to the newly assigned execution unit 304. Alternatively, the scheduler 300 may just stop sending new tasks in to execution unit 304, and once all tasks currently being carried out in execution unit 304 have completed, then execution unit 304 may be reassigned to pixel shader 340, and new tasks (mentioned earlier) can start being assigned.” [0075]) Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Jiao into the combination of Molnar and Ellis, in order to perform the dynamic allocation or reallocation of processing resources.
25. Claim 16 is similar in scope to claim 7, and thus is rejected under similar rationale.
Conclusion
26. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michelle Chin whose telephone number is (571)270-3697. The examiner can normally be reached on Monday-Friday 8:00 AM-4:30 PM.
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/MICHELLE CHIN/
Primary Examiner, Art Unit 2614