DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/26/2026 has been entered.
Claim Rejections - 35 USC § 112 1st
Claims 1-20 are rejected under 35 U.S.C. 112, first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor(s), at the time the application was filed, had possession of the claimed invention. There is no definition of the term ‘interrupt target’ in Instant Application (IA). Because lack of definition and lack of discourse around the term ‘interrupt target’, it appears, IA’s invention is not about interrupt targets. For the purpose of examination, the term is construed as a part of descriptive language that admits common sense or what is well known in the art. For instance, two (or more) consecutive interrupts either request same service or different services; that is just common sense. Determining either type (same or different) of service is also common sense or obvious since the determination is merely binary, yes or no.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 9-10, and 18-21 are rejected under 35 U.S.C. 103 as being unpatentable over Danko (U.S. Publication 2012/0210104), hereinafter Danko in view of Lai et al. (U.S. Publication 2001/0032287), hereinafter Lai.
Referring to claim 1, Danko teaches, as claimed, a device comprising:
a processor (see Fig. 7, Processor 702) configured to receive interrupts (a processor with suspendable interrupts, see Paragraph 15) from a processor component (see Fig. 7, Suspendable Interrupt Control 722); and
a control circuit (see Fig. 7, Interrupt Controller 710) configured to delay (maximum delay, see Paragraph 39), in response to the processor entering an idle state (Place processor in idle state, see Fig. 4, Step 410), the processor component from sending interrupts to the processor (Set masking of suspendable interrupts, see Fig. 4, Step 408); and
merge one or more delayed interrupts (interrupts may be combined, see Paragraph 43).
Danko does not disclose expressly interrupts that share a same interrupt target.
Lai does disclose interrupts (multiple interrupt requests, see Paragraph 13) that share a same interrupt target (same interrupt service routine, see Paragraph 13; Note, an interrupt service routine is the target of the interrupt request).
At the time of the invention it would have been obvious to a person of ordinary skill in the art to incorporate Lai’s message signaled interrupt concept into Danko’s interrupt system.
The suggestion/motivation for doing so would have been to more effectively support multiple interrupts from different peripherals (inevitable to share the interrupt signals, see Lai Abstract and Paragraph 7).
As to claim 2, the modification teaches the device of claim 1, wherein the processor component is configured to delay sending interrupts to the processor by using a delay timer (Trigger Time, see Danko Fig. 5a and Paragraph 32) for each interrupt.
As to claim 3, the modification teaches the device of claim 2, wherein a delay time for the delay timer corresponds to an idle duration (Max. delay; see Danko Fig. 5a and Paragraph 32; Note, a duration can be calculated given timers) of the idle state of the processor.
As to claim 4, the modification teaches the device of claim 3, wherein the idle duration corresponds to a duty cycle (read cycle, see Lai Paragraph 11; Note, a read cycle like write or execute cycle is a duty cycle) policy (see Danko will execute, see Paragraph 41, Fig. 7, Scheduler 720; Note, it is implicit that a scheduler for OS which is for processor corresponds to duty cycles policy of the processor) for the processor.
As to claim 5, the modification teaches the device of claim 2, wherein a delay time for the delay timer corresponds to a delay tolerance (tolerant timers, see Paragraph 43) based on a priority (priority levels, see Paragraph 21) of a corresponding interrupt (suspendable interrupts, see Paragraphs 21 and 43).
As to claim 6, the modification teaches the device of claim 2, wherein the processor component is configured to send an interrupt (serviced once the interrupt signal 512 is received, see Danko Paragraph 33) when a corresponding delay timer expires (timer 2 expires, see Danko Paragraph 33).
As to claim 7, the modification teaches the device of claim 2, wherein the processor component is configured to cancel the delay timers (can be changed to the smaller value… maximum delay value associated with a suspendable interrupt to be changed, see Danko Paragraph 24; Note, when original maximum delay value is changed to smaller value, the difference of delay time has been effectively cancelled) when the processor exits (until processor is placed in the wake state, see Danko Paragraph 24) the idle state.
As to claim 9, the modification teaches the device of claim 1, wherein the control circuit is configured to resume, in response to the processor exiting the idle state (see Danko Fig. 6, Step 622 or Step 614), the processor component sending interrupts to the processor (see Danko Fig. 6. Step 624 or Step 616).
As to claim 10, the modification teaches the device of claim 1, wherein the processor component is configured to send a high priority (priority levels, see Danko Paragraph 21) interrupt to the processor during the idle state.
As to claim 18, Danko teaches the method comprising:
entering an idle state (Place processor in idle state, see Fig. 4, Step 410) of a processor (see Fig. 7, Processor 702);
coalescing (interrupts may be combined, see Paragraph 43), in response to entering the idle state, interrupts to the processor during the idle state, wherein the coalescing includes merging (see Paragraph 43; Note, of course, coalescing includes merging or combining) one or more delayed interrupts;
exiting the idle state of the processor (wake, see Fig. 4, Step 414); and
resuming (unmask, see Fig. 4, Step 416), in response to exiting the idle state, interrupts to the processor.
Danko does not disclose expressly interrupts that share a same interrupt target.
Lai does disclose interrupts (multiple interrupt requests, see Paragraph 13) that share a same interrupt target (same interrupt service routine, see Paragraph 13; Note, an interrupt service routine is the target of the interrupt request).
At the time of the invention it would have been obvious to a person of ordinary skill in the art to incorporate Lai’s message signaled interrupt concept into Danko’s interrupt system.
The suggestion/motivation for doing so would have been to more effectively support multiple interrupts from different peripherals (inevitable to share the interrupt signals, see Lai Abstract and Paragraph 7).
As to claim 19, the modification teaches the method of claim 18, wherein coalescing interrupts comprises delaying interrupts using delay timers having delay times corresponding to at least one of an idle duration (Max. delay; see Danko Fig. 5a and Paragraph 32; Note, a duration can be calculated given timers) of the processor or a delay tolerance based on a priority of a corresponding interrupt (Note, mere alternative).
As to claim 20, the modification teaches the method of claim 19, further comprising sending an interrupt at an earlier of a corresponding delay timer expiring (timer 2 expires, see Paragraph 33) or exiting the idle state of the processor Note, mere alternative).
As to claim 21, the modification teaches, as claimed, the device of claim 1, wherein the control circuit is configured to merge (interrupts may be combined, see Danko Paragraph 43) the one or more delayed interrupts (Set masking of suspendable interrupts, see Danko Fig. 4, Step 408; Note, suspendable interrupts are delayed interrupts) into a single delayed interrupt by combining interrupts having a same target service routine (the same interrupt service routine, see Lai Paragraph 13).
Claims 8 and 12-17 are rejected under 35 U.S.C. 103 as being unpatentable over Danko/Lai modification further in view of Tsirkin (U.S. Publication 2024/0086229), hereinafter Tsirkin.
As to claim 8, Danko/Lai modification teaches the device of claim 1, wherein the control circuit is configured to allow, in response to the processor exiting (see Danko Fig. 6, Step 622 or Step 614; Note, waking is exiting the idle state) the idle state, the processor component to send interrupts (see Danko Fig. 6, Step 604, Step, 620 and Step 612; Note, when woke processor can receive interrupt signal) to the processor.
The Danko/Lai modification does not expressly disclose in response to exiting the idle state, sending delayed interrupts.
Tsirkin does disclose send, in response to the processor exiting the idle state (storing the interrupt in the interrupt register until an event occurs, such as the virtual machine waking up, see Paragraph 12), delayed interrupts (interrupt is to be delayed, see Paragraph 12).
At the time of the invention it would have been obvious to a person of ordinary skill in the art to incorporate Tsirkin’s delaying of certain interrupts into Danko masked/unmasked interrupts.
The suggestion/motivation for doing so would have been to allow for different priority levels (see Danko Paragraph 21).
Referring to claim 12, Danko teaches, as claimed, a system comprising:
a processor (see Fig. 7, Processor 702);
a control circuit (see Fig. 7, Interrupt Controller 710) configured to initiate entry to an idle state (Place processor in idle state, see Fig. 4, Step 410) of the processor for an idle duration (maximum delay, see Paragraph 39) and initiate exit of the idle state after the idle duration elapses (Monitor time, see Fig. 4, Step 412);
merge one or more delayed interrupts (interrupts may be combined, see Paragraph 43) based on a type of interrupt (masked state of interrupt, see Paragraph 23); and
a plurality of processor components (see Fig. 7, Applications 716) each configured to:
delay (see Fig. 5a, Max. delay), in response to the processor entering the idle state, sending interrupts (masked interrupt, see Paragraph 23; Note, masked interrupts are delayed and unmasked interrupts wakes processor and get serviced) to the processor; and
in response to the processor exiting the idle state after the idle duration, resume sending interrupts.
Danko does not disclose expressly interrupts that share a same interrupt target.
Lai does disclose interrupts (multiple interrupt requests, see Paragraph 13) that share a same interrupt target (same interrupt service routine, see Paragraph 13; Note, an interrupt service routine is the target of the interrupt request).
At the time of the invention it would have been obvious to a person of ordinary skill in the art to incorporate Lai’s message signaled interrupt concept into Danko’s interrupt system.
The suggestion/motivation for doing so would have been to more effectively support multiple interrupts from different peripherals (inevitable to share the interrupt signals, see Lai Abstract and Paragraph 7).
Still, the Danko/Lai modification does not disclose expressly send, in response to the processor exiting the idle state, delayed interrupts.
Tsirkin does disclose send, in response to the processor exiting the idle state (storing the interrupt in the interrupt register until an event occurs, such as the virtual machine waking up, see Paragraph 12), delayed interrupts (interrupt is to be delayed, see Paragraph 12).
At the time of the invention it would have been obvious to a person of ordinary skill in the art to incorporate Tsirkin’s delaying of certain interrupts into Danko masked/unmasked interrupts.
The suggestion/motivation for doing so would have been to allow for different priority levels (see Danko Paragraph 21).
As to claim 13, the modification teaches the system of claim 12, wherein:
each of the plurality of processor components is configured to delay sending interrupts to the processor by using a delay timer (see Danko Fig. 5a, Timer and Max. delay) for each interrupt;
a delay time (see Danko Fig. 5a, .5 or 1.2) for the delay timer corresponds to at least one of the idle duration or a delay tolerance (tolerant timers, see Danko Paragraph 43) based on a priority (priority levels, see Danko Paragraph 21) of a corresponding interrupt (the interrupt is to be delayed, see Danko Paragraph 12); and
each of the plurality of processor components is configured to send an interrupt when a corresponding delay timer expires (timer 2 expires, see Danko Paragraph 33).
As to claim 14, the modification teaches the system of claim 13, wherein each of the plurality of processor components is configured to cancel the delay timers (can be changed to the smaller value… maximum delay value associated with a suspendable interrupt to be changed, see Danko Paragraph 24; Note, when original maximum delay value is changed to smaller value, the difference of delay time has been effectively cancelled) in response to an instruction (instructions, see Danko Paragraph 19) from the control circuit to send delayed interrupts (suspendable interrupt, see Paragraph 19).
As to claim 15, the modification teaches the system of claim 12, wherein at least one of the plurality of processor components is configured to send a high priority (priority levels, see Danko Paragraph 21) interrupt to the processor during the idle state.
As to claim 16, the modification teaches the system of claim 12, wherein the idle duration corresponds to a duty cycle (see Fig. 7, Scheduler 720; Note, duty cycle indicates the fraction of time a resource is available or not which is what a scheduler manage) policy managed by the control circuit for the processor.
As to claim 17, the modification teaches the system of claim 12, wherein the control circuit is configured to hold delayed interrupts in one or more buffers (see Tsirkin Fig. 2, Register 105) and merge (combined, see Danko Paragraph 43) buffered interrupts based on type of interrupts (masked state of interrupt, see Danko Paragraph 23).
Response to Arguments
Applicant's arguments filed 2/26/2026 have been fully considered but they are moot in view of new grounds of rejections.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Hyun Nam whose telephone number is (571) 270-1725 and fax number is (571) 270-2725. The examiner can normally be reached on Monday through Friday 8:30 AM to 5:00 PM EST. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on (571) 270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HYUN NAM/Primary Examiner, Art Unit 2183