DETAILED ACTION
This office action is in response to a Request for Continued Examination (RCE) filed 12/18/2025 application 18/620,776 filed 3/28/2004 that claims priority to PCT/CN2021/078387 filed 3/1/2021.
Claims 1, 4, 14, and 19 have been cancelled. No claims are new. Claims 2, 5, 12 15, 17, and 20 have been amended. Thus claims 2-3, 5-13, 15-18, and 20-21 have been examined.
The objections and rejections from the prior correspondence that are not restated herein are withdrawn.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/18/2025 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3, 5-8, 10-13, 15-18, and 20-21 are rejected Under U.S.C 103 as being unpatentable over Sinclair (Sinclair et al., US Pub. No: US 2014/0189207 A1) and further in view of Goto et al., US 2010/0058003 A1)
Regarding claim 2, Sinclair teaches A memory system, comprising: one or more memory devices; (Sinclair Figs. 1, 2, and 4A and supporting paras [0047]-[0049] and [0052-0055] discloses a multi-layer memory organization within Storage Device 102.) and processing circuitry coupled with the one or more memory devices and configured to cause the memory system to: (Sinclair Fig. 4A and paras [0052]-[0055] discloses Storage device 102 contains Processor 424 that is an example of processing circuitry configured to execute the disclosed processes)
receive a command to write data to the one or more memory devices, (Sinclair [0056] discloses the system receives write requests from a host (at step 502) directed to write data to the flash memory layers within Storage Device 120 (at step 508) where Storage Device 120 is an example of one or more memory device.) the data having a data size; (Sinclair [0056] discloses the flash memory target is selected based on the size of the data )
add the data to a first buffer, a second buffer, or a combination thereof based at least in part on the data size and a threshold size, (Sinclair [0050] and [0056] discloses that data will be deemed random and written to the first memory layer (a second buffer) if the size is less than a full metapage, otherwise it will be judged as sequential and written to the second memory layer(a first buffer).) the first buffer storing a first set of data and the second buffer storing a second set of data (Sinclair [0053]-[0056] discloses the first memory layer (the second buffer) may SLC data storing 1 bit per cell data (a second set of data) and the second memory layer (the first buffer) may store 2 bits per cell data (a first set of data).) based at least in part on adding the data to the first buffer, the second buffer, or a combination thereof; (Sinclair [0050] and [0056] discloses the data will be written to the second layer (the first buffer storing a first set of data) if the size of the data to write is greater than or equal to a metadata and the data is deemed to be sequential. After storing the data, the first buffer stores a first set of data and a second buffer stores a second set of data based on adding data to the second memory (the first buffer).)
and write the first set of data into the one or more memory devices … based at least in part on the first set of data satisfying a condition for the first buffer (Sinclair [0056] teaches sequential data may be written to a the second memory layer (the first memory area that contains the first set of data if the size of the data is greater than or equal to a full metapage which is a threshold value that defines a condition for storing data in the first buffer.)
Sinclair suggests wherein the processing circuitry is configured to cause the memory system to maintain the second set of data in the second buffer after writing the first set of data into the one or more memory devices based at least in part on the condition for the first buffer. (Sinclair [0056] discloses there may be a plurality of writes to flash memory areas that may write 1) sequential data greater than or equal to the size of a metadata page in a first memory area that contains a first set of data and 2) random data less than the size of a metadata page in a second memory area that contains a second set of data. Each flash memory area may maintain data in their respective areas. Sinclair Fig. 5 discloses that following the processing of Receive data from a host the system returns to step 502 to process additional requests, and each request may be sequential data written to the second flash memory layer at step 506 or to the first flash memory layer at step 508 with no restriction on the order (sequential versus random) requests. Thus Sinclair Fig. 5 suggests the second (random) data written to the second set of data may be written to and maintained in the second set of data after writing sequential data that was written to the first set of data. The random data is maintained in the second buffer (first flash layer) until the system has an opportunity to flush the data to the next flash layer (the second flash layer that is the first buffer), thus causing the memory to maintain the second set of random data in the second buffer after writing the first set of data which is data written to the one or more memory devices based at least in part on the condition of the first buffer (where the condition is a size threshold associated with the first buffer used to determine that data should be written to the first buffer when the data size is greater than a first threshold. See Sinclair Fig. 5, steps 510, 512 and 506 that details the processes of flushing data from the first layer to the second layer based on a criterial being met, otherwise maintaining the data within the layer along the ‘no’ path of step 512.) One would be motivated to do so to support all of the combination of hosts requests supported by Fig.5 of Sinclair, including the need to send both random and sequential date requests and to send it in any order. Examiner notes that not allowing the host to send data in any order would place an undue and unusual hardship of maintaining the I/O history on the host.
However, Sinclair does not explicitly teach write the first set of data into the one or more memory devices at a first offset of a set of offset within a multi-plane page ... wherein the set of offsets comprises a respective plurality of offsets for each plane of the multi-plane page, and.
Goto, of a similar field of endeavor, further discloses write the first set of data into the one or more memory devices at a first offset of a set of offsets within a multi-plane page (Consistent with paragraph [0010] of the instant application writing a multi-plane page may be writing to one or more planes of a memory die that includes a quantity of planes (e.g., two or four planes) in parallel. Goto [0006] discloses that Goto is directed to programming data (writing) data to planes in parallel. Goto [0008]-[0011] discloses that writing data may be based on writing a data that is broken into a subset of pages. Goto Fig. 3A and supporting paras [0093]-[0095] discloses that four pages that span two planes are written to successive pages using successive page offsets that correspond to the channel # (0 to 3) that in turn identify the target device (300a to 300d) where the cannel # is an example of a multi-plane page offset as it identifies the target location relative to the prior page write in a multi-plane page write. Thus a first offset may be to channel #0 of the set of offsets 0, 1, 2, and 3. Goto [0095] discloses these may be programmed concurrently (i.e. in parallel).)
... wherein the set of offsets comprises a respective plurality of offsets for each plane of the multi-plane page, and (Goto [0006] and [0008]-[0011]) represent the set of offsets 0, 1, 2, and 3 represent a plurality of offset (four offsets) for each plane 0 and plane 1 that make up a multi-plane page write given the four pages are written in parallel. Thus the multiplane write of Goto Fig. 3A may be data that comprises a metapage of Sinclair in the solution of Sinclair in view of Goto that writes data to 8 sequential pages of the second flash memory layer of Sinclair in response to the first set of data satisfying a condition (being a metadata in size).
Sinclair and Goto are in a similar field of endeavor as both relate to programming flash memory. Thus it would have been obvious to a person of ordinary skill in the art before the effectively filed date of the claimed invention to incorporate the programming data into a plurality of planes as taught by Goto into the solution of Sinclair that writes memory to flash in pages. Thus, combining prior art elements according to known methods to yield predictable results; (writing page data to a plurality of planes as taught by Gogo into the solution of Sinclair that writes data into pages to improve the flash performance by programming the memory planes in parallel. See Goto [0006].)
Regarding claim 3, Sinclair and Goto teaches all of the limitations in claim 2 above.
Goto further teaches wherein to write the first set of data into the one or more memory devices, the processing circuitry is further is configured to cause the memory system to: write the first set of data into a page that spans a plurality of planes of the one or more memory devices. (Goto [0008]-[0011] discloses that a page may be divided into subsets and each subset is written to a separate memory plane. See also Goto Fig. 3A and supporting paras [0093]-[0095] as detailed above.).
The motivation to combine Goto into the existing combination is the same as set forth in claim 2 above.
Regarding claim 5, The combination of Sinclair and Goto teaches all of the limitations of claim 2 above.
Goto further teaches wherein the first offset within the multi-plane page is zero in response to adding the data to the first buffer. (Got Fig. 3A and supporting paras [0093]-[0095] discloses writing to a multi-plane using channel numbers that correspond to the target memory device may be to the first page in the first channel 0, that has a channel offset of 0 as it is written to the first pages of the first channel in each plane of the memory devices.)
The motivation to combine Goto into the existing combination is the same as set forth in claim 4 above.
Regarding claim 6, The combination of Sinclair and Goto teaches all of the limitations of claim 2 above. Sinclair teaches wherein the threshold size is associated with a physical page size of the one or more memory devices and a quantity of planes of the one or more memory devices. (Sinclair Fig. 2 and supporting para [0051] discloses a metapage size is based on forming one page from each of the blocks of each of the planes 200, 202, 204, and 206, thus is a function of the physical page sizes of the memory devices and the quantity of planes of the memory device (4 in this example).)
Regarding claim 7, The combination of Sinclair and Goto teaches all of the limitations of claim 2 above. Sinclair further teaches wherein the data is added to the second buffer in response to the data size being less than the threshold size. (Sinclair [0050] and [0056] discloses that data will be deemed random and written to the first memory layer (a second buffer) if the size is less than a full metapage.)
Regarding claim 8, The combination of Sinclair and Goto teaches all of the limitations of claim 2 above. Sinclair further teaches wherein one or more portions of the data are added to the first buffer in response to the data size being greater than or equal to the threshold size, each portion of the one or more portions having the threshold size. (Sinclair [0050] and [0056] discloses that if the size is greater than or equal to a full metapage it will be judged as sequential and written to the second memory layer(a first buffer).)
Regarding claim 10, The combination of Sinclair and Goto teaches all of the limitations of claim 2 above. Sinclair further teaches wherein at least a portion of the second set of data stored in the second buffer is copied to the first buffer in response to the second set of data having a second data size that is greater than or equal to the threshold size. (Sinclair [0057] teaches that when a flash memory layer (for example when the first flash memory storing data for a second buffer) has a number of valid blocks is above a transfer threshold, it will transfer data from the first memory layer (the second buffer) to the second memory layer (the first buffer).)
Regarding claim 11, The combination of Sinclair and Goto teaches all of the limitations of claim 2 above. Sinclair further teaches wherein first data is written into a plurality of single level memory cells, multi-level memory cells, triple-level memory cells, quad- level memory cells, or a combination thereof, of the one or more memory devices. (Sinclair [0053]-[0056] discloses the second memory layer (a first buffer storing first data) may be multi-level memory cells that store 2 bits per cell data.)
Regarding claim 12, Sinclair teaches A non-transitory computer-readable medium storing code comprising instructions which, when executed by processing circuitry of a memory system, cause the memory system to: (Sinclair [0055] discloses that the system may be operated via a controller running executable code for implementing the instructions described in the application. Sinclair [0096] discloses that the controller code may be executed by one or more processors.)
The remained of claim 12 recites limitations described in claim 2 above and thus is rejected based on the teachings and rationale of claim 2 above.
Regarding claim 13, the combination of Sinclair and Goto teaches the limitations of claim 12 above.
The remained of claim 13 recites limitations described in claim 3 above and thus is rejected based on the teachings and rationale of claim 3 above.
Regarding claim 15, the combination of Sinclair and Goto teaches the limitations of claim 12 above.
The remained of claim 15 recites limitations described in claim 5 above and thus is rejected based on the teachings and rationale of claim 5 above.
Regarding claim 16, the combination of Sinclair and Goto teaches the limitations of claim 12 above.
The remained of claim 16 recites limitations described in claim 6 above and thus is rejected based on the teachings and rationale of claim 6 above.
Regarding claim 17, Sinclair teaches A method performed by a memory system, comprising: (Sinclair [0005]-[0007] discloses the solution may be implemented as a method performed by a memory system.)
The remained of claim 17 recites limitations described in claim 2 above an thus is rejected based on the teachings and rationale of claim 2 above.
Regarding claim 18, the combination of Sinclair and Goto teaches the limitations of claim 17 above.
The remained of claim 18 recites limitations described in claim 3 above and thus is rejected based on the teachings and rationale of claim 3 above.
Regarding claim 20, the combination of Sinclair and Goto teaches the limitations of claim 17 above.
The remained of claim 18 recites limitations described in claim 5 above and thus is rejected based on the teachings and rationale of claim 5 above.
Regarding claim 21, the combination of Sinclair and Goto teaches the limitations of claim 17 above.
The remained of claim 21 recites limitations described in claim 6 above and thus is rejected based on the teachings and rationale of claim 6 above.
Claim 9 is rejected Under U.S.C 103 as being unpatentable over Sinclair (Sinclair et al., US Pub. No: US 2014/0189207 A1) and further in view of Goto et al., US 2010/0058003 A1) as detailed in claim 2 above and Further in view of Lasser (LASSER US 2016/0099065 A1).
Regarding claim 9, The combination of Sinclair and Goto teaches all of the limitations of claim 2 above.
However, the combination does not explicitly teach wherein an additional portion of the data is added to the second buffer in response to a size of the additional portion being less than the threshold size, wherein the data includes the one or more portions and the additional portion.
Lasser, of a similar field of endeavor, further discloses wherein an additional portion of the data is added to the second buffer in response to a size of the additional portion being less than the threshold size, wherein the data includes the one or more portions and the additional portion. (Examiner notes that consistent with paragraph [0081] the additional data may be data that is added so that data writes that do not fill up a page or some fixed size write may be written with extra data beyond the data to write (for example filled with zeros, dummy, or random data). Sinclair [0051] discloses the smallest amount of data that can be written is a page, but does not detail what the system does to achieve the minimum page size in response to the one or more portions being less than a page. Lasser [0019]-[0021] and [0023] teaches that the memory die may insert random data before any write is attempted to a page. Thus the solution of Sinclair in view of Goto and Lasser that may write data of any size would pad the write data that is less than a page (and less than the threshold size since the threshold size is a metapage which is 4 pages per Sinclair [0051]) with random data so that the data save to the storage contains the one or more portions (the data to write that is less than a threshold size and less than a page) and the additional portion of the data that is the random data to fill up a page (the additional data).
Sinclair, Goto, and Lasser are all in a similar field of endeavor as all relate to writing data to flash memory pages. Thus it would have been obvious to a person of ordinary skill in the art before the effectively filed data of the claimed invention to incorporate the insertion of random data by the die into any page made available for writing data as taught by Lasser into the solution of Sinclair and Goto that writes host data to flash storage, thus combining prior art elements according to known methods to achieve predictable results (to support host writes that may be of any size to flash storage that requires the data to be at least a page in size, and to fill the unused portion of the page with random data, versus a constant pattern such as all zeros, since writing a constant pattern Is known to cause data corruption to adjacent memory cells.)
Relevant Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure is an article titled “Storage and I/O : Reads vs. Writes” published at https://louwrentius.com/storage-and-io-reads-vs-writes.html that writes may simple be placing data in a cache.
Response to Remarks
Examiner thanks applicant for their claim amendments and remarks of 12/18/2025. They have been fully considered.
35 U.S.C 103
Independent Claims 2, 12, and 17
Applicant argues on pages 10 of their remarks the features of Goto does not teach or suggest “a respective plurality of offsets for each plane of the multi-plane page” much less to “write the first set of data into the one or more memory device at a first offset of [the] set of offsets within the multi-plane page based at least in part on the first set of data satisfying a condition for the first buffer,” as recited in amended claim 1”.
Examiner respectfully disagrees. Consistent with paragraph [0010] of the instant application, writing a multi-plane page may be writing in parallel to one or more planes of a memory die that includes a quantity of planes (e.g., two or four planes). Goto [0006] discloses that Goto is directed to programming data (writing) data to planes in parallel. Goto [0008]-[0011] discloses that writing data may be based on writing a data that is broken into a subset of pages. Goto Fig. 3A and supporting paras [0093]-[0095] discloses that four pages that span two planes are written to successive pages using successive page offsets that correspond to the channel # (0 to 3) that in turn identify the target device (300a to 300d) where the channel # is an example of a multi-plane page offset as it identifies the target location relative to the prior page write in a multi-plane page write. Thus a first offset may be to channel #0 of the set of offsets 0, 1, 2, and 3. Goto [0095] discloses these may be programmed concurrently (i.e. in parallel). Thus Goto discloses a first offset 0, of a set of offsets (0, 1, 2, and 3) for each plane of a multi-plane (for planes 0 and plane 1) page write (to multiple pages written to one or more planes in parallel).
Goto [0006] and [0008]-[0011]) represent the set of offsets 0, 1, 2, and 3 represent a plurality of offset (four offsets) for each plane 0 and plane 1 that make up a multi-plane page write given the four pages are written in parallel. Thus the multiplane write of Goto Fig. 3A may be data that comprises a metapage of Sinclair in the solution of Sinclair in view of Goto that writes data to 8 sequential pages of the second flash memory layer of Sinclair, in response to the first set of data satisfying a condition (being a metadata in size).
Applicants argument with respect to independent claims 12 and 17 all rely upon logical similar to those presented in claim 1 above and thus have been addressed in the rejection and remarks to claim 1 above.
Applicants arguments with respect to dependent claims 3, 5-8, 1-11, 13, 1-16, 18, and 20-21 all rely upon perceived errors in the base claims and thus have been addressed in the arguments to the base claims above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JANICE M. GIROUARD whose telephone number is (469)295-9131. The examiner can normally be reached M-F 9:30 - 7:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim Vo can be reached at 571-272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JANICE M. GIROUARD/Primary Examiner, Art Unit 2138