DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Acknowledgement is made of application #18/620,785 filed on 03/28/2024 in which claims 1-20 have been presented for prosecution in a first action on the merits.
Priority
As required by M.P.E.P. 201.14(e), acknowledgement is made of applicant's claim for priority based on US provisional applications #63/541,475, filed on 09/29/2023.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 03/28/2024 has been considered and put on record. Initialed copies are attached herewith.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 11 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 11 recites the underlined limitation “ The apparatus of claim 2, wherein the apparatus is configured to transmit the differential output signal using an Alternating Current (AC) coupling to an external device, the apparatus and an external device connected to the apparatus having ground planes at different voltages.”. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 12 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fried et al., (Fried) USPAT 5,686,872.
Regarding claim 12: Fried at least discloses and shows in Figs. 3-4: A system(400; see Fig. 4) comprising: a first device(first transmission line 410) having a ground plane(see Figs. 2A-2C and 4) at a first voltage(construed as Vcc(transmit) minus a diode voltage drop multiplied by R216/R216 + R214), a first transmission terminal(402), and a second transmission terminal(432); a second device(428) having a ground plane(see Fig. 2B) at a second voltage((construed as Vcc(Receive) minus a diode voltage drop multiplied by R226/R226 + R222), a first receiver terminal(412), and a second receiver terminal(422); a first capacitor(408) coupled to the first transmission terminal(402) of the first device(410) and the first receiver terminal(412) of the second device(428); a second capacitor(426) coupled to the second transmission terminal(432) of the first device(410) and the second receiver terminal(422) of the second device(428)(see col. 13, lines 15-62); wherein the first device(410) is configured to: operate in either a linear mode or a saturation mode based on a magnitude of electromagnetic interference(see col. 12, lines 26-65); and during the linear mode or the saturation mode, use the first transmission terminal(402) and second transmission terminal(432) to transmit a differential signal to the second device(428).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 19 is rejected under 35 U.S.C. 103 as being obvious over Fried et al., (Fried) USPAT 5,686,872.
Regarding claim 19, Fried at least discloses and shows in Figs. 2A-2C,3 and 4: A system comprising: a plurality of battery cells; a first device(410) connected to Vcc(transmit)(see Fig. 2B), the first device including a first transmission terminal (402) and a second transmission terminal(432); a second device(428) connected to Vcc(receive)(see Fig. 2B), Vcc(receive) having a different voltage((construed as Vcc(Receive) minus a diode voltage drop multiplied by R226/R226 + R222), than (construed as Vcc(transmit) minus a diode voltage drop multiplied by R216/R216 + R214), the second device(428) including a first receiver terminal(412) and a second receiver terminal(422); wherein the first device(410) is configured to: operate in either a linear mode or a saturation mode based on a magnitude of electromagnetic interference(see col. 12, lines 26-65); and during the linear mode or the saturation mode, use the first transmission terminal(402) and second transmission terminal(432) to transmit a differential signal to the second device.
Fried discloses all the claimed invention except for the limitations of , “a first subset of the battery cells and a second subset of battery cells”. Fried stayed silent regarding the nature of power supply Vcc(transmit) and Vcc(receive).
It would have been an obvious matter of design choice to include a power supply comprising a plurality of battery cells; a first device connected to a first subset of the battery cells, the first device including a first transmission terminal and a second transmission terminal; a second device connected to a second subset of battery cells, the second subset of battery cells having a different voltage than the first subset of battery cells, as recited, for the advantages of providing a cheap power source that will power the whole system and be easily replaceable to thereby ensure a continuous source of power to the system.
Accordingly claim 19 would have been obvious.
Claim 18 is rejected under 35 U.S.C. 103 as being obvious over Fried et al., (Fried) USPAT 5,686,872 in view of Kato US 2021/0145250
Regarding claim 18, Fried does not expressly teach the limitations of:
wherein the differential signal is formatted with Manchester Encoding during both the linear mode and the saturation mode
However, Kato teaches, wherein the differential signal is formatted with Manchester Encoding during both the linear mode and the saturation mode(see [0097]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize a differential signal that is formatted with Manchester Encoding during both the linear mode and the saturation mode, as recited, for the advantages of detecting whether a transition occurs at the beginning of the bit cell and to protect the signal integrity from wire swapping or polarity inversion. Furthermore, the use of differential Manchester encoding is beneficial to use since it only tracks edge transitions and not absolute while providing a self-synchronizing line code that combines both data and clock timing in a single stream.
Accordingly claim 18 would have been obvious.
Allowable Subject Matter
Claims 13-17 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 13, patentability exists at least in part with the claimed limitations of, “…wherein the first device includes: a first diode including an anode coupled to a supply terminal of the first device and a cathode coupled to a supply terminal of first pre-driver circuitry; a second diode including a cathode coupled to the cathode of the first diode and an anode; a first transistor including a first current terminal coupled to the supply terminal of the first device, a second current terminal, and a control terminal coupled to the second current terminal; a second transistor including a first current terminal coupled to the supply terminal of the first device, a control terminal coupled to the control terminal of the first transistor, and a second current terminal; a third diode including an anode coupled to the second current terminal of the second transistor and a cathode coupled to the anode of the second diode; a third transistor including a first current terminal coupled to the anode of the second diode, a control terminal coupled to an output terminal of first driver circuitry, and a second current terminal coupled to a first communication terminal; a fourth diode including an anode coupled to the supply terminal of the first device and a cathode coupled to an output terminal of second pre-driver circuitry; a fifth diode including a cathode coupled to the cathode of the fifth diode and an anode; a sixth diode including an anode coupled to the second current terminal of the second transistor and a cathode coupled to the anode of the sixth diode; a fourth transistor including a first current terminal coupled to the anode of the sixth diode, a control terminal coupled to the output terminal of second driver circuitry, and a second current terminal coupled to a second communication terminal; a first resistor including a first terminal coupled to the second communication terminal and a second terminal; a second resistor including a second terminal coupled to the first communication terminal and a second terminal coupled to the second terminal of the first resistor; amplifier circuitry including a first input terminal configured to receive a nominal common mode voltage; a second input terminal; and an output terminal coupled to both the second input terminal of the amplifier circuitry and the second terminal of the first resistor; a fifth transistor including a second current terminal coupled to the first communication terminal; a control terminal; and a first current terminal coupled to the control terminal of the fifth transistor; a sixth transistor including a second current terminal coupled to the first current terminal of the fifth transistor, a control terminal coupled to an output terminal of third driver circuitry, and a first current terminal; a seventh transistor including a second current terminal coupled to the second communication terminal, a control terminal, and a first current terminal coupled to the control terminal of the seventh transistor; an eighth transistor including a second current terminal coupled to the first current terminal of the seventh transistor, a control terminal coupled to an output of fourth driver circuitry, and a first current terminal; a ninth transistor including a second current terminal coupled to the first current terminal of the sixth transistor and the first current terminal of the eighth transistor, a control terminal, and a first current terminal configured to be coupled to ground; and a tenth transistor including a first current terminal coupled to the second current terminal of the first transistor, a control terminal coupled to the second current terminal of the first transistor and to the control terminal of the ninth transistor, and a first current terminal configured to be coupled to ground”.
Claims 14-17 depend either directly or indirectly from claim 13 and thus are also allowed for the same reasons.
Regarding claim 20, patentability exists at least in part with the claimed limitations of, “…wherein the first device includes: a first diode including an anode coupled to a supply terminal of the first device and a cathode coupled to a supply terminal of first pre-driver circuitry; a second diode including a cathode coupled to the cathode of the first diode and an anode; a first transistor including a first current terminal coupled to the supply terminal of the first device, a second current terminal, and a control terminal coupled to the second current terminal; a second transistor including a first current terminal coupled to the supply terminal of the first device, a control terminal coupled to the control terminal of the first transistor, and a second current terminal; a third diode including an anode coupled to the second current terminal of the second transistor and a cathode coupled to the anode of the second diode; a third transistor including a first current terminal coupled to the anode of the second diode, a control terminal coupled to an output terminal of first driver circuitry, and a second current terminal coupled to a first communication terminal; a fourth diode including an anode coupled to the supply terminal of the first device and a cathode coupled to an output terminal of second pre-driver circuitry; a fifth diode including a cathode coupled to the cathode of the fifth diode and an anode; a sixth diode including an anode coupled to the second current terminal of the second transistor and a cathode coupled to the anode of the sixth diode; a fourth transistor including a first current terminal coupled to the anode of the sixth diode, a control terminal coupled to the output terminal of second driver circuitry, and a second current terminal coupled to a second communication terminal; a first resistor including a first terminal coupled to the second communication terminal and a second terminal; a second resistor including a second terminal coupled to the first communication terminal and a second terminal coupled to the second terminal of the first resistor; amplifier circuitry including a first input terminal configured to receive a nominal common mode voltage; a second input terminal; and an output terminal coupled to both the second input terminal of the amplifier circuitry and the second terminal of the first resistor; a fifth transistor including a second current terminal coupled to the first communication terminal; a control terminal; and a first current terminal coupled to the control terminal of the fifth transistor; a sixth transistor including a second current terminal coupled to the first current terminal of the fifth transistor, a control terminal coupled to an output terminal of third driver circuitry, and a first current terminal; a seventh transistor including a second current terminal coupled to the second communication terminal, a control terminal, and a first current terminal coupled to the control terminal of the seventh transistor; an eighth transistor including a second current terminal coupled to the first current terminal of the seventh transistor, a control terminal coupled to an output of fourth driver circuitry, and a first current terminal; a ninth transistor including a second current terminal coupled to the first current terminal of the sixth transistor and the first current terminal of the eighth transistor, a control terminal, and a first current terminal configured to be coupled to ground; and a tenth transistor including a first current terminal coupled to the second current terminal of the first transistor, a control terminal coupled to the second current terminal of the first transistor and to the control terminal of the ninth transistor, and a first current terminal configured to be coupled to ground”.
Claims 1-10 are objected to but are otherwise allowable over the current prior art of record.
Regarding claim 1, the prior art of record either taken alone or in combination thereof fails to teach or reasonably suggest, in the claimed combination, an apparatus comprising, among other patentability features, “a first diode including an anode coupled to a supply terminal of the apparatus and a cathode coupled to a supply terminal of first pre-driver circuitry; a second diode including a cathode coupled to the cathode of the first diode and an anode; a first transistor including a first current terminal coupled to the supply terminal of the apparatus, a second current terminal, and a control terminal coupled to the second current terminal; a second transistor including a first current terminal coupled to the supply terminal of the apparatus, a control terminal coupled to the control terminal of the first transistor, and a second current terminal; a third diode including an anode coupled to the second current terminal of the second transistor and a cathode coupled to the anode of the second diode; a third transistor including a first current terminal coupled to the anode of the second diode, a control terminal coupled to an output terminal of first driver circuitry, and a second current terminal coupled to a first communication terminal; a fourth diode including an anode coupled to the supply terminal of the apparatus and a cathode coupled to an output terminal of second pre-driver circuitry; a fifth diode including a cathode coupled to the cathode of the fifth diode and an anode; a sixth diode including an anode coupled to the second current terminal of the second transistor and a cathode coupled to the anode of the sixth diode; a fourth transistor including a first current terminal coupled to the anode of the sixth diode, a control terminal coupled to the output terminal of second driver circuitry, and a second current terminal coupled to a second communication terminal; a first resistor including a first terminal coupled to the second communication terminal and a second terminal; a second resistor including a second terminal coupled to the first communication terminal and a second terminal coupled to the second terminal of the first resistor; amplifier circuitry including a first input terminal configured to receive a nominal common mode voltage; a second input terminal; and an output terminal coupled to both the second input terminal of the amplifier circuitry and the second terminal of the first resistor; a fifth transistor including a second current terminal coupled to the first communication terminal; a control terminal; and a first current terminal coupled to the control terminal of the fifth transistor; a sixth transistor including a second current terminal coupled to the first current terminal of the fifth transistor, a control terminal coupled to an output terminal of third driver circuitry, and a first current terminal; a seventh transistor including a second current terminal coupled to the second communication terminal, a control terminal, and a first current terminal coupled to the control terminal of the seventh transistor; an eighth transistor including a second current terminal coupled to the first current terminal of the seventh transistor, a control terminal coupled to an output of fourth driver circuitry, and a first current terminal; a ninth transistor including a second current terminal coupled to the first current terminal of the sixth transistor and the first current terminal of the eighth transistor, a control terminal, and a first current terminal configured to be coupled to ground; and a tenth transistor including a first current terminal coupled to the second current terminal of the first transistor, a control terminal coupled to the second current terminal of the first transistor and to the control terminal of the ninth transistor, and a first current terminal configured to be coupled to ground”.
Claims 2-10 depend either directly or indirectly from claim 1 and thus are also allowable for the same reasons.
Citation of Prior art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
USPAT 9,294,300 B2 to Janz et al., (Janz) discloses the general state of the art regarding token based-communication in daisy chain configured battery management devices.
USPAT 8,913,362 B2 to Simmonds discloses a diode protection of cascaded mixed-voltage transistors.
US 2019/0013960 A1 to Sadwick discloses a switched wireless signaling.
USPAT 6,311,045 B1 to Domokos discloses the general state of the art regarding an apparatus for signal isolation in a radio transmitter-receiver.
Conclusion
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M'BAYE DIAO
Primary Examiner
Art Unit 2859
/M BAYE DIAO/Primary Examiner, Art Unit 2859 September 16, 2026
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