DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of invention I (claims 1 – 16) in the reply filed on 4/27/26 is acknowledged. The traversal is on the grounds that examination of the integrated circuit claims necessarily requires consideration of the same structure and functionality that underlies the method claims, requiring restriction would not result in a meaningful reduction in examination burden. This is not found persuasive because the method steps of forming the device are not required to forming the device of the apparatus claims.
The requirement is still deemed proper and is therefore made FINAL.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the dielectric electric layers must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 – 10 and 12 – 16 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Li (U.S. PG Pub. # 2024/0176069 A1).
In Re claim 1, ‘069 teaches integrated photonics circuitry comprising:
a substrate (131);
an interposer structure mounted on the substrate,
the interposer structure including a glass chiplet (103);
an electrical and photonic integrated circuit (EPIC) (104 or 104 and 114) having a first portion disposed on the glass chiplet and a second portion disposed over the substrate (all portions are disposed over both);
and a waveguide (160) of the glass chiplet, the waveguide coupled to the EPIC (fig. 5B).
In Re claim 2, '069 teaches edge coupled as claimed (par. 0079, fig. 5B).
In Re claim 3, Applicant is claiming the product including the process of making the circuitry, and therefore is of "product-by-process" nature. The courts have been holding for quite some time that the determination of the patentability of product-by-process claim is based on the product itself rather than on the process by which the product is made. In re Thrope, 777 F. 2d 695, 227 USPQ 964 (Fed. Cir. 1985); and patentability of claim to a product does not rest merely on a difference in the method by which that product is made. Rather, it is the product itself which must be new and unobvious. Applicant has chosen to claim the invention in the product form. Thus a prior art product which possesses the claimed product characteristics can anticipate or render obvious the claim subject matter regardless of the manner in which it is fabricated. A rejection based on 35 U.S.C. section 102 or alternatively on 35 U.S.C. section 103 of the status is eminently fair and acceptable. In re Brown and Saffer, 173 USPQ 685 and 688; In re Pilkington, 162 USPQ 147.
In Re claims 4 and 5, '069 teaches adhesive (127, par. 0089 or 150) and solder (150) as claimed.
In Re claim 6, '069 teaches a mold material (148-1 or 148-2 9 or epoxy 127, pars. 0089, 0091) as claimed.
In Re claim 7, '069 teaches a plurality of dielectric electric layers (148-1 and 148-2 are between mold, lower 127, and 114) and routing circuitry (196) as claimed.
In Re claim 8, '069 teaches epoxy (127, pars. 0089, 0091) as claimed.
In Re claim 9, '069 teaches a processor (128) as claimed.
In Re claim 10, '069 teaches a silicon bridge (202) as claimed.
In Re claim 12, ‘069 teaches an integrated circuit (IC) package (fig. 5B) comprising:
a substrate (131);
an interposer structure mounted on a substrate, the interposer structure comprising:
a glass chiplet (103, par. 0075);
a silicon bridge (202 is a die, par. 0037);
a plurality of dielectric electric layers (interpreted as electric layers that contact a dielectric as this phrase is not depicted in the drawings, 196 and 130 are embedded in dielectric material of 148 and 127, respectively, par. 0089, or interpreted as 148 is a plurality of dielectric layers per par. 0103 as redistribution layer technique applies layers corresponding to each layer of conductive traces of which 5 are depicted in 148 of fig. 5B) disposed on the silicon bridge (fig. 5B) and having routing circuitry formed therethrough (interpreted as the silicon bridge has circuitry formed therethrough, par. 0085 or the electric layers form routing circuitry);
and a wave guide (160);
a processor (128) disposed over the interposer structure;
and an electrical and photonic integrated circuit (EPIC) (104 and 114), the EPIC disposed over the interposer structure adjacent the processor and on the glass chiplet,
the EPIC and the processor electrically coupled by the routing circuitry and the silicon bridge (to each other via 202 and to layer 148 as the claim does not recite coupled to each other),
the waveguide edge coupled (par. 0079) to the EPIC.
In Re claim 13, '069 teaches mold (148) as claimed (fig. 5B).
In Re claim 14, '069 teaches pillars (vertical sections of 196).
In Re claim 15, '069 teaches the mold (148) contacting the glass chiplet (103, fig. 5B).
In Re claim 16, '069 teaches edge coupling as claimed (par. 0079, fig. 5B).
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Psaila et al. (U.S. PG Pub. # 2021/0003775 A1).
In Re claims 1 and 11, ‘775 teaches integrated photonics circuitry comprising:
a substrate (102);
an interposer structure mounted on the substrate,
the interposer structure including a glass chiplet (122);
an electrical and photonic integrated circuit (EPIC) (124, par. 0167) having a first portion disposed on the glass chiplet and a second portion disposed over the substrate (all portions are disposed over both);
and a waveguide (126) of the glass chiplet, the waveguide evanescently coupled to the EPIC (par. 0168, fig. 9).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHAD SMITH whose telephone number is (571)270-1294. The examiner can normally be reached M-F 7:30 - 5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Uyen-Chau Le can be reached at 1-571-272-2397. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHAD H SMITH/ Primary Examiner, Art Unit 2874
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