DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. This Non-Final office action is in response to application 18/620,910, application filed on 03/28/2024. Claims 1-20 are currently pending in this application.
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
4. Claim(s) 1-4 and 6-20 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Smith (US PG Pub No. 2025/0181491).
5. With respect to independent claim 1, Smith teaches:
A semiconductor device (see stacked semiconductor package, Fig 1B; see stacked semiconductor platform, para 112) comprising:
a first die comprising a data source (see memory/data dies as chips in a multi-chip package, para 74);
a second die comprising an execution unit (see second die as logic chip 100, Fig 1B, see CPU/ALU which is responsible for extracting instructions from memory and executing those instructions, para 115-116), wherein the second die is oriented in a common plane with the first die and positioned relative to the first die in a vertical dimension perpendicular to an orientation of the common plane (see common plane as shown in Fig 1A, showing memory chips stacked vertically on logic/execution/CPU chip); and
a data path that electrically couples the data source and the execution unit (see circuit/chips connected via a datapath/bus, para 57).
6. With respect to independent claim 14, Smith teaches:
A system comprising:
a semiconductor device (see stacked semiconductor package, Fig 1B; see stacked semiconductor platform, para 112) comprising:
a first die comprising a data source (see memory/data dies as chips in a multi-chip package, para 74);
a second die comprising an execution unit, wherein the second die is oriented in a common plane with the first die and positioned relative to the first die in a vertical dimension perpendicular to an orientation of the common plane (see second die as logic chip 100, Fig 1B, see CPU/ALU which is responsible for extracting instructions from memory and executing those instructions, para 115-116; see common plane as shown in Fig 1A, showing memory chips stacked vertically on logic/execution/CPU chip); and
a data path that electrically couples the data source and the execution unit (see common plane as shown in Fig 1A, showing memory chips stacked vertically on logic/execution/CPU chip); and
a component external to the semiconductor device configured to interact with the semiconductor device (see CPU which provides instructions for sending/receiving data, where CPU 1A-108 is external to chip structure 1A-100), wherein the interaction comprises at least one of:
transmitting data to the semiconductor device; or receiving data from the semiconductor device (see Fig 1A, showing CPU providing datapath for sending/receiving data).
7. With respect to independent claim 18, Smith teaches:
A method comprising: providing:
a first die comprising a data source (see memory/data dies as chips in a multi-chip package, para 74); and
a second die comprising an execution unit (see second die as logic chip 100, Fig 1B, see CPU/ALU which is responsible for extracting instructions from memory and executing those instructions, para 115-116);
orienting the second die in a common plane with the first die (see common plane as shown in Fig 1A, showing memory chips stacked vertically on logic/execution/CPU chip);
positioning the second die relative to the first die in a vertical dimension perpendicular to an orientation of the common plane such that the data source and the execution unit are substantially aligned with one another in the vertical dimension (see stacked semiconductor chip, including memory data source chips stacked vertically over top of logic/execution chip, Fig 8); and
forming a data path that electrically couples the data source and the execution unit (see Fig 1A, showing CPU providing datapath for sending/receiving data).
8. With respect to claim 2, Smith teaches:
wherein:
the first die, the second die, and the data path are included in a silicon stack comprising a plurality of layers (see 1st memory/data chips stacked on top of logic chip, where data path/bus tx/rx transmission circuit 216 is part of the stack, Fig 2; see alternative arrangement Fig 6, showing CPU on same chip stack package as memory/data chips);
the first die is included in a first layer of the silicon stack (see memory/data chips in Fig 1A, as 1A-100 chip stack);
the second die is included in a second layer of the silicon stack (see first die 1A-102 of Fig 1A which is a memory chip/stack, and underneath at 1A-106 is a die/chip); and
the data path transits the silicon stack between at least the first layer and the second layer (see via stack between memory/data chips and logic/execution chip, para 168; see TSV’s in architecture between logic chips and memory chips, para 238).
9. With respect to claim 3, Smith teaches:
wherein the data path transits at least one intermediary layer in the silicon stack, the at least one intermediary layer disposed in the silicon stack between the first die and the second die (see interposer layer which can include communication paths, para 85).
10. With respect to claim 4, Smith teaches:
wherein the at least one intermediary layer comprises a bonding layer that affixes at least one of the first layer or the second layer within the silicon stack (see bonding between layers of chip stack, para 250; semiconductor wafers in stack are bonded together to create stack, para 456; bonding dies, para 458).
11. With respect to claim 6, Smith teaches:
wherein at least one of: the data path is an integer data path; the data source is an integer data source; or the execution unit is an integer data source (see integer data, para 91).
12. With respect to claim 7, Smith teaches:
wherein the data source comprises an additional execution unit (see portions of memory/data chips/circuits comprise TX/RX control which acts as an execution unit for retrieving/transmitting data to the memory/data chip, para 148, Fig 8).
13. With respect to claim 8, Smith teaches:
wherein the data source comprises at least one of: a physical register file; a reservation station; a data cache; an instruction cache; or a data queue (see cache, para 111; see instruction cache/control, para 84; see registers, para 56).
14. With respect to claim 9, Smith teaches:
wherein the execution unit comprises at least one of: an arithmetic logic unit; an address generation unit; a crossbar mux; or a functional unit (see arithmetic logic unit ALU, para 115; providing/generating address control information, para 66).
15. With respect to claim 10, Smith teaches:
wherein the second die comprises a plurality of execution units (see second logic/execution chip containing multiple CPU’s, Fig 16).
16. With respect to claim 11, Smith teaches:
wherein the plurality of execution units comprises execution units of different types (see PHY, shared circuit blocks, I/O pad, etc all part of the logic/execution chip, Fig 19-3).
17. With respect to claim 12, Smith teaches:
wherein: the first die comprises a plurality of data sources (see plurality of memory sources/echelons in memory/data stack, see Fig 5); and the
semiconductor device further comprises a plurality of data paths that each electrically couple a corresponding one of the plurality of data sources to the execution unit in the second die (see combination of TSV’s, interposer, and memory echelon which connects memory/data chips to logic/execution chip, Fig 6, 8).
18. With respect to claim 13, Smith teaches:
wherein: the first die comprises a plurality of data sources (see plurality of memory sources/echelons in memory/data stack, see Fig 5);
the second die comprises a plurality of execution units (see plurality of memory sources/echelons in memory/data stack, see Fig 5); and
a plurality of data paths electrically couple each data source to multiple execution units in the plurality of execution units (see combination of TSV’s, interposer, and memory echelon which connects memory/data chips to logic/execution chip, Fig 6, 8).
19. With respect to claim 15, Smith teaches:
wherein the data source comprises an additional execution unit (see portions of memory/data chips/circuits comprise TX/RX control which acts as an execution unit for retrieving/transmitting data to the memory/data chip, para 148, Fig 8).
20. With respect to claim 16, Smith teaches:
wherein the data source comprises at least one of: a physical register file; a reservation station; a data cache; an instruction cache; or a data queue (see cache, para 111; see instruction cache/control, para 84; see registers, para 56).
21. With respect to claim 17, Smith teaches:
wherein the execution unit comprises at least one of: an arithmetic logic unit; an address generation unit; a crossbar mux; or a functional unit (see arithmetic logic unit ALU, para 115; providing/generating address control information, para 66).
22. With respect to claim 19, Smith teaches:
wherein forming the data path that electrically couples the data source and the execution unit comprises forming the data path within an intermediary layer that separates the first die and the second die (see via stack between memory/data chips and logic/execution chip, para 168; see TSV’s in architecture between logic chips and memory chips, para 238; see interposer layer which can include communication paths, para 85).
23. With respect to claim 20, Smith teaches:
wherein:
the first die is included in a first layer of a silicon stack (see memory/data chips in Fig 1A, as 1A-100 chip stack);
the second die is included in a second layer of the silicon stack (see first die 1A-102 of Fig 1A which is a memory chip/stack, and underneath at 1A-106 is a die/chip);
the silicon stack further comprises at least one intermediary layer comprising a bonding layer that affixes at least one of the first layer or the second layer within the silicon stack (see via stack between memory/data chips and logic/execution chip, para 168; see TSV’s in architecture between logic chips and memory chips, para 238; see interposer layer which can include communication paths, para 85); and
the method further comprises bonding the first layer and the second layer within the silicon stack via the bonding layer (see bonding between layers of chip stack, para 250; semiconductor wafers in stack are bonded together to create stack, para 456; bonding dies, para 458).
Claim Rejections - 35 USC § 103
24. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
25. Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Smith (US PG Pub No. 2025/0181491) in view of Shwartz et al. (US PG Pub No. 2023/0092152).
26. With respect to claim 5, Smith appears to be silent regarding:
wherein at least one of: the data path is a floating-point data path; the data source is a floating-point data source; or the execution unit is a floating-point execution unit.
However, Shwartz teaches:
wherein at least one of: the data path is a floating-point data path; the data source is a floating-point data source; or the execution unit is a floating-point execution unit (see floating point execution unit as part of chip stack, para 105).
It would have been obvious to one of ordinary skill in the art before the time of the invention to have incorporated Shwartz’s floating point execution unit into the invention of Smith for at least the following reason(s): Schwarts points out that physical register elements and register file systems like those taught in Smith generally are capable of floating point execution, and is a well-known capability of register file systems in ALU-type processors.
Conclusion
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/SUCHIN PARIHAR/
Primary Examiner, Art Unit 2851
