DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to claims filed 03/28/2024.
Claims 1-30 are pending.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “a scheduler” in Claim 11-24 and “first processing”, in Claim 21.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof. A review of the disclosure as originally filed, hereafter "disclosure", reveals that the corresponding structure of the “a scheduler” is a general purpose computer, see at least instant specification ¶4 and ¶9-10. Furthermore, the corresponding structure for “first processing” is a general purpose computer, see at least instant specification ¶10. In accordance with MPEP § 2181 (ll)(B), when the corresponding structure of computer implemented mean plus function limitations corresponds to a general purpose computer, an algorithm is required to transform the general purpose computer into a special purpose computer to be sufficient as corresponding structure. Applicant has failed to define the algorithm for each of the claimed functions and has instead only provided either verbatim support for the claimed function (which is insufficient as a steps of steps of a corresponding algorithm) or exemplary language that does not make clear the metes and bounds of the algorithm. As such, see rejections under 35 U.S.C. § 112(a) and (b) below.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 11-24 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 11 recites “a scheduler” and Claim 21 recites “first processing” which invokes 35 U.S.C. § 112(f), see claim interpretation above. The disclosure does not recite sufficient corresponding structure (in this instance computer + algorithm), again see claim interpretation above. As such, and in accordance with MPEP § 2181 (ll)(B), last paragraph "When a claim containing a computer-implemented 35 U.S.C. 112(f) claim limitation is found to be indefinite under 35 U.S.C. 112(b) for failure to disclose sufficient corresponding structure (e.g., the computer and the algorithm) in the specification that performs the entire claimed function, it will also lack written description under 35 U.S.C. 112(a)."
Claims 12-20 and 22-24 are further rejected based on their dependency to the aforementioned rejected Claims 11 and 21.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2, 4, 8-9, 11-24 and 26-30 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 11 recites “a scheduler” and Claim 21 recites “first processing” invoking 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. The disclosure fails to disclose sufficient corresponding structure (in this instance computer+ algorithm), see claim interpretation above. As such, and in accordance with MPEP § 2181 (ll)(B) "For a computer-implemented 35 U.S.C. 112(f) claim limitation, the specification must disclose an algorithm for performing the claimed specific computer function, or else the claim is indefinite under 35 U.S.C. 112(b).".Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Claims 2, 12, 23 and 26 recite the limitation “the lighter workload levels”. There is insufficient antecedent basis for this limitation in the Claim.
For the purposes of compact prosecution, Examiner will interpret “the lighter workload levels” to mean “a lighter workload level”.
Claims 4 and 14 recite the limitation “a highest workload”, it is unclear whether this is the same or different “a highest workload” already established in Claims 3 and 13 respectively.
For the purposes of compact prosecution, Examiner will interpret “a highest workload” in Claims 4 and 14 as referring to the same “a highest workload” established in Claims 3 and 13 respectively.
Claims 8 and 18 recite the limitation “the highest priority heaviest thread”. There is insufficient antecedent basis for this limitation in the Claim.
For the purposes of compact prosecution, Examiner will interpret “the highest priority heaviest thread” to mean “a highest priority thread” defined in Claims 3 and 13.
Claims 9 and 19 recite the limitation “the same first CPU core”. There is insufficient antecedent basis for this limitation in the Claim.
For the purposes of compact prosecution, Examiner will interpret “the same first CPU core” as referring to “a same first CPU core” defined in Claims 8 and 18.
Claims 13, 15-17, 12-20, 22-24 and 27-30 are further rejected based on their dependency to the aforementioned rejected Claims.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-30 are rejected under 35 U.S.C. 101 because the claimed invention recites a judicial exception, is directed to that judicial exception, an abstract idea, as it has not been integrated into practical application and the claims further do not recite significantly more than the judicial exception. Examiner has evaluated the claims under the framework provided in the 2019 Patent Eligibility Guidance published in the Federal Register 01/07/2019 and has provided such analysis below.
Step 1:
Claim 1-10 are directed to methods and fall within the statutory category of processes; Claims 11-24 are directed to a system and falls within the statutory category of machines; Claims 25-30 are directed to a computer program product and falls within the statutory category of manufacture; . Therefore, “Are the claims to a process, machine, manufacture or composition of matter?” Yes.
In order to evaluate the Step 2A inquiry “Is the claim directed to a law of nature, a natural phenomenon or an abstract idea?” we must determine, at Step 2A Prong 1, whether the claim recites a law of nature, a natural phenomenon or an abstract idea and further whether the claim recites additional elements that integrate the judicial exception into a practical application.
Step 2A Prong 1:
Claims 1, 11, 21 and 25: The limitations of “identify/identifying threads of execution responsible for creating the frames and which correspond to a number of first CPU cores/first processing means in the CPU architecture”, “for a predetermined time period,” … “create/creating a ranking of the threads according to their workload levels;”, “determine/determining a present workload level of each first CPU core/first processing means;”, “create/creating a ranking of the first CPU cores/first processing means according to their present workload levels;”, and “assign/assigning each thread to a single first CPU core/processing means according to the ranking of the first CPU cores and according to the ranking of the threads”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can mentally identify which resource is responsible for the execution of a particular task. A person can also mentally assess how much of a resource is being used and rank them based on that usage during a preset period of time. Lastly, a person can mentally select which resource to use based on those rankings.
Therefore, yes, Claims 1, 11, 21 and 25 recite judicial exceptions.
The claims have been identified to recite judicial exceptions, Step 2A Prong 2 will evaluate whether the claims are directed to the judicial exception.
Step 2A Prong 2:
Claims 1, 11, 21 and 25: The judicial exceptions are not integrated into practical applications. In particular, the claims recite the following additional elements – “receive/receiving input to create frames on a display device of battery-powered portable computing device at a predetermined rate;”, merely recite insignificant extra-solution data gathering and data storage which do not integrate the judicial exception into a practical application. See MPEP § 2106.05(g). Further “the CPU architecture comprising first CPU cores and second CPU cores”, “the CPU architecture comprising first processing means and second processing means”, “each first CPU core has a first processing capacity and each second CPU core has a second processing capacity, the first processing capacity being greater than the second processing capacity;” and “each first CPU core having a first processing capacity and each second CPU core having a second processing capacity, the first processing capacity being greater than the second processing capacity;” recites a field of use which generally links the use of a judicial exception to a particular technological environment (MPEP § 2106.05(h)).
Therefore, “Do the claims recite additional elements that integrate the judicial exception into a practical application? No, these additional elements do not integrate the abstract idea into a practical application and they do not impose any meaningful limits on practicing the abstract idea. The claim is directed to an abstract idea.
After having evaluating the inquires set forth in Steps 2A Prong 1 and 2, it has been concluded that the Claims 1, 11, 21 and 25 not only recite a judicial exception but that the claims are directed to a judicial exception as a judicial exception has not been integrated into a practical application.
Step 2B:
Claims 1, 11, 21, and 25: The claims do not include additional elements, alone or in combination, that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements amount to no more than generic computing components, field of use/technological environment, and insignificant extra-solution activity which do not amount to significantly more than the abstract idea. Further, the insignificant extra-solution activity is Well-Understood, Routine, and Conventional. “The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. i. Receiving or transmitting data over a network”. See MPEP § 2106.05(d)(II).
Therefore, “Do the claims recite additional elements that amount to significantly more than the judicial exception? No, these additional elements, alone or in combination, do not amount to significantly more than the judicial exception.
Having concluded analysis within the provided framework, Claims 1, 11, 21 and 25 do not recite patent eligible subject matter under 35 U.S.C. § 101.
Claims 2, 12, 23 and 26: “first CPU cores with the lighter workload levels receive higher priority threads having higher workload levels, and first CPU cores with heavier workload levels receive lower priority threads having lighter workload levels”, and “first processing means with the lighter workload levels receive higher priority threads having higher workload levels, and first processing means with heavier workload levels receive lower priority threads having lighter workload levels”, recites a field of use which generally links the use of a judicial exception to a particular technological environment (MPEP § 2106.05(h)). With regard to integration into practical application and whether additional elements amount to significantly more, Claims 2, 12, 23 and 26 fail both prongs of Step 2A, thus the claims are directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, Claims 2, 12, 23 and 26 do not recite patent eligible subject matter under 35 U.S.C. § 101.
Claims 3, 13, 24 and 27: “the CPU architecture comprises a [single or multiple] prime CPU core”, recites a field of use which generally links the use of a judicial exception to a particular technological environment (MPEP § 2106.05(h)). Further, “the method further comprises assigning the [single prime CPU core or one of the multiple] prime CPU core(s) with a highest priority thread having a highest workload”, “the system further comprises the single prime core or one of the multiple prime CPU cores being assigned with a highest priority thread having a highest workload”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can assign high workloads to high priority resources. With regard to integration into practical application and whether additional elements amount to significantly more, Claims 3, 13, 24 and 27 fail both prongs of Step 2A, thus the claims are directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, Claims 3, 13, 24 and 27 do not recite patent eligible subject matter under 35 U.S.C. § 101.
Claims 4, 14 and 28: “after assigning the [single prime core or one of the multiple] prime CPU core(s) with the highest priority thread having a highest workload, assigning any remaining ranked among the first CPU cores” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can assign high workloads to high priority resources. With regard to integration into practical application and whether additional elements amount to significantly more, Claims 4, 14 and 28 fail both prongs of Step 2A, thus the claims are directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, Claims 4, 14 and 28 do not recite patent eligible subject matter under 35 U.S.C. § 101.
Claims 5, 15 and 29: “the predetermined time period comprises a multiple of a display device refresh rate”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, but for the recitation of generic computing components being used as a tool to perform the functionality, a person can assign high workloads to high priority resources. With regard to integration into practical application and whether additional elements amount to significantly more, Claims 5, 15 and 29 fail both prongs of Step 2A, thus the claims are directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, Claims 5, 15 and 29 do not recite patent eligible subject matter under 35 U.S.C. § 101.
Claims 6, 16 and 30: “identifies the threads of execution responsible for creating the frames and which correspond only up to the number of first CPU cores in the CPU architecture”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can mentally identify which resource is responsible for the execution of a particular task. With regard to integration into practical application and whether additional elements amount to significantly more, Claims 6, 16 and 30 fail both prongs of Step 2A, thus the claims are directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, Claims 6, 16 and 30 do not recite patent eligible subject matter under 35 U.S.C. § 101.
Claims 7 and 17: “scheduler receives data about the threads of execution from a thread hinting framework”, merely recite insignificant extra-solution data gathering activity which do not integrate the judicial exception into a practical application. See MPEP § 2106.05(g). With regard to integration into practical application and whether additional elements amount to significantly more, Claims 7 and 17 fail both prongs of Step 2A, thus the claims are directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more, performing a well understood, routine, and conventional task of data gathering. “The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. i. Receiving or transmitting data over a network”. See MPEP § 2106.05(d)(II). Therefore, Claims 7 and 17 do not recite patent eligible subject matter under 35 U.S.C. § 101.
Claims 8 and 18: “ a thread of execution assigned to a first CPU core will continue to use a same first CPU core until the thread gets ranked as the highest priority heaviest thread at the end of the predetermined time period at which point the highest priority thread will be moved onto a single prime core or one of multiple prime cores for a subsequent predetermined time period”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can mentally assign work a resource based on a ranked determined during a certain time period. With regard to integration into practical application and whether additional elements amount to significantly more, Claims 8 and 18 fail both prongs of Step 2A, thus the claims are directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, Claims 8 and 18 do not recite patent eligible subject matter under 35 U.S.C. § 101.
Claims 9 and 19: “if a thread of execution is assigned to a first CPU core, then the thread will continue to use the same first CPU core until frame rendering is complete”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can mentally assign work to a resource for completion. With regard to integration into practical application and whether additional elements amount to significantly more, Claims 9 and 19 fail both prongs of Step 2A, thus the claims are directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, Claims 9 and 19 do not recite patent eligible subject matter under 35 U.S.C. § 101.
Claims 10 and 20: “the battery-powered portable computing device comprises at least one of a: mobile telephone, a portable digital assistant (PDA), a portable game console, a VR console, a palmtop computer, or a tablet computer”, merely recite insignificant extra-solution data gathering activity which do not integrate the judicial exception into a practical application. See MPEP § 2106.05(g). With regard to integration into practical application and whether additional elements amount to significantly more, Claims 10 and 20 fail both prongs of Step 2A, thus the claims are directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more, performing a well understood, routine, and conventional task of data gathering. “The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. i. Receiving or transmitting data over a network”. See MPEP § 2106.05(d)(II). Therefore, Claims 10 and 20 do not recite patent eligible subject matter under 35 U.S.C. § 101.
Claim 20: “first processing means and second processing means comprise at least one of: a central processing unit, a multicore processing unit, a digital signal processor, a graphics processing unit, and a combination thereof”, recites a field of use which generally links the use of a judicial exception to a particular technological environment (MPEP § 2106.05(h)). With regard to integration into practical application and whether additional elements amount to significantly more, Claim 22 fails both prongs of Step 2A, thus the claims are directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, Claim 22 does not recite patent eligible subject matter under 35 U.S.C. § 101.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-5, 8, 10-11, 13-15, 18, 20-22, and 24-25 are rejected under 35 U.S.C. 103(a) as being unpatentable over Bae et al. (US 20210248010 A1) (hereinafter Bae), in view of Weissmann et al. (US 20210200656 A1) (hereinafter Weissmann),
Regarding Claim 1, Bae teaches:
A method for prioritizing and assigning threads in a CPU architecture,
“the processor 320 may allocate one of a plurality of cores (or central processing unit (CPU)) as a core to process a thread related to the generation of a plurality of frames in order to reduce the first time”, (Bae: ¶72), “the processor 120 may include a main processor 121 (e.g., a central processing unit (CPU) or an application processor (AP))”, (Bae: ¶31), “the size of load of the thread may be a value indicating a usage amount, a usage weight, or a usage rate of the thread used by the processor 320”, (Bae: ¶73), “when determining a core to process the thread related to the generation of a plurality of frames, the scheduler (not shown) may calculate the size of load of the thread related to the generation of the plurality of frames. The scheduler may determine the core to process the thread related to the generation of the plurality of frames on the basis of a sum of the size of load of the thread related to the generation of the plurality of frames and the size of load of the thread related to a task different from the generation of frames”, (Bae: ¶74), “he scheduler 432 may perform an operation of allocating cores 441, 442, and 443 to process thread related to the generation of the frame on the basis of the size of load of the thread related to the generation of the frame and/or the size of load of the thread related to another task”, (Bae: ¶105)
comprising: receiving input to create frames on a display device of battery-powered portable computing device at a predetermined rate;
“the electronic device 101 may include” … “an input device 150” … “a display device 160” … “a power management module 188, a battery 189”, (Bae: ¶30), “The input device 150 may receive a command or data to be used by other component (e.g., the processor 120) of the electronic device 101, from the outside (e.g., a user)”, (Bae: ¶35), “an embodiment of controlling the processor 320 or cores implemented in the processor 320 (for example, a first core 441, a second core 442, and/or an Nth core 443 of FIG. 4) for generating a plurality of frames to allow the electronic device 300 to generate the frame within the maximum time allocated for generating one frame will be described”, (Bae: ¶63), “a thread related to the generation of a plurality of frames”, (Bae: ¶72), “The frame rate may be defined in units of frame per second (fps) which means the number of frames per second” … “configures a frame rate of the display 310 as 120 fps, the display 310 may display 120 frames per second”, (Bae: ¶61).
identifying threads of execution responsible for creating the frames and which correspond to a number of first CPU cores in the CPU architecture,
“The electronic device includes a memory, a display, and a processor including a plurality of cores generating a plurality of frames including a first frame and a second frame” … “determine a size of a load for processing a thread related to generation of the second frame” … “allocate at least one of the plurality of cores as cores to process the thread, based on the determined size of the load, determine an operation frequency of the cores, based on the determined size of the load, and control the cores to generate the second frame according to the determined operation frequency”, (Bae: Abstract), “the processor 320 may allocate one of a plurality of cores (or central processing unit (CPU)) as a core to process a thread related to the generation of a plurality of frames in order to reduce the first time”, (Bae: ¶72), “when determining a core to process the thread related to the generation of a plurality of frames, the scheduler (not shown) may calculate the size of load of the thread related to the generation of the plurality of frames. The scheduler may determine the core to process the thread related to the generation of the plurality of frames…”, (Bae: ¶74).
Further regarding Claim 1, Bae fails to teach:
the CPU architecture comprising first CPU cores and second CPU cores, each first CPU core has a first processing capacity and each second CPU core has a second processing capacity, the first processing capacity being greater than the second processing capacity;
However, Weissman teaches: “Current heterogeneous processing systems include a mix of high power, high performance “big” cores and energy efficient “small” cores”, (Weissmann: ¶2), “. Assume that the processor has a full power budget (e.g., 5 W), and that PE A has higher performance than PE B when receiving the full power budget. Accordingly, as shown in FIG. 14A, a first performance ranking 1400 indicates that PE A is ranked higher than PE B”, (Weissmann: ¶151, Fig 14A), “the performance order ranking may reflect the relative performance capabilities of the PEs (e.g., from fast processing to slowest processing)”, (Weissmann: ¶144), “PERF/BIG CORES 1751” … “EFFICIENCY CORES 1752”, (Weissmann: Fig 17).
for a predetermined time period, creating a ranking of the threads according to their workload levels;
However, Weissman teaches: “the PE monitors 1310 may monitor metrics such as instructions per clock cycle, power consumed per time period”, (Weissmann: ¶140), “the scheduler 1710 performs a thread allocation analysis periodically (e.g., every 15 ms, 20 ms, etc) to perform the above performance and/or efficiency comparisons”, (Weissmann: ¶227), “As shown in FIG. 13A, the guide logic 1300 may include processing engine (PE) monitors 1310, thread monitors 1320, thread agnostic (TA) rank logic 1330, prediction logic 1335, thread specific (TS) rank logic 1340”, (Weissmann: ¶139), “TA rankings 1350 may include a performance order ranking, an efficiency order ranking, an energy order ranking, and an offline order ranking. In some embodiments, the performance order ranking may reflect the relative performance capabilities of the PEs (e.g., from fast processing to slowest processing)”, (Weissmann: ¶144, Fig 13B), “The first time a thread/workload is executed, it may be assigned a default class (e.g., Class 0). The table manager 1745 then analyzes the feedback results when executed in the default class, and if a more efficient categorization is available, the table manager 1745 assigns this particular thread/workload to a different class”, (Weissmann: ¶180).
determining a present workload level of each first CPU core;
However, Weissman teaches: “the PE monitors 1310 may monitor metrics such as instructions per clock cycle, power consumed per time period, percentage of maximum performance, average power state, temperature, percentage of lifecycle that has elapsed, total number of power cycles, maximum power level, and so forth”, (Weissmann: ¶140).
creating a ranking of the first CPU cores according to their present workload levels;
However, Weissman teaches: “the TA rank logic 1330 may use data from the PE monitors 1310 and/or the prediction logic 1335 to generate one or more TA rankings 1350. In some embodiments, each TA ranking 1350 may include a list of PEs arranged in a particular thread agnostic order” … “the performance order ranking may reflect the relative performance capabilities of the PEs (e.g., from fast processing to slowest processing). The efficiency order ranking may reflect the relative energy efficiency capabilities of the PEs (e.g., from most efficient to least efficient). The energy order ranking may reflect the relative power consumption of the PEs”, (Weissmann: ¶144).
and assigning each thread to a single first CPU core according to the ranking of the first CPU cores and according to the ranking of the threads.
However, Weissman teaches: “the scheduler to determine whether to migrate a second thread from the logical processors of the first logical processor type to a logical processor of the second logical processor type based on an evaluation of first and second performance values associated with execution of the first thread on the first or second logical processor types, respectively, and further based on an evaluation of third and fourth performance values associated with execution of the second thread on the first or second logical processor types”, (Weissmann: Abstract), “EVALUATE WHETHER TO MIGRATE ANY RUNNING THREADS FROM A HIGHEST PERFORMANCE LP BASED ON A COMPARISON OF PERFORMANCE VALUES ASSOCIATED WITH RUNNING THREADS AND NEW THREAD ON DIFFERENT LPs”, (Weissmann: Fig 18).
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to combine the CPU architecture comprising first CPU cores and second CPU cores, each first CPU core has a first processing capacity and each second CPU core has a second processing capacity, the first processing capacity being greater than the second processing capacity; for a predetermined time period, creating a ranking of the threads according to their workload levels; determining a present workload level of each first CPU core; creating a ranking of the first CPU cores according to their present workload levels; and assigning each thread to a single first CPU core according to the ranking of the first CPU cores and according to the ranking of the threads of Weissmann with the methods and systems of Bae resulting in a system that can rank threads based on workloads for processing on a heterogeneous CPU architecture. A person having ordinary skill in the art would have been motivated to make this combination, with a reasonable expectation of success, for the purpose of “optimally allocate software threads to cores or other processing resources for optimal performance and/or energy consumption”, (Weissmann: ¶164), “address several challenges including assisting the OS to identify the most appropriate core or logical processor type, helping the OS to schedule the right software thread to the right core and set relative priorities between threads when there are more threads then high perf cores, and helping the OS to schedule the most appropriate software thread to the most appropriate core or logical processor type to implement the best energy and power savings”, (Weissmann: ¶165).
Regarding Claim 3, Bae teaches:
the CPU architecture comprises a prime CPU core, and the method further comprises assigning the prime CPU core with a highest priority thread having a highest workload.
“The processor 320 may compare the first load size with the second load size and use a larger load size for processing the thread related to the generation of a plurality of frames” … “determine (or change) a core to process the thread using a larger value between the first load size and the second load size”, (Bae: ¶79), “When the corrected size of the load is larger than the size of the load calculated by the scheduler, the electronic device 300 may perform thread processing using a core having a higher performance”, (Bae: ¶77).
Further regarding Claim 3, Bae fails to teach:
the CPU architecture comprises a prime CPU core, and the method further comprises assigning the prime CPU core with a highest priority thread having a highest workload.
However, Weissmann teaches: “systems include a mix of high power, high performance “big” cores and energy efficient “small” cores”, (Weissmann: ¶2), “the embodiments of the invention address several challenges including assisting the OS to identify the most appropriate core or logical processor type, helping the OS to schedule the right software thread to the right core and set relative priorities between threads when there are more threads then high perf cores”, (Weissmann: ¶165), “For a “High Priority” thread, the relevant column is determined based on the thread class index (k). In one embodiment, the index is provided by a feedback MSR 1755. On the thread performance class column (k), a row is identified with the highest performance value. If the corresponding logical processor is free, then the thread is scheduled on this logical processor”, (Weissmann: ¶214), “Those threads with the highest ratios are then allocated to the highest performance or efficiency logical processors while the others are scheduled (or migrated) on the next best performance or efficiency logical processors”, (Weissmann: ¶225).
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to combine the CPU architecture comprises a prime CPU core, and the method further comprises assigning the prime CPU core with a highest priority thread having a highest workload of Weissmann with the methods and systems of Bae resulting in a system that contains separate sets of cores with different processing capacities. A person having ordinary skill in the art would have been motivated to make this combination, with a reasonable expectation of success, for the purpose of “optimally allocate software threads to cores or other processing resources for optimal performance and/or energy consumption”, (Weissmann: ¶164), “address several challenges including assisting the OS to identify the most appropriate core or logical processor type, helping the OS to schedule the right software thread to the right core and set relative priorities between threads when there are more threads then high perf cores, and helping the OS to schedule the most appropriate software thread to the most appropriate core or logical processor type to implement the best energy and power savings”, (Weissmann: ¶165).
Regarding Claim 4, Bae fails to teach:
after assigning the prime CPU core with the highest priority thread having a highest workload, assigning any remaining ranked among the first CPU cores.
However, Weissmann teaches: “the thread with the larger index is executed on the highest efficiency logical processor, while the other thread is run (or migrated) to an alternate logical processor”, (Weissmann: ¶224), “Those threads with the highest ratios are then allocated to the highest performance or efficiency logical processors while the others are scheduled (or migrated) on the next best performance or efficiency logical processors”, (Weissmann: ¶225), “the scheduling order is: (1) schedule first on the core with highest performance/energy; (2) second, scheduled on the core with the lower perf/energy capabilities; and (3) finally, schedule on the core with SMT support”, (Weissmann: ¶168), “the scheduler 1710 relies on (or includes) a guide/mapping unit 1714 to evaluate different thread/logical processor mappings in view of the global table 1740 to determine which thread should be mapped to which logical processor. The scheduler 1710 may then implement the mapping”, (Weissmann: ¶176). Examiner notes: the scheduler iteratively plans the placement of each thread to cores.
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to combine after assigning the prime CPU core with the highest priority thread having a highest workload, assigning any remaining ranked among the first CPU cores of Weissmann with the methods and systems of Bae resulting in a system that can assign all pending threads based on their rankings. A person having ordinary skill in the art would have been motivated to make this combination, with a reasonable expectation of success, for the purpose of “optimally allocate software threads to cores or other processing resources for optimal performance and/or energy consumption”, (Weissmann: ¶164), “address several challenges including assisting the OS to identify the most appropriate core or logical processor type, helping the OS to schedule the right software thread to the right core and set relative priorities between threads when there are more threads then high perf cores, and helping the OS to schedule the most appropriate software thread to the most appropriate core or logical processor type to implement the best energy and power savings”, (Weissmann: ¶165).
Regarding Claim 5, Bae teaches:
the predetermined time period comprises a multiple of a display device refresh rate.
“the processor 320 may determine the second time on the basis of a period of a synchronization signal (Vsync) used for generating the frame by the application manager 201 or the surfaceflinger”, (Bae: ¶66), “For example, when the processor 320 configures a frame rate of the display 310 as 60 fps, the processor 320 may be required to complete the generation of one frame within about 16.6 ms. In another example, when the processor 320 configures a frame rate of the display 310 as 120 fps, the processor 320 may be required to complete the generation of one frame within about 8.3 ms”, (Bae: ¶62).
Regarding Claim 8, Bae fails to teach:
a thread of execution assigned to a first CPU core will continue to use a same first CPU core until the thread gets ranked as the highest priority heaviest thread at the end of the predetermined time period at which point the highest priority thread will be moved onto a single prime core or one of multiple prime cores for a subsequent predetermined time period.
However, Weissmann teaches: “If the ratio for the new thread is greater, then the running thread is migrated to its alternate logical processor. if the ratio for the running thread is greater, then the new thread will be scheduled on its alternate logical processor.”, (Weissman: ¶221), “If the ratio is greater for the running thread, then the new thread is scheduled on the secondary LP (which will provide it with the second highest performance)”, (Weissmann: ¶222), “Those threads with the highest ratios are then allocated to the highest performance or efficiency logical processors while the others are scheduled (or migrated) on the next best performance or efficiency logical processors”, (Weissmann: ¶ 225), “the scheduler 1710 performs a thread allocation analysis periodically (e.g., every 15 ms, 20 ms, etc) to perform the above performance and/or efficiency comparisons. If a higher performance or improved energy efficiency option is available, it will then migrate one or more threads between logical processors to achieve this higher performance or higher efficiency option”, (Weissmann: ¶227). Examiner notes: a currently running thread remains on its current processor unless a newly scheduled thread has the superior performance/priority ratio in which the running thread with a high ratio receives a higher priority.
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to combine a thread of execution assigned to a first CPU core will continue to use a same first CPU core until the thread gets ranked as the highest priority heaviest thread at the end of the predetermined time period at which point the highest priority thread will be moved onto a single prime core or one of multiple prime cores for a subsequent predetermined time period of Weissmann with the methods and systems of Bae resulting in a system that can prioritize running a thread with a heavier workload on a faster resource. A person having ordinary skill in the art would have been motivated to make this combination, with a reasonable expectation of success, for the purpose of “optimally allocate software threads to cores or other processing resources for optimal performance and/or energy consumption”, (Weissmann: ¶164), “address several challenges including assisting the OS to identify the most appropriate core or logical processor type, helping the OS to schedule the right software thread to the right core and set relative priorities between threads when there are more threads then high perf cores, and helping the OS to schedule the most appropriate software thread to the most appropriate core or logical processor type to implement the best energy and power savings”, (Weissmann: ¶165).
Regarding Claim 10, Bae teaches:
the battery-powered portable computing device comprises at least one of a: mobile telephone, a portable digital assistant (PDA), a portable game console, a VR console, a palmtop computer, or a tablet computer.
“Various electronic devices such as smart phones, tablet personal computers (PCs), portable multimedia players (PMPs), personal digital assistants (PDAs), laptop PCs, and wearable devices are widely spread”, (Bae: ¶3), “The computer program product may be distributed in the form of” … “online via an application store (e.g., PlayStore™), or between two user devices (e.g., smart phones) directly”, (Bae: ¶173), “The electronic devices may include, for example, a portable communication device (e.g., a smartphone), a computer device, a portable multimedia device, a portable medical device, a camera, a wearable device, or a home appliance”, (Bae: ¶169).
Regarding Claim 11, Bae teaches:
A system for prioritizing and assigning threads in a CPU architecture,
“the processor 320 may allocate one of a plurality of cores (or central processing unit (CPU)) as a core to process a thread related to the generation of a plurality of frames in order to reduce the first time”, (Bae: ¶72), “the processor 120 may include a main processor 121 (e.g., a central processing unit (CPU) or an application processor (AP))”, (Bae: ¶31), “the size of load of the thread may be a value indicating a usage amount, a usage weight, or a usage rate of the thread used by the processor 320”, (Bae: ¶73), “when determining a core to process the thread related to the generation of a plurality of frames, the scheduler (not shown) may calculate the size of load of the thread related to the generation of the plurality of frames. The scheduler may determine the core to process the thread related to the generation of the plurality of frames on the basis of a sum of the size of load of the thread related to the generation of the plurality of frames and the size of load of the thread related to a task different from the generation of frames”, (Bae: ¶74), “he scheduler 432 may perform an operation of allocating cores 441, 442, and 443 to process thread related to the generation of the frame on the basis of the size of load of the thread related to the generation of the frame and/or the size of load of the thread related to another task”, (Bae: ¶105)
comprising: a scheduler configured to receive input to create frames on a display device of battery-powered portable computing device at a predetermined rate,
“the electronic device 101 may include” … “an input device 150” … “a display device 160” … “a power management module 188, a battery 189”, (Bae: ¶30), “The input device 150 may receive a command or data to be used by other component (e.g., the processor 120) of the electronic device 101, from the outside (e.g., a user)”, (Bae: ¶35), “an embodiment of controlling the processor 320 or cores implemented in the processor 320 (for example, a first core 441, a second core 442, and/or an Nth core 443 of FIG. 4) for generating a plurality of frames to allow the electronic device 300 to generate the frame within the maximum time allocated for generating one frame will be described”, (Bae: ¶63), “a thread related to the generation of a plurality of frames”, (Bae: ¶72), “The frame rate may be defined in units of frame per second (fps) which means the number of frames per second” … “configures a frame rate of the display 310 as 120 fps, the display 310 may display 120 frames per second”, (Bae: ¶61).
the scheduler being configured to identify threads of execution responsible for creating the frames and which correspond to a number of first CPU cores in the CPU architecture,
“The electronic device includes a memory, a display, and a processor including a plurality of cores generating a plurality of frames including a first frame and a second frame” … “determine a size of a load for processing a thread related to generation of the second frame” … “allocate at least one of the plurality of cores as cores to process the thread, based on the determined size of the load, determine an operation frequency of the cores, based on the determined size of the load, and control the cores to generate the second frame according to the determined operation frequency”, (Bae: Abstract), “the processor 320 may allocate one of a plurality of cores (or central processing unit (CPU)) as a core to process a thread related to the generation of a plurality of frames in order to reduce the first time”, (Bae: ¶72), “when determining a core to process the thread related to the generation of a plurality of frames, the scheduler (not shown) may calculate the size of load of the thread related to the generation of the plurality of frames. The scheduler may determine the core to process the thread related to the generation of the plurality of frames…”, (Bae: ¶74).
Further regarding Claim 11, Bae fails to teach:
the CPU architecture comprising first CPU cores and second CPU cores, each first CPU core having a first processing capacity and each second CPU core having a second processing capacity, the first processing capacity being greater than the second processing capacity;
However, Weissman teaches: “Current heterogeneous processing systems include a mix of high power, high performance “big” cores and energy efficient “small” cores”, (Weissmann: ¶2), “. Assume that the processor has a full power budget (e.g., 5 W), and that PE A has higher performance than PE B when receiving the full power budget. Accordingly, as shown in FIG. 14A, a first performance ranking 1400 indicates that PE A is ranked higher than PE B”, (Weissmann: ¶151, Fig 14A), “the performance order ranking may reflect the relative performance capabilities of the PEs (e.g., from fast processing to slowest processing)”, (Weissmann: ¶144), “PERF/BIG CORES 1751” … “EFFICIENCY CORES 1752”, (Weissmann: Fig 17).
and wherein for a predetermined time period, the scheduler is configured to create a ranking of the threads according to their workload levels;
However, Weissman teaches: “the PE monitors 1310 may monitor metrics such as instructions per clock cycle, power consumed per time period”, (Weissmann: ¶140), “the scheduler 1710 performs a thread allocation analysis periodically (e.g., every 15 ms, 20 ms, etc) to perform the above performance and/or efficiency comparisons”, (Weissmann: ¶227), “As shown in FIG. 13A, the guide logic 1300 may include processing engine (PE) monitors 1310, thread monitors 1320, thread agnostic (TA) rank logic 1330, prediction logic 1335, thread specific (TS) rank logic 1340”, (Weissmann: ¶139), “TA rankings 1350 may include a performance order ranking, an efficiency order ranking, an energy order ranking, and an offline order ranking. In some embodiments, the performance order ranking may reflect the relative performance capabilities of the PEs (e.g., from fast processing to slowest processing)”, (Weissmann: ¶144, Fig 13B), “The first time a thread/workload is executed, it may be assigned a default class (e.g., Class 0). The table manager 1745 then analyzes the feedback results when executed in the default class, and if a more efficient categorization is available, the table manager 1745 assigns this particular thread/workload to a different class”, (Weissmann: ¶180).
the scheduler being configured to determine a present workload level of each first CPU core;
However, Weissman teaches: “the PE monitors 1310 may monitor metrics such as instructions per clock cycle, power consumed per time period, percentage of maximum performance, average power state, temperature, percentage of lifecycle that has elapsed, total number of power cycles, maximum power level, and so forth”, (Weissmann: ¶140).
the scheduler being configured to create a ranking of the first CPU cores according to their present workload levels;
However, Weissman teaches: “the TA rank logic 1330 may use data from the PE monitors 1310 and/or the prediction logic 1335 to generate one or more TA rankings 1350. In some embodiments, each TA ranking 1350 may include a list of PEs arranged in a particular thread agnostic order” … “the performance order ranking may reflect the relative performance capabilities of the PEs (e.g., from fast processing to slowest processing). The efficiency order ranking may reflect the relative energy efficiency capabilities of the PEs (e.g., from most efficient to least efficient). The energy order ranking may reflect the relative power consumption of the PEs”, (Weissmann: ¶144).
and the scheduler being configured to assign each thread to a single first CPU core according to the ranking of the first CPU cores and according to the ranking of the threads.
However, Weissman teaches: “the scheduler to determine whether to migrate a second thread from the logical processors of the first logical processor type to a logical processor of the second logical processor type based on an evaluation of first and second performance values associated with execution of the first thread on the first or second logical processor types, respectively, and further based on an evaluation of third and fourth performance values associated with execution of the second thread on the first or second logical processor types”, (Weissmann: Abstract), “EVALUATE WHETHER TO MIGRATE ANY RUNNING THREADS FROM A HIGHEST PERFORMANCE LP BASED ON A COMPARISON OF PERFORMANCE VALUES ASSOCIATED WITH RUNNING THREADS AND NEW THREAD ON DIFFERENT LPs”, (Weissmann: Fig 18).
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to combine the CPU architecture comprising first CPU cores and second CPU cores, each first CPU core has a first processing capacity and each second CPU core has a second processing capacity, the first processing capacity being greater than the second processing capacity; for a predetermined time period, creating a ranking of the threads according to their workload levels; determining a present workload level of each first CPU core; creating a ranking of the first CPU cores according to their present workload levels; and assigning each thread to a single first CPU core according to the ranking of the first CPU cores and according to the ranking of the threads of Weissmann with the methods and systems of Bae resulting in a system that can rank threads based on workloads for processing on a heterogeneous CPU architecture. A person having ordinary skill in the art would have been motivated to make this combination, with a reasonable expectation of success, for the purpose of “optimally allocate software threads to cores or other processing resources for optimal performance and/or energy consumption”, (Weissmann: ¶164), “address several challenges including assisting the OS to identify the most appropriate core or logical processor type, helping the OS to schedule the right software thread to the right core and set relative priorities between threads when there are more threads then high perf cores, and helping the OS to schedule the most appropriate software thread to the most appropriate core or logical processor type to implement the best energy and power savings”, (Weissmann: ¶165).
Regarding Claim 13, Bae teaches:
the CPU architecture comprises a single or multiple prime CPU cores, and the system further comprises the single prime core or one of the multiple prime CPU cores being assigned with a highest priority thread having a highest workload.
“The processor 320 may compare the first load size with the second load size and use a larger load size for processing the thread related to the generation of a plurality of frames” … “determine (or change) a core to process the thread using a larger value between the first load size and the second load size”, (Bae: ¶79), “When the corrected size of the load is larger than the size of the load calculated by the scheduler, the electronic device 300 may perform thread processing using a core having a higher performance”, (Bae: ¶77).
Further regarding Claim 13, Bae fails to teach:
the CPU architecture comprises a single or multiple prime CPU cores, and the system further comprises the single prime core or one of the multiple prime CPU cores being assigned with a highest priority thread having a highest workload.
However, Weissmann teaches: “systems include a mix of high power, high performance “big” cores and energy efficient “small” cores”, (Weissmann: ¶2), “the embodiments of the invention address several challenges including assisting the OS to identify the most appropriate core or logical processor type, helping the OS to schedule the right software thread to the right core and set relative priorities between threads when there are more threads then high perf cores”, (Weissmann: ¶165), “For a “High Priority” thread, the relevant column is determined based on the thread class index (k). In one embodiment, the index is provided by a feedback MSR 1755. On the thread performance class column (k), a row is identified with the highest performance value. If the corresponding logical processor is free, then the thread is scheduled on this logical processor”, (Weissmann: ¶214), “Those threads with the highest ratios are then allocated to the highest performance or efficiency logical processors while the others are scheduled (or migrated) on the next best performance or efficiency logical processors”, (Weissmann: ¶225).
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to combine the CPU architecture comprises a single or multiple prime CPU cores, and the system further comprises the single prime core or one of the multiple prime CPU cores being assigned with a highest priority thread having a highest workload of Weissmann with the methods and systems of Bae resulting in a system that contains separate sets of cores with different processing capacities. A person having ordinary skill in the art would have been motivated to make this combination, with a reasonable expectation of success, for the purpose of “optimally allocate software threads to cores or other processing resources for optimal performance and/or energy consumption”, (Weissmann: ¶164), “address several challenges including assisting the OS to identify the most appropriate core or logical processor type, helping the OS to schedule the right software thread to the right core and set relative priorities between threads when there are more threads then high perf cores, and helping the OS to schedule the most appropriate software thread to the most appropriate core or logical processor type to implement the best energy and power savings”, (Weissmann: ¶165).
Regarding Claim 14, Bae fails to teach:
after assigning the single prime core or one of the multiple prime CPU cores with the highest priority thread having a highest workload, the scheduler assigning any remaining ranked among the first CPU cores.
However, Weissmann teaches: “the thread with the larger index is executed on the highest efficiency logical processor, while the other thread is run (or migrated) to an alternate logical processor”, (Weissmann: ¶224), “Those threads with the highest ratios are then allocated to the highest performance or efficiency logical processors while the others are scheduled (or migrated) on the next best performance or efficiency logical processors”, (Weissmann: ¶225), “the scheduling order is: (1) schedule first on the core with highest performance/energy; (2) second, scheduled on the core with the lower perf/energy capabilities; and (3) finally, schedule on the core with SMT support”, (Weissmann: ¶168), “the scheduler 1710 relies on (or includes) a guide/mapping unit 1714 to evaluate different thread/logical processor mappings in view of the global table 1740 to determine which thread should be mapped to which logical processor. The scheduler 1710 may then implement the mapping”, (Weissmann: ¶176). Examiner notes: the scheduler iteratively plans the placement of each thread to cores.
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to combine after assigning the single prime core or one of the multiple prime CPU cores with the highest priority thread having a highest workload, the scheduler assigning any remaining ranked among the first CPU cores of Weissmann with the methods and systems of Bae resulting in a system that can assign all pending threads based on their rankings. A person having ordinary skill in the art would have been motivated to make this combination, with a reasonable expectation of success, for the purpose of “optimally allocate software threads to cores or other processing resources for optimal performance and/or energy consumption”, (Weissmann: ¶164), “address several challenges including assisting the OS to identify the most appropriate core or logical processor type, helping the OS to schedule the right software thread to the right core and set relative priorities between threads when there are more threads then high perf cores, and helping the OS to schedule the most appropriate software thread to the most appropriate core or logical processor type to implement the best energy and power savings”, (Weissmann: ¶165).
Regarding Claim 15, Bae teaches:
the predetermined time period comprises a multiple of a display device refresh rate.
“the processor 320 may determine the second time on the basis of a period of a synchronization signal (Vsync) used for generating the frame by the application manager 201 or the surfaceflinger”, (Bae: ¶66), “For example, when the processor 320 configures a frame rate of the display 310 as 60 fps, the processor 320 may be required to complete the generation of one frame within about 16.6 ms. In another example, when the processor 320 configures a frame rate of the display 310 as 120 fps, the processor 320 may be required to complete the generation of one frame within about 8.3 ms”, (Bae: ¶62).
Regarding Claim 18, Bae fail to teach:
a thread of execution assigned to a first CPU core will continue to use a same first CPU core until the thread gets ranked as the highest priority heaviest thread at the end of the predetermined time period at which point the highest priority thread will be moved onto the single prime core or one of the multiple prime cores for a subsequent predetermined time period.
However, Weissmann teaches: “If the ratio for the new thread is greater, then the running thread is migrated to its alternate logical processor. if the ratio for the running thread is greater, then the new thread will be scheduled on its alternate logical processor.”, (Weissman: ¶221), “If the ratio is greater for the running thread, then the new thread is scheduled on the secondary LP (which will provide it with the second highest performance)”, (Weissmann: ¶222), “Those threads with the highest ratios are then allocated to the highest performance or efficiency logical processors while the others are scheduled (or migrated) on the next best performance or efficiency logical processors”, (Weissmann: ¶ 225), “the scheduler 1710 performs a thread allocation analysis periodically (e.g., every 15 ms, 20 ms, etc) to perform the above performance and/or efficiency comparisons. If a higher performance or improved energy efficiency option is available, it will then migrate one or more threads between logical processors to achieve this higher performance or higher efficiency option”, (Weissmann: ¶227). Examiner notes: a currently running thread remains on its current processor unless a newly scheduled thread has the superior performance/priority ratio in which the running thread with a high ratio receives a higher priority.
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to combine a thread of execution assigned to a first CPU core will continue to use a same first CPU core until the thread gets ranked as the highest priority heaviest thread at the end of the predetermined time period at which point the highest priority thread will be moved onto the single prime core or one of the multiple prime cores for a subsequent predetermined time period of Weissmann with the methods and systems of Bae resulting in a system that can prioritize running a thread with a heavier workload on a faster resource. A person having ordinary skill in the art would have been motivated to make this combination, with a reasonable expectation of success, for the purpose of “optimally allocate software threads to cores or other processing resources for optimal performance and/or energy consumption”, (Weissmann: ¶164), “address several challenges including assisting the OS to identify the most appropriate core or logical processor type, helping the OS to schedule the right software thread to the right core and set relative priorities between threads when there are more threads then high perf cores, and helping the OS to schedule the most appropriate software thread to the most appropriate core or logical processor type to implement the best energy and power savings”, (Weissmann: ¶165).
Regarding Claim 20, Bae teaches:
the battery-powered portable computing device comprises at least one of a: mobile telephone, a portable digital assistant (PDA), a portable game console, a VR console, a palmtop computer, or a tablet computer.
“Various electronic devices such as smart phones, tablet personal computers (PCs), portable multimedia players (PMPs), personal digital assistants (PDAs), laptop PCs, and wearable devices are widely spread”, (Bae: ¶3), “The computer program product may be distributed in the form of” … “online via an application store (e.g., PlayStore™), or between two user devices (e.g., smart phones) directly”, (Bae: ¶173), “The electronic devices may include, for example, a portable communication device (e.g., a smartphone), a computer device, a portable multimedia device, a portable medical device, a camera, a wearable device, or a home appliance”, (Bae: ¶169).
Regarding Claim 21, Bae teaches:
A system for prioritizing and assigning threads in a CPU architecture,
“the processor 320 may allocate one of a plurality of cores (or central processing unit (CPU)) as a core to process a thread related to the generation of a plurality of frames in order to reduce the first time”, (Bae: ¶72), “the processor 120 may include a main processor 121 (e.g., a central processing unit (CPU) or an application processor (AP))”, (Bae: ¶31), “the size of load of the thread may be a value indicating a usage amount, a usage weight, or a usage rate of the thread used by the processor 320”, (Bae: ¶73), “when determining a core to process the thread related to the generation of a plurality of frames, the scheduler (not shown) may calculate the size of load of the thread related to the generation of the plurality of frames. The scheduler may determine the core to process the thread related to the generation of the plurality of frames on the basis of a sum of the size of load of the thread related to the generation of the plurality of frames and the size of load of the thread related to a task different from the generation of frames”, (Bae: ¶74), “he scheduler 432 may perform an operation of allocating cores 441, 442, and 443 to process thread related to the generation of the frame on the basis of the size of load of the thread related to the generation of the frame and/or the size of load of the thread related to another task”, (Bae: ¶105).
comprising: a scheduler for receiving input to create frames on a display device of battery-powered portable computing device at a predetermined rate,
“the electronic device 101 may include” … “an input device 150” … “a display device 160” … “a power management module 188, a battery 189”, (Bae: ¶30), “The input device 150 may receive a command or data to be used by other component (e.g., the processor 120) of the electronic device 101, from the outside (e.g., a user)”, (Bae: ¶35), “an embodiment of controlling the processor 320 or cores implemented in the processor 320 (for example, a first core 441, a second core 442, and/or an Nth core 443 of FIG. 4) for generating a plurality of frames to allow the electronic device 300 to generate the frame within the maximum time allocated for generating one frame will be described”, (Bae: ¶63), “a thread related to the generation of a plurality of frames”, (Bae: ¶72), “The frame rate may be defined in units of frame per second (fps) which means the number of frames per second” … “configures a frame rate of the display 310 as 120 fps, the display 310 may display 120 frames per second”, (Bae: ¶61).
the scheduler identifying threads of execution responsible for creating the frames and which correspond to a number of first processing means in the CPU architecture,
“The electronic device includes a memory, a display, and a processor including a plurality of cores generating a plurality of frames including a first frame and a second frame” … “determine a size of a load for processing a thread related to generation of the second frame” … “allocate at least one of the plurality of cores as cores to process the thread, based on the determined size of the load, determine an operation frequency of the cores, based on the determined size of the load, and control the cores to generate the second frame according to the determined operation frequency”, (Bae: Abstract), “the processor 320 may allocate one of a plurality of cores (or central processing unit (CPU)) as a core to process a thread related to the generation of a plurality of frames in order to reduce the first time”, (Bae: ¶72), “when determining a core to process the thread related to the generation of a plurality of frames, the scheduler (not shown) may calculate the size of load of the thread related to the generation of the plurality of frames. The scheduler may determine the core to process the thread related to the generation of the plurality of frames…”, (Bae: ¶74).
Further regarding Claim 21, Bae fails to teach:
the CPU architecture comprising first processing means and second processing means, each first processing means has a first processing capacity and each second processing means has a second processing capacity, the first processing capacity being greater than the second processing capacity;
However, Weissman teaches: “Current heterogeneous processing systems include a mix of high power, high performance “big” cores and energy efficient “small” cores”, (Weissmann: ¶2), “. Assume that the processor has a full power budget (e.g., 5 W), and that PE A has higher performance than PE B when receiving the full power budget. Accordingly, as shown in FIG. 14A, a first performance ranking 1400 indicates that PE A is ranked higher than PE B”, (Weissmann: ¶151, Fig 14A), “the performance order ranking may reflect the relative performance capabilities of the PEs (e.g., from fast processing to slowest processing)”, (Weissmann: ¶144), “PERF/BIG CORES 1751” … “EFFICIENCY CORES 1752”, (Weissmann: Fig 17).
and wherein for a predetermined time period, the scheduler creating a ranking of the threads according to their workload levels;
However, Weissman teaches: “the PE monitors 1310 may monitor metrics such as instructions per clock cycle, power consumed per time period”, (Weissmann: ¶140), “the scheduler 1710 performs a thread allocation analysis periodically (e.g., every 15 ms, 20 ms, etc) to perform the above performance and/or efficiency comparisons”, (Weissmann: ¶227), “As shown in FIG. 13A, the guide logic 1300 may include processing engine (PE) monitors 1310, thread monitors 1320, thread agnostic (TA) rank logic 1330, prediction logic 1335, thread specific (TS) rank logic 1340”, (Weissmann: ¶139), “TA rankings 1350 may include a performance order ranking, an efficiency order ranking, an energy order ranking, and an offline order ranking. In some embodiments, the performance order ranking may reflect the relative performance capabilities of the PEs (e.g., from fast processing to slowest processing)”, (Weissmann: ¶144, Fig 13B), “The first time a thread/workload is executed, it may be assigned a default class (e.g., Class 0). The table manager 1745 then analyzes the feedback results when executed in the default class, and if a more efficient categorization is available, the table manager 1745 assigns this particular thread/workload to a different class”, (Weissmann: ¶180).
the scheduler determining a present workload level of each first processing means;
However, Weissman teaches: “the PE monitors 1310 may monitor metrics such as instructions per clock cycle, power consumed per time period, percentage of maximum performance, average power state, temperature, percentage of lifecycle that has elapsed, total number of power cycles, maximum power level, and so forth”, (Weissmann: ¶140).
the scheduler creating a ranking of the first processing means according to their present workload levels;
However, Weissman teaches: “the TA rank logic 1330 may use data from the PE monitors 1310 and/or the prediction logic 1335 to generate one or more TA rankings 1350. In some embodiments, each TA ranking 1350 may include a list of PEs arranged in a particular thread agnostic order” … “the performance order ranking may reflect the relative performance capabilities of the PEs (e.g., from fast processing to slowest processing). The efficiency order ranking may reflect the relative energy efficiency capabilities of the PEs (e.g., from most efficient to least efficient). The energy order ranking may reflect the relative power consumption of the PEs”, (Weissmann: ¶144).
and the scheduler assigning each thread to a single first processing means according to the ranking of the first processing means and according to the ranking of the threads.
However, Weissman teaches: “the scheduler to determine whether to migrate a second thread from the logical processors of the first logical processor type to a logical processor of the second logical processor type based on an evaluation of first and second performance values associated with execution of the first thread on the first or second logical processor types, respectively, and further based on an evaluation of third and fourth performance values associated with execution of the second thread on the first or second logical processor types”, (Weissmann: Abstract), “EVALUATE WHETHER TO MIGRATE ANY RUNNING THREADS FROM A HIGHEST PERFORMANCE LP BASED ON A COMPARISON OF PERFORMANCE VALUES ASSOCIATED WITH RUNNING THREADS AND NEW THREAD ON DIFFERENT LPs”, (Weissmann: Fig 18).
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to combine the CPU architecture comprising first processing means and second processing means, each first processing means has a first processing capacity and each second processing means has a second processing capacity, the first processing capacity being greater than the second processing capacity; and wherein for a predetermined time period, the scheduler creating a ranking of the threads according to their workload levels the scheduler determining a present workload level of each first processing means the scheduler creating a ranking of the first processing means according to their present workload levels and the scheduler assigning each thread to a single first processing means according to the ranking of the first processing means and according to the ranking of the threads of Weissmann with the methods and systems of Bae resulting in a system that can rank threads based on workloads for processing on a heterogeneous CPU architecture. A person having ordinary skill in the art would have been motivated to make this combination, with a reasonable expectation of success, for the purpose of “optimally allocate software threads to cores or other processing resources for optimal performance and/or energy consumption”, (Weissmann: ¶164), “address several challenges including assisting the OS to identify the most appropriate core or logical processor type, helping the OS to schedule the right software thread to the right core and set relative priorities between threads when there are more threads then high perf cores, and helping the OS to schedule the most appropriate software thread to the most appropriate core or logical processor type to implement the best energy and power savings”, (Weissmann: ¶165).
Regarding Claim 22, Bae teaches:
first processing means and second processing means comprise at least one of: a central processing unit, a multicore processing unit, a digital signal processor, a graphics processing unit, and a combination thereof.
“the processor 320 may perform an operation of allocating a core (or a central processing unit)…”, (Bae: ¶71), “the processor 320 may allocate one of a plurality of cores (or central processing unit (CPU))…”, (Bae: ¶72), “the processor 120 may include a main processor 121 (e.g., a central processing unit (CPU) or an application processor (AP)), and an auxiliary processor 123 (e.g., a graphics processing unit (GPU), an image signal processor (ISP), a sensor hub processor, or a communication processor (CP)) that is operable independently from, or in conjunction with, the main processor 121”, (Bae: ¶31).
Regarding Claim 24, Bae teaches:
the CPU architecture comprises a single prime core or multiple prime CPU cores, and the system further comprises the single prime core or one of the multiple prime CPU cores being assigned with a highest priority thread having a highest workload.
“The processor 320 may compare the first load size with the second load size and use a larger load size for processing the thread related to the generation of a plurality of frames” … “determine (or change) a core to process the thread using a larger value between the first load size and the second load size”, (Bae: ¶79), “When the corrected size of the load is larger than the size of the load calculated by the scheduler, the electronic device 300 may perform thread processing using a core having a higher performance”, (Bae: ¶77).
Further regarding Claim 24, Bae fails to teach:
the CPU architecture comprises a single prime core or multiple prime CPU cores, and the system further comprises the single prime core or one of the multiple prime CPU cores being assigned with a highest priority thread having a highest workload.
However, Weissmann teaches: “systems include a mix of high power, high performance “big” cores and energy efficient “small” cores”, (Weissmann: ¶2), “the embodiments of the invention address several challenges including assisting the OS to identify the most appropriate core or logical processor type, helping the OS to schedule the right software thread to the right core and set relative priorities between threads when there are more threads then high perf cores”, (Weissmann: ¶165), “For a “High Priority” thread, the relevant column is determined based on the thread class index (k). In one embodiment, the index is provided by a feedback MSR 1755. On the thread performance class column (k), a row is identified with the highest performance value. If the corresponding logical processor is free, then the thread is scheduled on this logical processor”, (Weissmann: ¶214), “Those threads with the highest ratios are then allocated to the highest performance or efficiency logical processors while the others are scheduled (or migrated) on the next best performance or efficiency logical processors”, (Weissmann: ¶225).
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to combine the CPU architecture comprises a single prime core or multiple prime CPU cores, and the system further comprises the single prime core or one of the multiple prime CPU cores being assigned with a highest priority thread having a highest workload of Weissmann with the methods and systems of Bae resulting in a system that contains separate sets of cores with different processing capacities. A person having ordinary skill in the art would have been motivated to make this combination, with a reasonable expectation of success, for the purpose of “optimally allocate software threads to cores or other processing resources for optimal performance and/or energy consumption”, (Weissmann: ¶164), “address several challenges including assisting the OS to identify the most appropriate core or logical processor type, helping the OS to schedule the right software thread to the right core and set relative priorities between threads when there are more threads then high perf cores, and helping the OS to schedule the most appropriate software thread to the most appropriate core or logical processor type to implement the best energy and power savings”, (Weissmann: ¶165).
Regarding Claim 25, Bae teaches:
A computer program product for prioritizing and assigning threads in a CPU architecture, the computer program product comprising a non-transitory computer-readable medium having stored thereon in computer-executable form instructions
“including one or more instructions that are stored in a storage medium (e.g., internal memory 136 or external memory 138) that is readable by a machine (e.g., the electronic device 101)” … “ay invoke at least one of the one or more instructions stored in the storage medium, and execute it, with or without using one or more other components under the control of the processor.” … “This allows the machine to be operated to perform at least one function according to the at least one instruction invoked. The one or more instructions may include a code generated by a complier or a code executable by an interpreter”, (Bae: ¶172), “the processor 320 may allocate one of a plurality of cores (or central processing unit (CPU)) as a core to process a thread related to the generation of a plurality of frames in order to reduce the first time”, (Bae: ¶72), “the processor 120 may include a main processor 121 (e.g., a central processing unit (CPU) or an application processor (AP))”, (Bae: ¶31), “the size of load of the thread may be a value indicating a usage amount, a usage weight, or a usage rate of the thread used by the processor 320”, (Bae: ¶73), “when determining a core to process the thread related to the generation of a plurality of frames, the scheduler (not shown) may calculate the size of load of the thread related to the generation of the plurality of frames. The scheduler may determine the core to process the thread related to the generation of the plurality of frames on the basis of a sum of the size of load of the thread related to the generation of the plurality of frames and the size of load of the thread related to a task different from the generation of frames”, (Bae: ¶74), “he scheduler 432 may perform an operation of allocating cores 441, 442, and 443 to process thread related to the generation of the frame on the basis of the size of load of the thread related to the generation of the frame and/or the size of load of the thread related to another task”, (Bae: ¶105).
that when executed by CPU architecture configure the CPU architecture to: receive input to create frames on a display device of battery-powered portable computing device at a predetermined rate;
“the electronic device 101 may include” … “an input device 150” … “a display device 160” … “a power management module 188, a battery 189”, (Bae: ¶30), “The input device 150 may receive a command or data to be used by other component (e.g., the processor 120) of the electronic device 101, from the outside (e.g., a user)”, (Bae: ¶35), “an embodiment of controlling the processor 320 or cores implemented in the processor 320 (for example, a first core 441, a second core 442, and/or an Nth core 443 of FIG. 4) for generating a plurality of frames to allow the electronic device 300 to generate the frame within the maximum time allocated for generating one frame will be described”, (Bae: ¶63), “a thread related to the generation of a plurality of frames”, (Bae: ¶72), “The frame rate may be defined in units of frame per second (fps) which means the number of frames per second” … “configures a frame rate of the display 310 as 120 fps, the display 310 may display 120 frames per second”, (Bae: ¶61).
identify threads of execution responsible for creating the frames and which correspond to a number of first CPU cores in the CPU architecture,
“The electronic device includes a memory, a display, and a processor including a plurality of cores generating a plurality of frames including a first frame and a second frame” … “determine a size of a load for processing a thread related to generation of the second frame” … “allocate at least one of the plurality of cores as cores to process the thread, based on the determined size of the load, determine an operation frequency of the cores, based on the determined size of the load, and control the cores to generate the second frame according to the determined operation frequency”, (Bae: Abstract), “the processor 320 may allocate one of a plurality of cores (or central processing unit (CPU)) as a core to process a thread related to the generation of a plurality of frames in order to reduce the first time”, (Bae: ¶72), “when determining a core to process the thread related to the generation of a plurality of frames, the scheduler (not shown) may calculate the size of load of the thread related to the generation of the plurality of frames. The scheduler may determine the core to process the thread related to the generation of the plurality of frames…”, (Bae: ¶74).
Further regarding Claim 25, Bae fails to teach:
the CPU architecture comprising first CPU cores and second CPU cores, each first CPU core has a first processing capacity and each second CPU core has a second processing capacity, the first processing capacity being greater than the second processing capacity;
However, Weissman teaches: “Current heterogeneous processing systems include a mix of high power, high performance “big” cores and energy efficient “small” cores”, (Weissmann: ¶2), “. Assume that the processor has a full power budget (e.g., 5 W), and that PE A has higher performance than PE B when receiving the full power budget. Accordingly, as shown in FIG. 14A, a first performance ranking 1400 indicates that PE A is ranked higher than PE B”, (Weissmann: ¶151, Fig 14A), “the performance order ranking may reflect the relative performance capabilities of the PEs (e.g., from fast processing to slowest processing)”, (Weissmann: ¶144), “PERF/BIG CORES 1751” … “EFFICIENCY CORES 1752”, (Weissmann: Fig 17).
for a predetermined time period, create a ranking of the threads according to their workload levels;
However, Weissman teaches: “the PE monitors 1310 may monitor metrics such as instructions per clock cycle, power consumed per time period”, (Weissmann: ¶140), “the scheduler 1710 performs a thread allocation analysis periodically (e.g., every 15 ms, 20 ms, etc) to perform the above performance and/or efficiency comparisons”, (Weissmann: ¶227), “As shown in FIG. 13A, the guide logic 1300 may include processing engine (PE) monitors 1310, thread monitors 1320, thread agnostic (TA) rank logic 1330, prediction logic 1335, thread specific (TS) rank logic 1340”, (Weissmann: ¶139), “TA rankings 1350 may include a performance order ranking, an efficiency order ranking, an energy order ranking, and an offline order ranking. In some embodiments, the performance order ranking may reflect the relative performance capabilities of the PEs (e.g., from fast processing to slowest processing)”, (Weissmann: ¶144, Fig 13B), “The first time a thread/workload is executed, it may be assigned a default class (e.g., Class 0). The table manager 1745 then analyzes the feedback results when executed in the default class, and if a more efficient categorization is available, the table manager 1745 assigns this particular thread/workload to a different class”, (Weissmann: ¶180).
determine a present workload level of each first CPU core;
However, Weissman teaches: “the PE monitors 1310 may monitor metrics such as instructions per clock cycle, power consumed per time period, percentage of maximum performance, average power state, temperature, percentage of lifecycle that has elapsed, total number of power cycles, maximum power level, and so forth”, (Weissmann: ¶140).
create a ranking of the first CPU cores according to their present workload levels;
However, Weissman teaches: “the TA rank logic 1330 may use data from the PE monitors 1310 and/or the prediction logic 1335 to generate one or more TA rankings 1350. In some embodiments, each TA ranking 1350 may include a list of PEs arranged in a particular thread agnostic order” … “the performance order ranking may reflect the relative performance capabilities of the PEs (e.g., from fast processing to slowest processing). The efficiency order ranking may reflect the relative energy efficiency capabilities of the PEs (e.g., from most efficient to least efficient). The energy order ranking may reflect the relative power consumption of the PEs”, (Weissmann: ¶144).
and assign each thread to a single first CPU core according to the ranking of the first CPU cores and according to the ranking of the threads.
However, Weissman teaches: “the scheduler to determine whether to migrate a second thread from the logical processors of the first logical processor type to a logical processor of the second logical processor type based on an evaluation of first and second performance values associated with execution of the first thread on the first or second logical processor types, respectively, and further based on an evaluation of third and fourth performance values associated with execution of the second thread on the first or second logical processor types”, (Weissmann: Abstract), “EVALUATE WHETHER TO MIGRATE ANY RUNNING THREADS FROM A HIGHEST PERFORMANCE LP BASED ON A COMPARISON OF PERFORMANCE VALUES ASSOCIATED WITH RUNNING THREADS AND NEW THREAD ON DIFFERENT LPs”, (Weissmann: Fig 18).
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to combine the CPU architecture comprising first CPU cores and second CPU cores, each first CPU core has a first processing capacity and each second CPU core has a second processing capacity, the first processing capacity being greater than the second processing capacity; for a predetermined time period, create a ranking of the threads according to their workload levels; determine a present workload level of each first CPU core; create a ranking of the first CPU cores according to their present workload levels; and assign each thread to a single first CPU core according to the ranking of the first CPU cores and according to the ranking of the threads of Weissmann with the methods and systems of Bae resulting in a system that can rank threads based on workloads for processing on a heterogeneous CPU architecture. A person having ordinary skill in the art would have been motivated to make this combination, with a reasonable expectation of success, for the purpose of “optimally allocate software threads to cores or other processing resources for optimal performance and/or energy consumption”, (Weissmann: ¶164), “address several challenges including assisting the OS to identify the most appropriate core or logical processor type, helping the OS to schedule the right software thread to the right core and set relative priorities between threads when there are more threads then high perf cores, and helping the OS to schedule the most appropriate software thread to the most appropriate core or logical processor type to implement the best energy and power savings”, (Weissmann: ¶165).
Claims 2, 12, 23 and 26-30 are rejected under 35 U.S.C. 103(a) as being unpatentable over Bae in view of Weissmann, in further view of Park et al. (US 20200151005 A1) (hereinafter Park) and Duluk et al. (US 20190235928 A1) (hereinafter Duluk).
Regarding Claim 2, Bae in view of Weissmann fails to teach:
first CPU cores with the lighter workload levels receive higher priority threads having higher workload levels, and first CPU cores with heavier workload levels receive lower priority threads having lighter workload levels.
However, Park teaches: “The scheduler 136 may select an optimal CPU core, e.g., a target core (TC), by comparing the linear priority weight LPW of the schedule-requested task with the preemption compare index PCI of cores included in the limited core selection boundary LCSB” … “The scheduler 136 may assign the schedule-requested task to the selected CPU core depending on the comparison result”, (Park: ¶45), “The preemption compare index PCI is a new parameter that indicates the current load state of the candidate cores”, (Park: ¶57), “the mobile device 100 may perform more flexible scheduling depending on the priority of the schedule-requested task and the load state of the current CPU cores”, (Park: ¶35), “the scheduler 136 may select a core (hereinafter, referred to as a “target core”) that will execute a task, in consideration of not only the priority but also the utilization of the current cores, the expected power consumption, a cache reusable ratio, or the like”, (Park: ¶54). Examiner notes: Park teaches a system that considers the availability of processing resources when assigning threads to them, however it is noted that a more explicit teaching of higher priority items being assigned to high available resource is still missing hence the addition of Duluk later in this Office action.
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to combine first CPU cores with the lighter workload levels receive higher priority threads having higher workload levels, and first CPU cores with heavier workload levels receive lower priority threads having lighter workload levels of Park with the methods and systems of Bae in view of Weissmann resulting in a system that allocate threads based on availability. A person having ordinary skill in the art would have been motivated to make this combination, with a reasonable expectation of success, for the purpose of “to increase the power or processing speed of an application processor performing heterogeneous multi-processing (HMP)”, (Park: ¶93).
Further regarding Claim 2, Park fails to explicitly teach:
first CPU cores with the lighter workload levels receive higher priority threads having higher workload levels, and first CPU cores with heavier workload levels receive lower priority threads having lighter workload levels.
However, Duluk teaches: “the load balancer 422 places each received task in an appropriate location on the task table 436 and the priority-sorted task table 438” … “The load balancer 422 may consider resource bids received from each TRT 425 when selecting a TPC 340 to execute CTAs for a particular task, as further described herein”, (Duluk: ¶97), “the load balancer 422 selects the highest priority task that is eligible to execute on one or more TPCs 340”, (Duluk: ¶62), “the load balancer 422 selects a TPC 340 to execute the current CTA based on the TPC 340 that has the highest number of available CTA execution slots”, (Duluk: ¶63).
While Duluk does not explicitly teach “first CPU cores with heavier workload levels receive lower priority threads having lighter workload levels”, it does teach sending high priority tasks to high availability resources in “the load balancer 422 selects a TPC 340 to execute the current CTA based on the TPC 340 that has the highest number of available CTA execution slots”, (Duluk: ¶63). Sending high priority tasks to high availability resources is similar to “first CPU cores with heavier workload levels receive lower priority threads having lighter workload levels” because it does the same thing but in vice versa. It would have been obvious that sending high priority tasks to high availability resources encompasses “first CPU cores with heavier workload levels receive lower priority threads having lighter workload levels” for handling the other end of the spectrum of low priority tasks in a priority based scheduler.
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to combine first CPU cores with the lighter workload levels receive higher priority threads having higher workload levels, and first CPU cores with heavier workload levels receive lower priority threads having lighter workload levels of Duluk with the methods and systems of Bae in view of Weissmann and Park resulting in a system that allocate threads based on availability for both low and high priority threads. A person having ordinary skill in the art would have been motivated to make this combination, with a reasonable expectation of success, for the purpose of “provide improved fairness in scheduling and allocation relative to prior approaches”, (Duluk: ¶81).
Regarding Claim 12, Bae in view of Weissmann fails to teach:
first CPU cores with the lighter workload levels receive higher priority threads having higher workload levels, and first CPU cores with heavier workload levels receive lower priority threads having lighter workload levels.
However, Park teaches: “The scheduler 136 may select an optimal CPU core, e.g., a target core (TC), by comparing the linear priority weight LPW of the schedule-requested task with the preemption compare index PCI of cores included in the limited core selection boundary LCSB” … “The scheduler 136 may assign the schedule-requested task to the selected CPU core depending on the comparison result”, (Park: ¶45), “The preemption compare index PCI is a new parameter that indicates the current load state of the candidate cores”, (Park: ¶57), “the mobile device 100 may perform more flexible scheduling depending on the priority of the schedule-requested task and the load state of the current CPU cores”, (Park: ¶35), “the scheduler 136 may select a core (hereinafter, referred to as a “target core”) that will execute a task, in consideration of not only the priority but also the utilization of the current cores, the expected power consumption, a cache reusable ratio, or the like”, (Park: ¶54). Examiner notes: Park teaches a system that considers the availability of processing resources when assigning threads to them, however it is noted that a more explicit teaching of higher priority items being assigned to high available resource is still missing hence the addition of Duluk later in this Office action.
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to combine first CPU cores with the lighter workload levels receive higher priority threads having higher workload levels, and first CPU cores with heavier workload levels receive lower priority threads having lighter workload levels of Park with the methods and systems of Bae in view of Weissmann resulting in a system that allocate threads based on availability. A person having ordinary skill in the art would have been motivated to make this combination, with a reasonable expectation of success, for the purpose of “to increase the power or processing speed of an application processor performing heterogeneous multi-processing (HMP)”, (Park: ¶93).
Further Regarding Claim 12, Park fails to explicitly teach:
first CPU cores with the lighter workload levels receive higher priority threads having higher workload levels, and first CPU cores with heavier workload levels receive lower priority threads having lighter workload levels.
However, Duluk teaches: “the load balancer 422 places each received task in an appropriate location on the task table 436 and the priority-sorted task table 438” … “The load balancer 422 may consider resource bids received from each TRT 425 when selecting a TPC 340 to execute CTAs for a particular task, as further described herein”, (Duluk: ¶97), “the load balancer 422 selects the highest priority task that is eligible to execute on one or more TPCs 340”, (Duluk: ¶62), “the load balancer 422 selects a TPC 340 to execute the current CTA based on the TPC 340 that has the highest number of available CTA execution slots”, (Duluk: ¶63).
While Duluk does not explicitly teach “first CPU cores with heavier workload levels receive lower priority threads having lighter workload levels”, it does teach sending high priority tasks to high availability resources in “the load balancer 422 selects a TPC 340 to execute the current CTA based on the TPC 340 that has the highest number of available CTA execution slots”, (Duluk: ¶63). Sending high priority tasks to high availability resources is similar to “first CPU cores with heavier workload levels receive lower priority threads having lighter workload levels” because it does the same thing but in vice versa. It would have been obvious that sending high priority tasks to high availability resources encompasses “first CPU cores with heavier workload levels receive lower priority threads having lighter workload levels” for handling the other end of the spectrum of low priority tasks in a priority based scheduler.
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to combine first CPU cores with the lighter workload levels receive higher priority threads having higher workload levels, and first CPU cores with heavier workload levels receive lower priority threads having lighter workload levels of Duluk with the methods and systems of Bae in view of Weissmann and Park resulting in a system that allocate threads based on availability for both low and high priority threads. A person having ordinary skill in the art would have been motivated to make this combination, with a reasonable expectation of success, for the purpose of “provide improved fairness in scheduling and allocation relative to prior approaches”, (Duluk: ¶81).
Regarding Claim 23, Bae in view of Weissmann fails to teach:
first processing means with the lighter workload levels receive higher priority threads having higher workload levels, and first processing means with heavier workload levels receive lower priority threads having lighter workload levels.
However, Park teaches: “The scheduler 136 may select an optimal CPU core, e.g., a target core (TC), by comparing the linear priority weight LPW of the schedule-requested task with the preemption compare index PCI of cores included in the limited core selection boundary LCSB” … “The scheduler 136 may assign the schedule-requested task to the selected CPU core depending on the comparison result”, (Park: ¶45), “The preemption compare index PCI is a new parameter that indicates the current load state of the candidate cores”, (Park: ¶57), “the mobile device 100 may perform more flexible scheduling depending on the priority of the schedule-requested task and the load state of the current CPU cores”, (Park: ¶35), “the scheduler 136 may select a core (hereinafter, referred to as a “target core”) that will execute a task, in consideration of not only the priority but also the utilization of the current cores, the expected power consumption, a cache reusable ratio, or the like”, (Park: ¶54). Examiner notes: Park teaches a system that considers the availability of processing resources when assigning threads to them, however it is noted that a more explicit teaching of higher priority items being assigned to high available resource is still missing hence the addition of Duluk later in this Office action.
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to combine first processing means with the lighter workload levels receive higher priority threads having higher workload levels, and first processing means with heavier workload levels receive lower priority threads having lighter workload levels of Park with the methods and systems of Bae in view of Weissmann resulting in a system that allocate threads based on availability. A person having ordinary skill in the art would have been motivated to make this combination, with a reasonable expectation of success, for the purpose of “to increase the power or processing speed of an application processor performing heterogeneous multi-processing (HMP)”, (Park: ¶93).
Further Regarding Claim 23, Park fails to explicitly teach:
first processing means with the lighter workload levels receive higher priority threads having higher workload levels, and first processing means with heavier workload levels receive lower priority threads having lighter workload levels.
However, Duluk teaches: “the load balancer 422 places each received task in an appropriate location on the task table 436 and the priority-sorted task table 438” … “The load balancer 422 may consider resource bids received from each TRT 425 when selecting a TPC 340 to execute CTAs for a particular task, as further described herein”, (Duluk: ¶97), “the load balancer 422 selects the highest priority task that is eligible to execute on one or more TPCs 340”, (Duluk: ¶62), “the load balancer 422 selects a TPC 340 to execute the current CTA based on the TPC 340 that has the highest number of available CTA execution slots”, (Duluk: ¶63).
While Duluk does not explicitly teach “first CPU cores with heavier workload levels receive lower priority threads having lighter workload levels”, it does teach sending high priority tasks to high availability resources in “the load balancer 422 selects a TPC 340 to execute the current CTA based on the TPC 340 that has the highest number of available CTA execution slots”, (Duluk: ¶63). Sending high priority tasks to high availability resources is similar to “first CPU cores with heavier workload levels receive lower priority threads having lighter workload levels” because it does the same thing but in vice versa. It would have been obvious that sending high priority tasks to high availability resources encompasses “first CPU cores with heavier workload levels receive lower priority threads having lighter workload levels” for handling the other end of the spectrum of low priority tasks in a priority based scheduler.
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to combine first processing means with the lighter workload levels receive higher priority threads having higher workload levels, and first processing means with heavier workload levels receive lower priority threads having lighter workload levels of Duluk with the methods and systems of Bae in view of Weissmann and Park resulting in a system that allocate threads based on availability for both low and high priority threads. A person having ordinary skill in the art would have been motivated to make this combination, with a reasonable expectation of success, for the purpose of “provide improved fairness in scheduling and allocation relative to prior approaches”, (Duluk: ¶81).
Regarding Claim 26, Bae in view of Weissmann fails to teach:
first CPU cores with the lighter workload levels receive higher priority threads having higher workload levels, and first CPU cores with heavier workload levels receive lower priority threads having lighter workload levels.
However, Park teaches: “The scheduler 136 may select an optimal CPU core, e.g., a target core (TC), by comparing the linear priority weight LPW of the schedule-requested task with the preemption compare index PCI of cores included in the limited core selection boundary LCSB” … “The scheduler 136 may assign the schedule-requested task to the selected CPU core depending on the comparison result”, (Park: ¶45), “The preemption compare index PCI is a new parameter that indicates the current load state of the candidate cores”, (Park: ¶57), “the mobile device 100 may perform more flexible scheduling depending on the priority of the schedule-requested task and the load state of the current CPU cores”, (Park: ¶35), “the scheduler 136 may select a core (hereinafter, referred to as a “target core”) that will execute a task, in consideration of not only the priority but also the utilization of the current cores, the expected power consumption, a cache reusable ratio, or the like”, (Park: ¶54). Examiner notes: Park teaches a system that considers the availability of processing resources when assigning threads to them, however it is noted that a more explicit teaching of higher priority items being assigned to high available resource is still missing hence the addition of Duluk later in this Office action.
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to combine first CPU cores with the lighter workload levels receive higher priority threads having higher workload levels, and first CPU cores with heavier workload levels receive lower priority threads having lighter workload levels of Park with the methods and systems of Bae in view of Weissmann resulting in a system that allocate threads based on availability. A person having ordinary skill in the art would have been motivated to make this combination, with a reasonable expectation of success, for the purpose of “to increase the power or processing speed of an application processor performing heterogeneous multi-processing (HMP)”, (Park: ¶93).
Further Regarding Claim 26, Park fails to explicitly teach:
first CPU cores with the lighter workload levels receive higher priority threads having higher workload levels, and first CPU cores with heavier workload levels receive lower priority threads having lighter workload levels.
However, Duluk teaches: “the load balancer 422 places each received task in an appropriate location on the task table 436 and the priority-sorted task table 438” … “The load balancer 422 may consider resource bids received from each TRT 425 when selecting a TPC 340 to execute CTAs for a particular task, as further described herein”, (Duluk: ¶97), “the load balancer 422 selects the highest priority task that is eligible to execute on one or more TPCs 340”, (Duluk: ¶62), “the load balancer 422 selects a TPC 340 to execute the current CTA based on the TPC 340 that has the highest number of available CTA execution slots”, (Duluk: ¶63).
While Duluk does not explicitly teach “first CPU cores with heavier workload levels receive lower priority threads having lighter workload levels”, it does teach sending high priority tasks to high availability resources in “the load balancer 422 selects a TPC 340 to execute the current CTA based on the TPC 340 that has the highest number of available CTA execution slots”, (Duluk: ¶63). Sending high priority tasks to high availability resources is similar to “first CPU cores with heavier workload levels receive lower priority threads having lighter workload levels” because it does the same thing but in vice versa. It would have been obvious that sending high priority tasks to high availability resources encompasses “first CPU cores with heavier workload levels receive lower priority threads having lighter workload levels” for handling the other end of the spectrum of low priority tasks in a priority based scheduler.
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to combine first CPU cores with the lighter workload levels receive higher priority threads having higher workload levels, and first CPU cores with heavier workload levels receive lower priority threads having lighter workload levels of Duluk with the methods and systems of Bae in view of Weissmann and Park resulting in a system that allocate threads based on availability for both low and high priority threads. A person having ordinary skill in the art would have been motivated to make this combination, with a reasonable expectation of success, for the purpose of “provide improved fairness in scheduling and allocation relative to prior approaches”, (Duluk: ¶81).
Regarding Claim 27, Bae teaches:
the CPU architecture comprises a single prime CPU core or multiple prime CPU cores, and the method further comprises assigning the single prime CPU core or one of the multiple prime CPU cores with a highest priority thread having a highest workload.
“The processor 320 may compare the first load size with the second load size and use a larger load size for processing the thread related to the generation of a plurality of frames” … “determine (or change) a core to process the thread using a larger value between the first load size and the second load size”, (Bae: ¶79), “When the corrected size of the load is larger than the size of the load calculated by the scheduler, the electronic device 300 may perform thread processing using a core having a higher performance”, (Bae: ¶77).
Further regarding Claim 27, Bae in view of Park and Duluk fails to teach:
the CPU architecture comprises a single prime CPU core or multiple prime CPU cores, and the method further comprises assigning the single prime CPU core or one of the multiple prime CPU cores with a highest priority thread having a highest workload.
However, Weissmann teaches: “systems include a mix of high power, high performance “big” cores and energy efficient “small” cores”, (Weissmann: ¶2), “the embodiments of the invention address several challenges including assisting the OS to identify the most appropriate core or logical processor type, helping the OS to schedule the right software thread to the right core and set relative priorities between threads when there are more threads then high perf cores”, (Weissmann: ¶165), “For a “High Priority” thread, the relevant column is determined based on the thread class index (k). In one embodiment, the index is provided by a feedback MSR 1755. On the thread performance class column (k), a row is identified with the highest performance value. If the corresponding logical processor is free, then the thread is scheduled on this logical processor”, (Weissmann: ¶214), “Those threads with the highest ratios are then allocated to the highest performance or efficiency logical processors while the others are scheduled (or migrated) on the next best performance or efficiency logical processors”, (Weissmann: ¶225).
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to combine the CPU architecture comprises a single prime CPU core or multiple prime CPU cores, and the method further comprises assigning the single prime CPU core or one of the multiple prime CPU cores with a highest priority thread having a highest workload of Weissmann with the methods and systems of Bae in view of Park and Duluk resulting in a system that contains separate sets of cores with different processing capacities. A person having ordinary skill in the art would have been motivated to make this combination, with a reasonable expectation of success, for the purpose of “optimally allocate software threads to cores or other processing resources for optimal performance and/or energy consumption”, (Weissmann: ¶164), “address several challenges including assisting the OS to identify the most appropriate core or logical processor type, helping the OS to schedule the right software thread to the right core and set relative priorities between threads when there are more threads then high perf cores, and helping the OS to schedule the most appropriate software thread to the most appropriate core or logical processor type to implement the best energy and power savings”, (Weissmann: ¶165).
Regarding Claim 28, Bae in view of Park and Duluk fails to teach:
after assigning a prime CPU core with the highest priority thread having a highest workload, assigning any remaining ranked among the first CPU cores.
However, Weissmann teaches: “the thread with the larger index is executed on the highest efficiency logical processor, while the other thread is run (or migrated) to an alternate logical processor”, (Weissmann: ¶224), “Those threads with the highest ratios are then allocated to the highest performance or efficiency logical processors while the others are scheduled (or migrated) on the next best performance or efficiency logical processors”, (Weissmann: ¶225), “the scheduling order is: (1) schedule first on the core with highest performance/energy; (2) second, scheduled on the core with the lower perf/energy capabilities; and (3) finally, schedule on the core with SMT support”, (Weissmann: ¶168), “the scheduler 1710 relies on (or includes) a guide/mapping unit 1714 to evaluate different thread/logical processor mappings in view of the global table 1740 to determine which thread should be mapped to which logical processor. The scheduler 1710 may then implement the mapping”, (Weissmann: ¶176). Examiner notes: the scheduler iteratively plans the placement of each thread to cores.
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to combine after assigning a prime CPU core with the highest priority thread having a highest workload, assigning any remaining ranked among the first CPU cores of Weissmann with the methods and systems of Bae in view of Park and Duluk resulting in a system that can assign all pending threads based on their rankings. A person having ordinary skill in the art would have been motivated to make this combination, with a reasonable expectation of success, for the purpose of “optimally allocate software threads to cores or other processing resources for optimal performance and/or energy consumption”, (Weissmann: ¶164), “address several challenges including assisting the OS to identify the most appropriate core or logical processor type, helping the OS to schedule the right software thread to the right core and set relative priorities between threads when there are more threads then high perf cores, and helping the OS to schedule the most appropriate software thread to the most appropriate core or logical processor type to implement the best energy and power savings”, (Weissmann: ¶165).
Regarding Claim 29, Bae teaches:
the predetermined time period comprises a multiple of a display device refresh rate.
“the processor 320 may determine the second time on the basis of a period of a synchronization signal (Vsync) used for generating the frame by the application manager 201 or the surfaceflinger”, (Bae: ¶66), “For example, when the processor 320 configures a frame rate of the display 310 as 60 fps, the processor 320 may be required to complete the generation of one frame within about 16.6 ms. In another example, when the processor 320 configures a frame rate of the display 310 as 120 fps, the processor 320 may be required to complete the generation of one frame within about 8.3 ms”, (Bae: ¶62).
Regarding Claim 30, Bae teaches:
identify the threads of execution responsible for creating the frames and which correspond only up to the number of first CPU cores in the CPU architecture.
“The application manager 421 may receive thread related to the generation of a plurality of frames and store identification information of the received thread (thread identification (TID))”, (Bae: ¶90), “the scheduler 432 may perform an operation of allocating cores 441, 442, and 443 to process thread related to the generation of the frame”, (Bae: ¶105), “The scheduler 432 may allocate (or change) the core to process the thread related to the generation of the frame among the first core 441, the second core 442, and/or the N.sup.th core 443, and the first core 441, the second core 442, and/or the N.sup.th core 443”, (Bae: ¶107), “the system server 424 may identify whether an application corresponding to the thread identifier is a foreground application or a background application”, (Bae: ¶96). Examiner notes: the system is identifying a thread corresponding to a foreground application which requires frames to be displayed.
Claims 6-7, and 16-17 are rejected under 35 U.S.C. 103(a) as being unpatentable over Bae in view of Weissmann, in further view of Banerjee et al. (US 20180260243 A1) (hereinafter Banerjee).
Regarding Claim 6, Bae teaches:
a completely fair scheduler identifies the threads of execution responsible for creating the frames and which correspond only up to the number of first CPU cores in the CPU architecture.
“The application manager 421 may receive thread related to the generation of a plurality of frames and store identification information of the received thread (thread identification (TID))”, (Bae: ¶90), “the scheduler 432 may perform an operation of allocating cores 441, 442, and 443 to process thread related to the generation of the frame”, (Bae: ¶105), “The scheduler 432 may allocate (or change) the core to process the thread related to the generation of the frame among the first core 441, the second core 442, and/or the N.sup.th core 443, and the first core 441, the second core 442, and/or the N.sup.th core 443”, (Bae: ¶107), “the system server 424 may identify whether an application corresponding to the thread identifier is a foreground application or a background application”, (Bae: ¶96). Examiner notes: the system is identifying a thread corresponding to a foreground application which requires frames to be displayed.
Further regarding Claim 6, Bae in view of Weissmann fails to teach:
a completely fair scheduler identifies the threads of execution responsible for creating the frames and which correspond only up to the number of first CPU cores in the CPU architecture.
However, Banerjee teaches: “The Completely Fair scheduler (CFS) is a task based scheduler in Linux operating system. The CFS schedules the entities on cores based on the execution history of the entities”, (Banerjee: ¶3), “The CFS algorithm primarily tracks the amount of time that a scheduling entity has run on a virtualized ideal multi-tasking processor…”, (Banerjee: ¶4), “In an embodiment, Completely Fair Queuing (CFQ) IO Scheduler unit 234 is in communication with the scheduler unit 102” … “the CFQ is an I/O scheduler for the Linux kernel. In an embodiment, the CFQ IO Scheduler unit 234 includes Block Request Queues unit 236, and IO time calculation unit 238”, (Banerjee: ¶50).
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to combine a completely fair scheduler identifies the threads of execution responsible for creating the frames and which correspond only up to the number of first CPU cores in the CPU architecture of Banerjee with the methods and systems of Bae in view of Weissmann resulting in a system that uses a completely fair scheduler. A person having ordinary skill in the art would have been motivated to make this combination, with a reasonable expectation of success, for the purpose of “the proposed mechanism provides a power efficient scheduler design without impacting the performance of an electronic device that includes the multi-core processor system. Further, the proposed method provides a mechanism for improving the power consumption of the electronic device”, (Banerjee: ¶28), “leading to a more energy efficient scheduler design whilst not impacting the performance of the electronic device 100”, (Banerjee: ¶35).
Regarding Claim 7, Bae in view of Weissmann fails to teach:
the completely fair scheduler receives data about the threads of execution from a thread hinting framework.
However, Banerjee teaches: “The Completely Fair scheduler (CFS) is a task based scheduler in Linux operating system. The CFS schedules the entities on cores based on the execution history of the entities” … “This led to a set of patches that added information regarding the per-entity utilization of a core to the CFS”, (Banerjee: ¶3), “the entity may be a task, a thread, a data flow, or the like.”, (Banerjee: ¶31), “the OOM Translation unit 218 is configured to translate OOM score to a scheduler understandable format.”, (Banerjee: ¶39), “The S.sub.platform value from the equation (1) is used as an input to the scheduler unit 102 by the platform OOM value unit 216”, (Banerjee: ¶45), “The OOM scores that are used by the platform categorize the entities based on characteristics of the entities. This is used by the scheduler unit 102 to categorize the entity as either the background entity or the non-background entity”, (Banerjee: ¶42), “the Cluster Selection unit 224 receives input from the Per-Task CPU Utilization unit 226. The Per-Task CPU Utilization unit 226 tracks the CPU utilization by the entity based on the input from the CPU metadata unit 228. The CPU metadata unit 226 tracts CPU utilization or CPU performance of the proposed mechanism”, (Banerjee: ¶47), “The input from the Update Task Statistics unit 220 includes an updated entity structure. The Update Task Statistics unit 220 updates entity statistics into structure of the entity based on frequency of execution data from the Task Tick unit 222”, (Banerjee: ¶58). Examiner notes: Banerjee’s CFS/scheduler unit receives scheduler usable thread characteristic data from platform/helper units that function as a thread hinting framework.
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to combine the completely fair scheduler receives data about the threads of execution from a thread hinting framework of Banerjee with the methods and systems of Bae in view of Weissmann resulting in a system that uses a completely fair scheduler that receives data to make better placement decisions. A person having ordinary skill in the art would have been motivated to make this combination, with a reasonable expectation of success, for the purpose of “the proposed mechanism provides a power efficient scheduler design without impacting the performance of an electronic device that includes the multi-core processor system. Further, the proposed method provides a mechanism for improving the power consumption of the electronic device”, (Banerjee: ¶28), “leading to a more energy efficient scheduler design whilst not impacting the performance of the electronic device 100”, (Banerjee: ¶35).
Regarding Claim 16, Bae teaches:
the scheduler identifies the threads of execution responsible for creating the frames and which correspond only up to the number of first CPU cores in the CPU architecture.
“The application manager 421 may receive thread related to the generation of a plurality of frames and store identification information of the received thread (thread identification (TID))”, (Bae: ¶90), “the scheduler 432 may perform an operation of allocating cores 441, 442, and 443 to process thread related to the generation of the frame”, (Bae: ¶105), “The scheduler 432 may allocate (or change) the core to process the thread related to the generation of the frame among the first core 441, the second core 442, and/or the N.sup.th core 443, and the first core 441, the second core 442, and/or the N.sup.th core 443”, (Bae: ¶107), “the system server 424 may identify whether an application corresponding to the thread identifier is a foreground application or a background application”, (Bae: ¶96). Examiner notes: the system is identifying a thread corresponding to a foreground application which requires frames to be displayed.
Regarding Claim 17, Bae in view of Weissmann fails to teach:
the scheduler receives data about the threads of execution from a thread hinting framework.
However, Banerjee teaches: “The Completely Fair scheduler (CFS) is a task based scheduler in Linux operating system. The CFS schedules the entities on cores based on the execution history of the entities” … “This led to a set of patches that added information regarding the per-entity utilization of a core to the CFS”, (Banerjee: ¶3), “the entity may be a task, a thread, a data flow, or the like.”, (Banerjee: ¶31), “the OOM Translation unit 218 is configured to translate OOM score to a scheduler understandable format.”, (Banerjee: ¶39), “The S.sub.platform value from the equation (1) is used as an input to the scheduler unit 102 by the platform OOM value unit 216”, (Banerjee: ¶45), “The OOM scores that are used by the platform categorize the entities based on characteristics of the entities. This is used by the scheduler unit 102 to categorize the entity as either the background entity or the non-background entity”, (Banerjee: ¶42), “the Cluster Selection unit 224 receives input from the Per-Task CPU Utilization unit 226. The Per-Task CPU Utilization unit 226 tracks the CPU utilization by the entity based on the input from the CPU metadata unit 228. The CPU metadata unit 226 tracts CPU utilization or CPU performance of the proposed mechanism”, (Banerjee: ¶47), “The input from the Update Task Statistics unit 220 includes an updated entity structure. The Update Task Statistics unit 220 updates entity statistics into structure of the entity based on frequency of execution data from the Task Tick unit 222”, (Banerjee: ¶58). Examiner notes: Banerjee’s CFS/scheduler unit receives scheduler usable thread characteristic data from platform/helper units that function as a thread hinting framework.
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to combine the scheduler receives data about the threads of execution from a thread hinting framework of Banerjee with the methods and systems of Bae in view of Weissmann resulting in a system that uses a completely fair scheduler that receives data to make better placement decisions. A person having ordinary skill in the art would have been motivated to make this combination, with a reasonable expectation of success, for the purpose of “the proposed mechanism provides a power efficient scheduler design without impacting the performance of an electronic device that includes the multi-core processor system. Further, the proposed method provides a mechanism for improving the power consumption of the electronic device”, (Banerjee: ¶28), “leading to a more energy efficient scheduler design whilst not impacting the performance of the electronic device 100”, (Banerjee: ¶35).
Claims 9 and 19 are rejected under 35 U.S.C. 103(a) as being unpatentable over Bae in view of Weissmann, in further view of Sangili et al. (US 20090037927 A1) (hereinafter Sangili).
Regarding Claim 9, Bae teaches:
if a thread of execution is assigned to a first CPU core, then the thread will continue to use the same first CPU core until frame rendering is complete.
“The electronic device includes a memory, a display, and a processor including a plurality of cores generating a plurality of frames including a first frame and a second frame” … “determine a size of a load for processing a thread related to generation of the second frame” … “allocate at least one of the plurality of cores as cores to process the thread, based on the determined size of the load, determine an operation frequency of the cores, based on the determined size of the load, and control the cores to generate the second frame according to the determined operation frequency”, (Bae: Abstract), “the processor 320 may allocate one of a plurality of cores (or central processing unit (CPU)) as a core to process a thread related to the generation of a plurality of frames in order to reduce the first time”, (Bae: ¶72), “when determining a core to process the thread related to the generation of a plurality of frames, the scheduler (not shown) may calculate the size of load of the thread related to the generation of the plurality of frames. The scheduler may determine the core to process the thread related to the generation of the plurality of frames…”, (Bae: ¶74).
Further regarding Claim 9, Bae in view of Weissmann fails to teach:
if a thread of execution is assigned to a first CPU core, then the thread will continue to use the same first CPU core until frame rendering is complete.
However, Sangili teaches: “A lock is associated with a shared resource (e.g., a CPU core) so that other threads will be blocked from accessing the shared resource until a currently running thread has completed its operation in the shared resource and has released the lock”, (Sangili: ¶2), “When the thread T1 has finished working on a resource and has released a lock (mutex) 141 for the core 105a, the thread T1 will issue a standard wakeup call 140 in a conventional manner to the thread T2, when thread T1 releases the lock 141 for the core 105a.”, (Sangili: ¶17).
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to combine if a thread of execution is assigned to a first CPU core, then the thread will continue to use the same first CPU core until frame rendering is complete of Sangili with the methods and systems of Bae in view of Weissmann resulting in a system that can display frames. A person having ordinary skill in the art would have been motivated to make this combination, with a reasonable expectation of success, for the purpose of “advantageously reduces the unnecessary contention on that resource by threads and wasted CPU consumption due to the unnecessary contention”, (Sangili: ¶15).
Regarding Claim 19, teaches:
if a thread of execution is assigned to a first CPU core, then the thread will continue to use the same first CPU core until frame rendering is complete
“The electronic device includes a memory, a display, and a processor including a plurality of cores generating a plurality of frames including a first frame and a second frame” … “determine a size of a load for processing a thread related to generation of the second frame” … “allocate at least one of the plurality of cores as cores to process the thread, based on the determined size of the load, determine an operation frequency of the cores, based on the determined size of the load, and control the cores to generate the second frame according to the determined operation frequency”, (Bae: Abstract), “the processor 320 may allocate one of a plurality of cores (or central processing unit (CPU)) as a core to process a thread related to the generation of a plurality of frames in order to reduce the first time”, (Bae: ¶72), “when determining a core to process the thread related to the generation of a plurality of frames, the scheduler (not shown) may calculate the size of load of the thread related to the generation of the plurality of frames. The scheduler may determine the core to process the thread related to the generation of the plurality of frames…”, (Bae: ¶74).
Further regarding Claim 19, Bae in view of Weissmann fails to teach:
if a thread of execution is assigned to a first CPU core, then the thread will continue to use the same first CPU core until frame rendering is complete
However, Sangili teaches: “A lock is associated with a shared resource (e.g., a CPU core) so that other threads will be blocked from accessing the shared resource until a currently running thread has completed its operation in the shared resource and has released the lock”, (Sangili: ¶2), “When the thread T1 has finished working on a resource and has released a lock (mutex) 141 for the core 105a, the thread T1 will issue a standard wakeup call 140 in a conventional manner to the thread T2, when thread T1 releases the lock 141 for the core 105a.”, (Sangili: ¶17).
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to combine if a thread of execution is assigned to a first CPU core, then the thread will continue to use the same first CPU core until frame rendering is complete of Sangili with the methods and systems of Bae in view of Weissmann resulting in a system that can display frames. A person having ordinary skill in the art would have been motivated to make this combination, with a reasonable expectation of success, for the purpose of “advantageously reduces the unnecessary contention on that resource by threads and wasted CPU consumption due to the unnecessary contention”, (Sangili: ¶15).
Conclusion
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/S.A./Examiner, Art Unit 2197
/BRADLEY A TEETS/Supervisory Patent Examiner, Art Unit 2197
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