DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 1 is objected to because of the following informalities: the limitation of “the dielectric structure including a dielectric material defining a plurality of voids and having a void percentage of at least 50%, wherein the dielectric structure and the plurality of voids alternate along a length of the signal line and both the dielectric structure and the plurality of voids are immediately adjacent and below the signal line with no intervening layer” may be interpreted such that the voids are part of the dielectric structure, causing confusion as to how the voids can alternate with the dielectric structure if they are part of the dielectric structure. The examiner suggests changing “wherein the dielectric structure and the plurality of voids alternate” to –wherein the dielectric material and the voids alternate-- Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-4, 7, & 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fjelstad et al. (US PGPub 20030214802)
As per claim 1:
Fjelstad et al. discloses in Fig. 1:
An apparatus comprising:
a signal line (conductors CD);
a lower ground plane (shield 130, [0059]) beneath the signal line and spaced therefrom;
a dielectric structure (dielectric support 110) supporting the signal line and located at least partially between the lower ground plane and the signal line, the dielectric structure including a dielectric material defining a plurality of voids and having a number and size of the openings that depends on desired design parameters ([0055-0056]), wherein the dielectric structure and the plurality of voids alternate along a length of the signal line (as seen in Figs. 1A-E) and both the dielectric structure and the plurality of voids are immediately adjacent and below the signal line with no intervening layer (as seen in Fig. 1A-B & D-E).
Fjelstad et al. does not disclose:
having a void percentage of at least 50%.
At the time of filing, it would have been obvious to one of ordinary skill in the art for the void percentage of Fjelstad et al. to be at least 50% as Fjelstad et al. discloses the number and width of the plurality of voids to be a design parameter, wherein the width of the voids is intended to be as wide as possible ([0055-056]) to provide the benefit of reducing dielectric constants and loss tangents, as taught by Fjelstad et al. ([0052])
As per claim 2:
Fjelstad et al. discloses in Fig. 1:
an upper ground plane (shield 140, [0059]) above the signal line and spaced therefrom, wherein the dielectric structure surrounds the signal line and supports the signal line between the upper and lower ground planes (as seen in Figs. 1A-E).
As per claim 3:
Fjelstad et al. discloses in Fig. 1:
the dielectric structure includes a plurality of spaced-apart dielectric support regions interspersed with the plurality of voids (as seen in Figs. 1D-E).
As per claim 4:
Fjelstad et al. discloses in Fig. 1:
the plurality of spaced-apart dielectric support regions are equally spaced (periodic, [0056]).
As per claim 7:
Fjelstad et al. discloses in Fig. 1:
the plurality of voids are filled with air ([0053]).
As per claim 9:
Fjelstad et al. discloses in Fig. 1:
the dielectric material includes a plurality of portions that are rectangular in cross section when viewed in a cross section along the long axis of the signal line (as seen in Figs. 1D-E).
Claim(s) 5 & 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over The resultant combination of Fjelstad et al. (US PGPub 20030214802) as applied to claims 1-3 above, and further in view of Sherman et al. (US Patent 6518844)
The resultant combination discloses the apparatus of claims 1-3, as rejected above.
As per claim 5:
The resultant combination does not disclose:
a left ground plane and a right ground plane supported by the dielectric structure and spaced left and right of the signal line when viewed in a cross section transverse to a long axis of the signal line.
Sherman et al. discloses in Fig.1:
A suspended transmission line (title) formed as a strip line with upper and lower void regions (cavities 70 & 72), wherein a signal line (first and second conductive strips 44 & 46) are formed with left and right ground planes (metallization layers 62) supported by a dielectric structure and spaced left and right of the signal line when viewed in a cross section transverse to a long axis of the signal line to provide an intermediate ground plane (col. 5 lines 34-67).
At the time of filing, it would have been obvious to one of ordinary skill in the art to form a left ground plane and a right ground plane supported by the dielectric structure and spaced left and right of the signal line when viewed in a cross-section transverse to a long axis of the signal line as disclosed by Sherman et al., as an art-recognized alternative configuration of a strip line as taught by Sherman et al. able to provide the same function and to provide the benefit of further shielding, as is well understood in the art.
As per claim 6:
The resultant combination does not disclose:
the left and right ground planes are fully supported by the dielectric structure.
Sherman et al. discloses in Fig.1:
A suspended transmission line (title) formed as a strip line with upper and lower void regions (cavities 70 & 72), wherein a signal line (first and second conductive strips 44 & 46) are formed with left and right ground planes (metallization layers 62) supported by a dielectric structure and spaced left and right of the signal line when viewed in a cross section transverse to a long axis of the signal line to provide an intermediate ground plane (col. 5 lines 34-67), wherein the left and right ground planes are fully supported by the dielectric structure (as seen in Fig. 1).
As a consequence of the combination of claim 5, the left and right ground planes are fully supported by the dielectric structure.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over The resultant combination of Fjelstad et al. (US PGPub 20030214802) as applied to claims 1-3 above, and further in view of Matsuda (US PGPub 20150305142)
The resultant combination discloses the apparatus of claims 1-3, as rejected above.
As per claim 8:
The resultant combination does not disclose:
the plurality of voids contain a vacuum.
Matsuda discloses in Figs. 1-13:
a plurality of voids (40) for a transmission line wherein the voids contain a vacuum ([0063]).
At the time of filing, it would have been obvious to one of ordinary skill in the art for the voids of Fjelstad et al. to contain a vacuum as an art-recognized alternative for the dielectric material of voids in a transmission line that provides the same function as taught by Matsuda ([0063]).
Claim(s) 10-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over The resultant combination of Fjelstad et al. (US PGPub 20030214802) as applied to claims 1-3 above, and further in view of Ma et al. (US PGPub 20230276719)
The resultant combination discloses the apparatus of claims 1-3, as rejected above.
As per claim 10:
The resultant combination does not disclose:
the signal line, the lower ground plane, the upper ground plane, and the dielectric structure have a length and first and second ends, further comprising a first quantum computing element coupled to the first end and a second quantum computing element coupled to the second end.
Ma et al. discloses in Fig. 1:
A quantum computing chip comprising signal lines (20), a first quantum computing element (qubits 40) coupled to a first end of each signal line, and a second quantum computing element (signal terminals 101) coupled to a second end of each signal line.
At the time of filing, it would have been obvious to one of ordinary skill in the art for the signal line of the resultant combination to be used as the signal line in an apparatus such as that of Ma et al. as an art-recognized alternative/equivalent transmission line able to provide the same function and that provides the benefit of resisting deformation and shielding/isolation as a strip line, as is well understood in the art.
As per claim 11:
The resultant combination does not disclose:
at least one of the first and second quantum computing elements comprises a physical manifestation of a qubit.
Ma et al. discloses in Fig. 1:
at least one of the first and second quantum computing elements comprises a physical manifestation of a qubit (40).
As a consequence of the combination of claim 10, the combination discloses at least one of the first and second quantum computing elements comprises a physical manifestation of a qubit.
As per claim 12:
The resultant combination does not disclose:
at least one of the first and second quantum computing elements comprises a readout port.
Ma et al. discloses in Fig. 1:
at least one of the first and second quantum computing elements comprises a signal port (101).
At the time of filing, it would have been obvious to one of ordinary skill in the art for the signal port of the combination to be a readout port, as one of a limited number of possibilities (input or output) for a signal port, wherein signal ports for qubits feature input and output ports to provide the benefit of functionality to the qubit, as is well understood in the art.
As per claim 13:
The resultant combination does not disclose:
at least one of the first and second quantum computing elements comprises a transmission line.
At the time of filing, it would have been obvious to one of ordinary skill in the art for at least one of the first and second quantum computing elements to comprise a transmission line, as connecting transmission lines is a well understood in the art method to provide the benefit of providing a signal path across distances or through different stages such as is commonly found in circuits comprising different temperatures such as those connected to super conducting stages or qubits, as is well understood in the art.
Response to Arguments
Applicant’s arguments, see applicant’s remarks, filed 03/18/2026, with respect to the rejection(s) of claim(s) 1-4 & 7-9 under Matsuda, 5-6 under Matsuda in view of Sherman, and 10-13 under Matsuda in view of Ma et al. have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Fjestad et al.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL S OUTTEN whose telephone number is (571)270-7123. The examiner can normally be reached M-F: 9:30AM-6:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached at (571) 272-1988. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Samuel S Outten/Primary Examiner, Art Unit 2843