CTFR 18/621,032 CTFR 88162 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Response to Amendment This office action has been issued in response to amendment filed on 04/28/2026. Claims 1, 7, 10, 14 and 16 have been amended. Claims 1-20 are pending, of which claims, of which claim 1, claim 10 and claim 16 are in independent form. Accordingly, this action has been made FINAL. 12-261 AIA Response to Argument Based on amended independent claim 1, claim 10 and claim 16, and based on applicant’s arguments, the 101 rejection for claims 1-20 has been withdrawn. 07-38 Applicant's arguments with respect to claim s 1-20 have been considered but are moot in view of the new ground(s) of rejection. 12-151 AIA 26-51 12-51 Status of Claims 5. Claims 1-20 are pending, of which claims, of which claim 1, claim 10 and 16 are in independent form. The Office's Note: 6. The Office has cited particular paragraphs / columns and line numbers in the reference(s) applied to the claims above for the convenience of the Applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim(s), other passages and figures may apply as well. It is respectfully requested from the Applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the cited passages as taught by the prior art or relied upon by the Examiner. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21 AIA 7. Claim 1-20 rejected under 35 U.S.C. 103(a) as being unpatentable over Kataria et al. (US 20220027519) and further in view of Chbani US 20240176864 (hereinafter Chbani ) . Claim 1 is rejected, Kataria teaches an apparatus comprising: (Kataria, abstract and summary) first memory configured to store a debug authentication status ( Kataria , US 20220027519, fig. 1 and para [0032], validation circuit 122 is further configured to receive certificate 135 that was generated by server computer system 115, and to decode debug permissions 140 using the identification value… Device 105 has access to, or may generate, the same keyword based on this identification value. Para [0033-0034], Using the decoded debug permissions 140, validation circuit 122 is further configured to enable one or more of the debug features on debug circuit 120. Certificate 135 may, for example, indicate that the user is allowed to access debug features associated with a graphics processor included in device 105. Debug system 110 is then allowed access to one or more of the debug features of device 105 based on debug permissions 140 in certificate 135. Debug system 110, for example, may send, to validation circuit 122, requests for setting breakpoints and tracing code execution by the graphics processor. Based on the permissions in the validated certificate 135, validation circuit 122 forwards these requests on to debug circuit 120 to be performed. Fig. 9, memory circuit – 950 and para [0111-0112].); a processor ( Kataria , Fig. 9, processor complex – 910 and para [0108-0109])); second memory storing instructions that, when executed, cause the processor to ( Kataria , Fig. 9, memory circuit – 950 and para [0111-0112]. fig. 9, processor complex – 910 and para [0108-0109]): check a debug authentication status in the first memory (Kataria, US 2022027519, para [0045], Validation circuit 122, using cryptographic circuit 224, validates any additional encrypted/hashed values that may be used to confirm that certificate 135 is a valid certificate issued by server computer system 115.); perform an authentication procedure in response to determining that the debug authentication status stored in the first memory does not indicate that debug is allowed ( Kataria , para [0046], Received certificate 135 further includes encoded debug permissions. In response to a successful validation of certificate 135, validation circuit 122 is configured to, as shown, extract and decode the encoded debug permissions. In some embodiments, the debug permissions are encoded using the previously sent identification value, in whole or in part. In such embodiments, validation circuit 122 decodes the debug permissions using the identification value.); and Kataria does not explicitly teach set , by the processor, the debug authentication status in the first memory to indicate that debug is allowed in response to a successful performance of the authentication procedure by the processor However, Chbani teaches set , by the processor, the debug authentication status in the first memory to indicate that debug is allowed in response to a successful performance of the authentication procedure by the processor ( Chbani , US 20240176864, para [0011], the first processing unit is configured: to read from the host register an authentication request from the external device; to authenticate the external device; and to set at least one of the one or more processing unit access ports to an open state, thereby causing the indication of the state of the one or more processing unit access ports to be updated in the status register. Para [0012], According to one embodiment, the first processing unit is configured to authenticate the external device by: storing an authentication challenge or password request to the device register; reading an authentication certificate or password from the host register; and verifying the certificate or password. Para [0047-0049], the authentication interface circuit. Para [0050], FIG. 3, the status register 302 stores, for each access port, a first bit APOP to AP15P indicating whether the corresponding access port AP0 to AP15 is present, and a second bit AP0S to AP15S indicating the current status of the corresponding access port AP0 to AP15, in other words whether it is open or closed. Fig. 4 and para [0069-0070], In an operation 407 (MASTER CPU VERIFIES CERTIFICATE+UNLOCKS APs), the master processing unit CPU1 is for example configured to verify the certificate, and if validated, to unlock, and thus set to open status, one or more of the processing unit access ports AP1 to APn based on the credentials indicated by the certificate. In other words, debug is opened for all or for selected processing unit access ports AP1 to APN. For example, this is done by writing, by the master processing unit CPU1, to the one or more system control registers 201 of FIG. 2. For example, each processing device access port has its own dedicated control bits in the system control registers 201.). It would have obvious to one having ordinary skill in the art before the effecting filing date of the claimed invention to combine the teachings of cited references. Thus, one of ordinary skill in the art before the effecting filing date of the claimed invention would have been motivated to incorporate Chabanin into Kataria to debug an electornic device. An authentication interface circuit authenticates an external device, and an access port is coupled between the debug and interface circuits. The interface circuit has registers including a status register that is readable by the external device via the ports, where the status register stores an indication of an open or closed state of each of the access as suggested by Chbani (See abstract and summary). Claim 2 is rejected for the reasons set forth hereinabove for claim 1, Kataria and Chbani teach the apparatus of claim 1, wherein the instructions, when executed, cause the processor to allow a debug session in response to a successful performance of the authentication procedure ( Kataria , para [0046], Validation circuit 122 is further configured to, using the decoded debug permissions, initiate an active debug session. During an active debug session, validation circuit 122 enables one or more of debug features 230 for access by debug system 110. In response to the enabling, debug system 110 may send debug requests to debug circuit 120 via validation circuit 122. The enabled ones of debug features 230 allow access to one or more of functional circuits 250.). Claim 3 is rejected for the reasons set forth hereinabove for claim 1, Kataria and Chbani teach the apparatus of claim 1, wherein the instructions, when executed, cause the processor to clear one or more bits indicating the debug authentication status in the first memory in response to a failed performance of the authentication procedure ( Kataria , para [0045], A failure to validate any one these values may result in validation circuit 122 denying certificate 135 and refusing access to debug features 230. Chbani , para [0011], the first processing unit is configured: to read from the host register an authentication request from the external device; to authenticate the external device; and to set at least one of the one or more processing unit access ports to an open state, thereby causing the indication of the state of the one or more processing unit access ports to be updated in the status register. Para [0012], According to one embodiment, the first processing unit is configured to authenticate the external device by: storing an authentication challenge or password request to the device register; reading an authentication certificate or password from the host register; and verifying the certificate or password. Para [0047-0049], the authentication interface circuit. Para [0050], FIG. 3, the status register 302 stores, for each access port, a first bit APOP to AP15P indicating whether the corresponding access port AP0 to AP15 is present, and a second bit AP0S to AP15S indicating the current status of the corresponding access port AP0 to AP15, in other words whether it is open or closed. Para [0051], Upon power-up of the electronic device 100, the contents of the status register 302 is for example loaded, by a state machine (not illustrated), from secure storage in a non-volatile memory, such as the memory 104 of FIG. 1. For example, by default, upon power-up, the access ports AP1 to APn are all set to be closed, whereas the access port AP0 is set to be open. The open or closed status to each of the access ports AP0 to. Fig. 4 and para [0069-0070], In an operation 407 (MASTER CPU VERIFIES CERTIFICATE+UNLOCKS APs), the master processing unit CPU1 is for example configured to verify the certificate, and if validated, to unlock, and thus set to open status, one or more of the processing unit access ports AP1 to APn based on the credentials indicated by the certificate. In other words, debug is opened for all or for selected processing unit access ports AP1 to APN. For example, this is done by writing, by the master processing unit CPU1, to the one or more system control registers 201 of FIG. 2. For example, each processing device access port has its own dedicated control bits in the system control registers 201). Claim 4 is rejected for the reasons set forth hereinabove for claim 1, Kataria and Chbani teach the apparatus of claim 1, wherein the instructions, when executed, cause the processor to disallow a debug session in response to a failed performance of the authentication procedure ( Kataria , para [0045], A failure to validate any one these values may result in validation circuit 122 denying certificate 135 and refusing access to debug features 230. nfiguration software or first debug instructions) can run first and may be designed to obtain the setting to be made from a source outside the system on a chip 300 as data generated by means of an authenticated method and to authenticate said setting. The privileged user can provide the setting to be made, for example. Fig. 5 and para [0076], The registers in which the trace configuration can be set are shown in FIG. 5 by way of illustration with fields, bits, types, descriptions, and so on. For the sake of clarity, this information is not repeated here. In one example, the register is configured to store read and write permissions for respective address ranges relating to respective virtual machines, and access to memory associated with various virtual machines is controlled by selectively storing read and/or write permissions to various address ranges in the register. For example, read and write permission for address ranges associated with VM2 (the VM being debugged) while read and write permission may not be stored for address ranges relating to VM1 (the VM to which access is to be blocked). Claim 5 is rejected for the reasons set forth hereinabove for claim1, Kataria and Chbani teach the apparatus of claim 1, wherein the instructions, when executed, cause the processor to enable a debug session in response to determining that the debug authentication status stored in the first memory indicates that debug is allowed ( Kataria , para [0046], Validation circuit 122 is further configured to, using the decoded debug permissions, initiate an active debug session. During an active debug session, validation circuit 122 enables one or more of debug features 230 for access by debug system 110. In response to the enabling, debug system 110 may send debug requests to debug circuit 120 via validation circuit 122. The enabled ones of debug features 230 allow access to one or more of functional circuits 250. Chbani , para [0011], the first processing unit is configured: to read from the host register an authentication request from the external device; to authenticate the external device; and to set at least one of the one or more processing unit access ports to an open state, thereby causing the indication of the state of the one or more processing unit access ports to be updated in the status register. Para [0012], According to one embodiment, the first processing unit is configured to authenticate the external device by: storing an authentication challenge or password request to the device register; reading an authentication certificate or password from the host register; and verifying the certificate or password. Para [0047-0049], the authentication interface circuit. Para [0050], FIG. 3, the status register 302 stores, for each access port, a first bit APOP to AP15P indicating whether the corresponding access port AP0 to AP15 is present, and a second bit AP0S to AP15S indicating the current status of the corresponding access port AP0 to AP15, in other words whether it is open or closed. Para [0051], Upon power-up of the electronic device 100, the contents of the status register 302 is for example loaded, by a state machine (not illustrated), from secure storage in a non-volatile memory, such as the memory 104 of FIG. 1. For example, by default, upon power-up, the access ports AP1 to APn are all set to be closed, whereas the access port AP0 is set to be open. The open or closed status to each of the access ports AP0 to. Fig. 4 and para [0069- 0070], In an operation 407 (MASTER CPU VERIFIES CERTIFICATE+UNLOCKS APs), the master processing unit CPU1 is for example configured to verify the certificate, and if validated, to unlock, and thus set to open status, one or more of the processing unit access ports AP1 to APn based on the credentials indicated by the certificate. In other words, debug is opened for all or for selected processing unit access ports AP1 to APN. For example, this is done by writing, by the master processing unit CPU1, to the one or more system control registers 201 of FIG. 2. For example, each processing device access port has its own dedicated control bits in the system control registers 201). Claim 6 is rejected for the reasons set forth hereinabove for claim 1, Kataria and Chbani teach the apparatus of claim 1, wherein the instructions, when executed, cause the processor to: determine that a power-on reset occurred; and perform the authentication procedure without checking the debug authentication status in response to determining that the power-on reset occurred ( Kataria , para [0044], If validation circuit 122 does not have a record of a request for debug access (e.g., has issued a liveness token that is still valid), then validation circuit 122 denies the received certificate 135 and may refuse any further attempt by debug system 110 to access debug features 230. This refusal may last until device 105 performs a power-on reset or other similar type of reset. Chbani , para [0011], the first processing unit is configured: to read from the host register an authentication request from the external device; to authenticate the external device; and to set at least one of the one or more processing unit access ports to an open state, thereby causing the indication of the state of the one or more processing unit access ports to be updated in the status register. Para [0012], According to one embodiment, the first processing unit is configured to authenticate the external device by: storing an authentication challenge or password request to the device register; reading an authentication certificate or password from the host register; and verifying the certificate or password. Para [0047-0049], the authentication interface circuit. Para [0050], FIG. 3, the status register 302 stores, for each access port, a first bit APOP to AP15P indicating whether the corresponding access port AP0 to AP15 is present, and a second bit AP0S to AP15S indicating the current status of the corresponding access port AP0 to AP15, in other words whether it is open or closed. Para [0051], Upon power-up of the electronic device 100, the contents of the status register 302 is for example loaded, by a state machine (not illustrated), from secure storage in a non-volatile memory, such as the memory 104 of FIG. 1. For example, by default, upon power-up, the access ports AP1 to APn are all set to be closed, whereas the access port AP0 is set to be open. The open or closed status to each of the access ports AP0 to. Fig. 4 and para [0069-0070], In an operation 407 (MASTER CPU VERIFIES CERTIFICATE+UNLOCKS APs), the master processing unit CPU1 is for example configured to verify the certificate, and if validated, to unlock, and thus set to open status, one or more of the processing unit access ports AP1 to APn based on the credentials indicated by the certificate. In other words, debug is opened for all or for selected processing unit access ports AP1 to APN. For example, this is done by writing, by the master processing unit CPU1, to the one or more system control registers 201 of FIG. 2. For example, each processing device access port has its own dedicated control bits in the system control registers 201). Claim 7 is rejected for the reasons set forth hereinabove for claim1, Kataria and Chbani teach the apparatus of claim 1, wherein the instructions, when executed, cause the processor to: the first memory configured to store the debug authentication status so that the debug authentication status is preserved across a non-power on reset ( Chbani , para [0011], the first processing unit is configured: to read from the host register an authentication request from the external device; to authenticate the external device; and to set at least one of the one or more processing unit access ports to an open state, thereby causing the indication of the state of the one or more processing unit access ports to be updated in the status register. Para [0012], According to one embodiment, the first processing unit is configured to authenticate the external device by: storing an authentication challenge or password request to the device register; reading an authentication certificate or password from the host register; and verifying the certificate or password. Para [0047-0049], the authentication interface circuit. Para [0050], FIG. 3, the status register 302 stores, for each access port, a first bit APOP to AP15P indicating whether the corresponding access port AP0 to AP15 is present, and a second bit AP0S to AP15S indicating the current status of the corresponding access port AP0 to AP15, in other words whether it is open or closed. Para [0051], Upon power-up of the electronic device 100, the contents of the status register 302 is for example loaded, by a state machine (not illustrated), from secure storage in a non-volatile memory, such as the memory 104 of FIG. 1. For example, by default, upon power-up, the access ports AP1 to APn are all set to be closed, whereas the access port AP0 is set to be open. The open or closed status to each of the access ports AP0 to. Fig. 4 and para [0069-0070], In an operation 407 (MASTER CPU VERIFIES CERTIFICATE+UNLOCKS APs), the master processing unit CPU1 is for example configured to verify the certificate, and if validated, to unlock, and thus set to open status, one or more of the processing unit access ports AP1 to APn based on the credentials indicated by the certificate. In other words, debug is opened for all or for selected processing unit access ports AP1 to APN. For example, this is done by writing, by the master processing unit CPU1, to the one or more system control registers 201 of FIG. 2. For example, each processing device access port has its own dedicated control bits in the system control registers 201.) determine that a non-power-on reset occurred; and check the debug authentication status in the first memory in response to determining that the non-power-on reset occurred ( Kataria , para [0040], validation circuit 122 may be enabled in response to a particular combination of voltage levels on particular physical connections of debug interface 226 during a power-on reset or other particular types of resets. Once enabled, debug interface is capable of receiving messages from debug system 110. Para [0048], When the particular amount of time has elapsed, validation circuit 122 may send a notification to debug system 110 indicating an imminent end to the current debug session, and may provide an option to extend the debug session by requesting an extension to certificate 135 or by requesting a new certificate. In some embodiments, validation circuit 122 may provide a new liveness token to debug system 110 if requested before ending the current active debug session. Debug system 110 may then use the new liveness token to request a new certificate form server computer system 115, and subsequently use the new certificate to keep the current debug session active for an extended amount of time. Chbani , para [0011], the first processing unit is configured: to read from the host register an authentication request from the external device; to authenticate the external device; and to set at least one of the one or more processing unit access ports to an open state, thereby causing the indication of the state of the one or more processing unit access ports to be updated in the status register. Para [0012], According to one embodiment, the first processing unit is configured to authenticate the external device by: storing an authentication challenge or password request to the device register; reading an authentication certificate or password from the host register; and verifying the certificate or password. Para [0047-0049], the authentication interface circuit. Para [0050], FIG. 3, the status register 302 stores, for each access port, a first bit APOP to AP15P indicating whether the corresponding access port AP0 to AP15 is present, and a second bit AP0S to AP15S indicating the current status of the corresponding access port AP0 to AP15, in other words whether it is open or closed. Para [0051], Upon power-up of the electronic device 100, the contents of the status register 302 is for example loaded, by a state machine (not illustrated), from secure storage in a non-volatile memory, such as the memory 104 of FIG. 1. For example, by default, upon power-up, the access ports AP1 to APn are all set to be closed, whereas the access port AP0 is set to be open. The open or closed status to each of the access ports AP0 to. Fig. 4 and para [0069-0070], In an operation 407 (MASTER CPU VERIFIES CERTIFICATE+UNLOCKS APs), the master processing unit CPU1 is for example configured to verify the certificate, and if validated, to unlock, and thus set to open status, one or more of the processing unit access ports AP1 to APn based on the credentials indicated by the certificate. In other words, debug is opened for all or for selected processing unit access ports AP1 to APN. For example, this is done by writing, by the master processing unit CPU1, to the one or more system control registers 201 of FIG. 2. For example, each processing device access port has its own dedicated control bits in the system control registers 201). Claim 8 is rejected for the reasons set forth hereinabove for claim 1, Kataria and Chbani teach the apparatus of claim 1, wherein the instructions, when executed, cause the processor to perform the authentication procedure based on a media access control (MAC) address associated with the apparatus ( Kataria , para [0069], These Ethernet packets may include internet protocol (IP) addresses and/or media access control (MAC) addresses. Fig. 5 and para [0075], Request 133, as shown, also includes current device configuration 504. Current device configuration 504 includes information regarding a current status of device 105, including, for example, status of one or more debug features that are available and/or are enabled. Liveness token 506, as described above, is a value that device 105 uses to determine a validity of a received certificate 135. Liveness token 506 is generated by device 105 and sent to debug system 110 for inclusion in request 133. Liveness token 506 may include a one-time-use nonce value that changes each time a debug system 110 requests a new debug session.). Claim 9 is rejected for the reasons set forth hereinabove for claim 8, Kataria and Chbani teach the apparatus of claim 8, wherein the instructions cause the processor to perform the authentication procedure based on the MAC address and further based on a value generated by a random number generator ( Kataria , para [0069], These Ethernet packets may include internet protocol (IP) addresses and/or media access control (MAC) addresses. Fig. 5 and para [0075], Request 133, as shown, also includes current device configuration 504. Current device configuration 504 includes information regarding a current status of device 105, including, for example, status of one or more debug features that are available and/or are enabled. Liveness token 506, as described above, is a value that device 105 uses to determine a validity of a received certificate 135. Liveness token 506 is generated by device 105 and sent to debug system 110 for inclusion in request 133. Liveness token 506 may include a one-time-use nonce value that changes each time a debug system 110 requests a new debug session.). Claim 10 is rejected, Kataria teaches a non-transitory computer readable medium comprising instructions that, when executed, cause a machine to at least (Kataria, abstract and summary): check a debug authentication status in a memory (Kataria, US 20220027519, para [0045], Validation circuit 122, using cryptographic circuit 224, validates any additional encrypted/hashed values that may be used to confirm that certificate 135 is a valid certificate issued by server computer system 115.); perform an authentication procedure in response to determining that the debug authentication status stored in the memory does not indicate that debug is allowed ( Kataria , para [0046], Received certificate 135 further includes encoded debug permissions. In response to a successful validation of certificate 135, validation circuit 122 is configured to, as shown, extract and decode the encoded debug permissions. In some embodiments, the debug permissions are encoded using the previously sent identification value, in whole or in part. In such embodiments, validation circuit 122 decodes the debug permissions using the identification value.); and Kataria does not explicitly teach set , by the machine, the debug authentication status in the first memory to indicate that debug is allowed in response to a successful performance of the authentication procedure by the machine However, Chbani teaches set , by the machine, the debug authentication status in the first memory to indicate that debug is allowed in response to a successful performance of the authentication procedure by the machine ( Chbani , US 20240176864, para [0011], the first processing unit is configured: to read from the host register an authentication request from the external device; to authenticate the external device; and to set at least one of the one or more processing unit access ports to an open state, thereby causing the indication of the state of the one or more processing unit access ports to be updated in the status register. Para [0012], According to one embodiment, the first processing unit is configured to authenticate the external device by: storing an authentication challenge or password request to the device register; reading an authentication certificate or password from the host register; and verifying the certificate or password. Para [0047-0049], the authentication interface circuit. Para [0050], FIG. 3, the status register 302 stores, for each access port, a first bit APOP to AP15P indicating whether the corresponding access port AP0 to AP15 is present, and a second bit AP0S to AP15S indicating the current status of the corresponding access port AP0 to AP15, in other words whether it is open or closed. Fig. 4 and para [0069-0070], In an operation 407 (MASTER CPU VERIFIES CERTIFICATE+UNLOCKS APs), the master processing unit CPU1 is for example configured to verify the certificate, and if validated, to unlock, and thus set to open status, one or more of the processing unit access ports AP1 to APn based on the credentials indicated by the certificate. In other words, debug is opened for all or for selected processing unit access ports AP1 to APN. For example, this is done by writing, by the master processing unit CPU1, to the one or more system control registers 201 of FIG. 2. For example, each processing device access port has its own dedicated control bits in the system control registers 201.). It would have obvious to one having ordinary skill in the art before the effecting filing date of the claimed invention to combine the teachings of cited references. Thus, one of ordinary skill in the art before the effecting filing date of the claimed invention would have been motivated to incorporate Chabanin into Kataria to debug an electornic device. An authentication interface circuit authenticates an external device, and an access port is coupled between the debug and interface circuits. The interface circuit has registers including a status register that is readable by the external device via the ports, where the status register stores an indication of an open or closed state of each of the access as suggested by Chbani (See abstract and summary). Claim 11 is rejected for the reasons set forth hereinabove for claim 10, Kataria and Chbani teach the non-transitory computer readable medium of claim 10, wherein the indication includes a bit indicating whether persistent debug is enabled( Kataria , Para [0048], When the particular amount of time has elapsed, validation circuit 122 may send a notification to debug system 110 indicating an imminent end to the current debug session, and may provide an option to extend the debug session by requesting an extension to certificate 135 or by requesting a new certificate. In some embodiments, validation circuit 122 may provide a new liveness token to debug system 110 if requested before ending the current active debug session. Debug system 110 may then use the new liveness token to request a new certificate form server computer system 115, and subsequently use the new certificate to keep the current debug session active for an extended amount of time. Chbani , para [0011], the first processing unit is configured: to read from the host register an authentication request from the external device; to authenticate the external device; and to set at least one of the one or more processing unit access ports to an open state, thereby causing the indication of the state of the one or more processing unit access ports to be updated in the status register. Para [0012], According to one embodiment, the first processing unit is configured to authenticate the external device by: storing an authentication challenge or password request to the device register; reading an authentication certificate or password from the host register; and verifying the certificate or password. Para [0047-0049], the authentication interface circuit. Para [0050], FIG. 3, the status register 302 stores, for each access port, a first bit APOP to AP15P indicating whether the corresponding access port AP0 to AP15 is present, and a second bit AP0S to AP15S indicating the current status of the corresponding access port AP0 to AP15, in other words whether it is open or closed. Para [0051], Upon power-up of the electronic device 100, the contents of the status register 302 is for example loaded, by a state machine (not illustrated), from secure storage in a non-volatile memory, such as the memory 104 of FIG. 1. For example, by default, upon power-up, the access ports AP1 to APn are all set to be closed, whereas the access port AP0 is set to be open. The open or closed status to each of the access ports AP0 to. Fig. 4 and para [0069-0070], In an operation 407 (MASTER CPU VERIFIES CERTIFICATE+UNLOCKS APs), the master processing unit CPU1 is for example configured to verify the certificate, and if validated, to unlock, and thus set to open status, one or more of the processing unit access ports AP1 to APn based on the credentials indicated by the certificate. In other words, debug is opened for all or for selected processing unit access ports AP1 to APN. For example, this is done by writing, by the master processing unit CPU1, to the one or more system control registers 201 of FIG. 2. For example, each processing device access port has its own dedicated control bits in the system control registers 201). Claim 12 is rejected for the reasons set forth hereinabove for claim 10, Kataria and Chbani teach the non-transitory computer readable medium of claim 10, wherein the instructions are part of a boot code of the machine and the memory further stores an application for execution by the machine (Kataria, para [0043-0044], Validation circuit 122 may also be configured to send information indicative of available features of the debug circuit, as well as currently enabled features of debug circuit 120. For example, device 105 may be booted into a particular debug mode in which a portion of debug features 230 are enabled, and/or a different portion are not available. As used herein, an “enabled debug feature” refers to a supported debug feature that may be accessed by a currently connected debug system that has general permission to access debug circuit 120. An “available debug feature” refers to a supported debug feature that may be enabled if the currently connected debug system has explicit permission, e.g., from certificate 135, to access that supported debug feature. Chbani , para [0011], the first processing unit is configured: to read from the host register an authentication request from the external device; to authenticate the external device; and to set at least one of the one or more processing unit access ports to an open state, thereby causing the indication of the state of the one or more processing unit access ports to be updated in the status register. Para [0012], According to one embodiment, the first processing unit is configured to authenticate the external device by: storing an authentication challenge or password request to the device register; reading an authentication certificate or password from the host register; and verifying the certificate or password. Para [0047-0049], the authentication interface circuit. Para [0050], FIG. 3, the status register 302 stores, for each access port, a first bit APOP to AP15P indicating whether the corresponding access port AP0 to AP15 is present, and a second bit AP0S to AP15S indicating the current status of the corresponding access port AP0 to AP15, in other words whether it is open or closed. Para [0051], Upon power-up of the electronic device 100, the contents of the status register 302 is for example loaded, by a state machine (not illustrated), from secure storage in a non-volatile memory, such as the memory 104 of FIG. 1. For example, by default, upon power-up, the access ports AP1 to APn are all set to be closed, whereas the access port AP0 is set to be open. The open or closed status to each of the access ports AP0 to. Fig. 4 and para [0069-0070], In an operation 407 (MASTER CPU VERIFIES CERTIFICATE+UNLOCKS APs), the master processing unit CPU1 is for example configured to verify the certificate, and if validated, to unlock, and thus set to open status, one or more of the processing unit access ports AP1 to APn based on the credentials indicated by the certificate. In other words, debug is opened for all or for selected processing unit access ports AP1 to APN. For example, this is done by writing, by the master processing unit CPU1, to the one or more system control registers 201 of FIG. 2. For example, each processing device access port has its own dedicated control bits in the system control registers 201). Claim 13 is rejected for the reasons set forth hereinabove for claim 10, Kataria and Chbani teach the non-transitory computer readable medium of claim 10, wherein the instructions, when executed, cause the machine to: determine that a power-on reset occurred; and perform the authentication procedure without checking the debug authentication status in response to determining that the power-on reset occurred ( Kataria , para [0044], If validation circuit 122 does not have a record of a request for debug access (e.g., has issued a liveness token that is still valid), then validation circuit 122 denies the received certificate 135 and may refuse any further attempt by debug system 110 to access debug features 230. This refusal may last until device 105 performs a power-on reset or other similar type of reset. Chbani , para [0011], the first processing unit is configured: to read from the host register an authentication request from the external device; to authenticate the external device; and to set at least one of the one or more processing unit access ports to an open state, thereby causing the indication of the state of the one or more processing unit access ports to be updated in the status register. Para [0012], According to one embodiment, the first processing unit is configured to authenticate the external device by: storing an authentication challenge or password request to the device register; reading an authentication certificate or password from the host register; and verifying the certificate or password. Para [0047-0049], the authentication interface circuit. Para [0050], FIG. 3, the status register 302 stores, for each access port, a first bit APOP to AP15P indicating whether the corresponding access port AP0 to AP15 is present, and a second bit AP0S to AP15S indicating the current status of the corresponding access port AP0 to AP15, in other words whether it is open or closed. Para [0051], Upon power-up of the electronic device 100, the contents of the status register 302 is for example loaded, by a state machine (not illustrated), from secure storage in a non-volatile memory, such as the memory 104 of FIG. 1. For example, by default, upon power-up, the access ports AP1 to APn are all set to be closed, whereas the access port AP0 is set to be open. The open or closed status to each of the access ports AP0 to. Fig. 4 and para [0069-0070], In an operation 407 (MASTER CPU VERIFIES CERTIFICATE+UNLOCKS APs), the master processing unit CPU1 is for example configured to verify the certificate, and if validated, to unlock, and thus set to open status, one or more of the processing unit access ports AP1 to APn based on the credentials indicated by the certificate. In other words, debug is opened for all or for selected processing unit access ports AP1 to APN. For example, this is done by writing, by the master processing unit CPU1, to the one or more system control registers 201 of FIG. 2. For example, each processing device access port has its own dedicated control bits in the system control registers 201). Claim 14 is rejected for the reasons set forth hereinabove for claim 10, Kataria and Chbani teach the non-transitory computer readable medium of claim 10, wherein the instructions, when executed, cause the machine to: the memory configured to store the debug authentication status so that the debug authentication status is preserved across a non-power on reset ( Chbani , , para [0011], the first processing unit is configured: to read from the host register an authentication request from the external device; to authenticate the external device; and to set at least one of the one or more processing unit access ports to an open state, thereby causing the indication of the state of the one or more processing unit access ports to be updated in the status register. Para [0012], According to one embodiment, the first processing unit is configured to authenticate the external device by: storing an authentication challenge or password request to the device register; reading an authentication certificate or password from the host register; and verifying the certificate or password. Para [0047-0049], the authentication interface circuit. Para [0050], FIG. 3, the status register 302 stores, for each access port, a first bit APOP to AP15P indicating whether the corresponding access port AP0 to AP15 is present, and a second bit AP0S to AP15S indicating the current status of the corresponding access port AP0 to AP15, in other words whether it is open or closed. Para [0051], Upon power-up of the electronic device 100, the contents of the status register 302 is for example loaded, by a state machine (not illustrated), from secure storage in a non-volatile memory, such as the memory 104 of FIG. 1. For example, by default, upon power-up, the access ports AP1 to APn are all set to be closed, whereas the access port AP0 is set to be open. The open or closed status to each of the access ports AP0 to. Fig. 4 and para [0069-0070], In an operation 407 (MASTER CPU VERIFIES CERTIFICATE+UNLOCKS APs), the master processing unit CPU1 is for example configured to verify the certificate, and if validated, to unlock, and thus set to open status, one or more of the processing unit access ports AP1 to APn based on the credentials indicated by the certificate. In other words, debug is opened for all or for selected processing unit access ports AP1 to APN. For example, this is done by writing, by the master processing unit CPU1, to the one or more system control registers 201 of FIG. 2. For example, each processing device access port has its own dedicated control bits in the system control registers 201.); determine that a non-power-on reset occurred; and check the debug authentication status in the memory in response to determining that the non-power-on reset occurred ( Kataria , para [0040], validation circuit 122 may be enabled in response to a particular combination of voltage levels on particular physical connections of debug interface 226 during a power-on reset or other particular types of resets. Once enabled, debug interface is capable of receiving messages from debug system 110. Para [0048], When the particular amount of time has elapsed, validation circuit 122 may send a notification to debug system 110 indicating an imminent end to the current debug session, and may provide an option to extend the debug session by requesting an extension to certificate 135 or by requesting a new certificate. In some embodiments, validation circuit 122 may provide a new liveness token to debug system 110 if requested before ending the current active debug session. Debug system 110 may then use the new liveness token to request a new certificate form server computer system 115, and subsequently use the new certificate to keep the current debug session active for an extended amount of time. Chbani , para [0011], the first processing unit is configured: to read from the host register an authentication request from the external device; to authenticate the external device; and to set at least one of the one or more processing unit access ports to an open state, thereby causing the indication of the state of the one or more processing unit access ports to be updated in the status register. Para [0012], According to one embodiment, the first processing unit is configured to authenticate the external device by: storing an authentication challenge or password request to the device register; reading an authentication certificate or password from the host register; and verifying the certificate or password. Para [0047-0049], the authentication interface circuit. Para [0050], FIG. 3, the status register 302 stores, for each access port, a first bit APOP to AP15P indicating whether the corresponding access port AP0 to AP15 is present, and a second bit AP0S to AP15S indicating the current status of the corresponding access port AP0 to AP15, in other words whether it is open or closed. Para [0051], Upon power-up of the electronic device 100, the contents of the status register 302 is for example loaded, by a state machine (not illustrated), from secure storage in a non-volatile memory, such as the memory 104 of FIG. 1. For example, by default, upon power-up, the access ports AP1 to APn are all set to be closed, whereas the access port AP0 is set to be open. The open or closed status to each of the access ports AP0 to. Fig. 4 and para [0069-0070], In an operation 407 (MASTER CPU VERIFIES CERTIFICATE+UNLOCKS APs), the master processing unit CPU1 is for example configured to verify the certificate, and if validated, to unlock, and thus set to open status, one or more of the processing unit access ports AP1 to APn based on the credentials indicated by the certificate. In other words, debug is opened for all or for selected processing unit access ports AP1 to APN. For example, this is done by writing, by the master processing unit CPU1, to the one or more system control registers 201 of FIG. 2. For example, each processing device access port has its own dedicated control bits in the system control registers 201). Claim 15 is rejected for the reasons set forth hereinabove for claim 10, Kataria and Chbani teach the non-transitory computer readable medium of claim 10, wherein the instructions, when executed, cause the machine to perform the authentication procedure based on a media access control (MAC) address associated with the machine ( Kataria , para [0069], These Ethernet packets may include internet protocol (IP) addresses and/or media access control (MAC) addresses. Fig. 5 and para [0075], Request 133, as shown, also includes current device configuration 504. Current device configuration 504 includes information regarding a current status of device 105, including, for example, status of one or more debug features that are available and/or are enabled. Liveness token 506, as described above, is a value that device 105 uses to determine a validity of a received certificate 135. Liveness token 506 is generated by device 105 and sent to debug system 110 for inclusion in request 133. Liveness token 506 may include a one-time-use nonce value that changes each time a debug system 110 requests a new debug session.). Claim 16 is rejected, Kataria teaches a method comprising (Kataria, abstract and summary): checking, via instructions executed by a device, a debug authentication indication of the device (Kataria, US 20220027519, para [0045], Validation circuit 122, using cryptographic circuit 224, validates any additional encrypted/hashed values that may be used to confirm that certificate 135 is a valid certificate issued by server computer system 115.); performing an authentication procedure in response to determining that the debug authentication indication does not indicate that debug is allowed ( Kataria , para [0046], Received certificate 135 further includes encoded debug permissions. In response to a successful validation of certificate 135, validation circuit 122 is configured to, as shown, extract and decode the encoded debug permissions. In some embodiments, the debug permissions are encoded using the previously sent identification value, in whole or in part. In such embodiments, validation circuit 122 decodes the debug permissions using the identification value.); and Kataria does not explicitly teach setting , by the device, the debug authentication status in the first memory to indicate that debug is allowed in response to a successful performance of the authentication procedure by the device However, Chbani teaches setting , by the device, the debug authentication status in the first memory to indicate that debug is allowed in response to a successful performance of the authentication procedure by the device ( Chbani , US 20240176864, para [0011], the first processing unit is configured: to read from the host register an authentication request from the external device; to authenticate the external device; and to set at least one of the one or more processing unit access ports to an open state, thereby causing the indication of the state of the one or more processing unit access ports to be updated in the status register. Para [0012], According to one embodiment, the first processing unit is configured to authenticate the external device by: storing an authentication challenge or password request to the device register; reading an authentication certificate or password from the host register; and verifying the certificate or password. Para [0047-0049], the authentication interface circuit. Para [0050], FIG. 3, the status register 302 stores, for each access port, a first bit APOP to AP15P indicating whether the corresponding access port AP0 to AP15 is present, and a second bit AP0S to AP15S indicating the current status of the corresponding access port AP0 to AP15, in other words whether it is open or closed. Fig. 4 and para [0069-0070], In an operation 407 (MASTER CPU VERIFIES CERTIFICATE+UNLOCKS APs), the master processing unit CPU1 is for example configured to verify the certificate, and if validated, to unlock, and thus set to open status, one or more of the processing unit access ports AP1 to APn based on the credentials indicated by the certificate. In other words, debug is opened for all or for selected processing unit access ports AP1 to APN. For example, this is done by writing, by the master processing unit CPU1, to the one or more system control registers 201 of FIG. 2. For example, each processing device access port has its own dedicated control bits in the system control registers 201.). It would have obvious to one having ordinary skill in the art before the effecting filing date of the claimed invention to combine the teachings of cited references. Thus, one of ordinary skill in the art before the effecting filing date of the claimed invention would have been motivated to incorporate Chabanin into Kataria to debug an electornic device. An authentication interface circuit authenticates an external device, and an access port is coupled between the debug and interface circuits. The interface circuit has registers including a status register that is readable by the external device via the ports, where the status register stores an indication of an open or closed state of each of the access as suggested by Chbani (See abstract and summary). Claim 17 is rejected for the reasons set forth hereinabove for claim 16, Kataria and Chbani teach the method as defined in claim 16, wherein checking the debug authentication indication includes determining that an indication is stored at the device that indicates that a persistent debug connection is disabled ( Kataria , Para [0048], When the particular amount of time has elapsed, validation circuit 122 may send a notification to debug system 110 indicating an imminent end to the current debug session, and may provide an option to extend the debug session by requesting an extension to certificate 135 or by requesting a new certificate. In some embodiments, validation circuit 122 may provide a new liveness token to debug system 110 if requested before ending the current active debug session. Debug system 110 may then use the new liveness token to request a new certificate form server computer system 115, and subsequently use the new certificate to keep the current debug session active for an extended amount of time. Chbani , para [0011], the first processing unit is configured: to read from the host register an authentication request from the external device; to authenticate the external device; and to set at least one of the one or more processing unit access ports to an open state, thereby causing the indication of the state of the one or more processing unit access ports to be updated in the status register. Para [0012], According to one embodiment, the first processing unit is configured to authenticate the external device by: storing an authentication challenge or password request to the device register; reading an authentication certificate or password from the host register; and verifying the certificate or password. Para [0047-0049], the authentication interface circuit. Para [0050], FIG. 3, the status register 302 stores, for each access port, a first bit APOP to AP15P indicating whether the corresponding access port AP0 to AP15 is present, and a second bit AP0S to AP15S indicating the current status of the corresponding access port AP0 to AP15, in other words whether it is open or closed. Para [0051], Upon power-up of the electronic device 100, the contents of the status register 302 is for example loaded, by a state machine (not illustrated), from secure storage in a non-volatile memory, such as the memory 104 of FIG. 1. For example, by default, upon power-up, the access ports AP1 to APn are all set to be closed, whereas the access port AP0 is set to be open. The open or closed status to each of the access ports AP0 to. Fig. 4 and para [0069-0070], In an operation 407 (MASTER CPU VERIFIES CERTIFICATE+UNLOCKS APs), the master processing unit CPU1 is for example configured to verify the certificate, and if validated, to unlock, and thus set to open status, one or more of the processing unit access ports AP1 to APn based on the credentials indicated by the certificate. In other words, debug is opened for all or for selected processing unit access ports AP1 to APN. For example, this is done by writing, by the master processing unit CPU1, to the one or more system control registers 201 of FIG. 2. For example, each processing device access port has its own dedicated control bits in the system control registers 201). Claim 18 is rejected for the reasons set forth hereinabove for claim 16, Kataria and Chbani teach the method of claim 16, further comprising allowing a debug session in response to a successful performance of the authentication procedure ( Kataria , para [0046], Validation circuit 122 is further configured to, using the decoded debug permissions, initiate an active debug session. During an active debug session, validation circuit 122 enables one or more of debug features 230 for access by debug system 110. In response to the enabling, debug system 110 may send debug requests to debug circuit 120 via validation circuit 122. The enabled ones of debug features 230 allow access to one or more of functional circuits 250. Chbani , para [0011], the first processing unit is configured: to read from the host register an authentication request from the external device; to authenticate the external device; and to set at least one of the one or more processing unit access ports to an open state, thereby causing the indication of the state of the one or more processing unit access ports to be updated in the status register. Para [0012], According to one embodiment, the first processing unit is configured to authenticate the external device by: storing an authentication challenge or password request to the device register; reading an authentication certificate or password from the host register; and verifying the certificate or password. Para [0047-0049], the authentication interface circuit. Para [0050], FIG. 3, the status register 302 stores, for each access port, a first bit APOP to AP15P indicating whether the corresponding access port AP0 to AP15 is present, and a second bit AP0S to AP15S indicating the current status of the corresponding access port AP0 to AP15, in other words whether it is open or closed. Para [0051], Upon power-up of the electronic device 100, the contents of the status register 302 is for example loaded, by a state machine (not illustrated), from secure storage in a non-volatile memory, such as the memory 104 of FIG. 1. For example, by default, upon power-up, the access ports AP1 to APn are all set to be closed, whereas the access port AP0 is set to be open. The open or closed status to each of the access ports AP0 to. Fig. 4 and para [0069-0070], In an operation 407 (MASTER CPU VERIFIES CERTIFICATE+UNLOCKS APs), the master processing unit CPU1 is for example configured to verify the certificate, and if validated, to unlock, and thus set to open status, one or more of the processing unit access ports AP1 to APn based on the credentials indicated by the certificate. In other words, debug is opened for all or for selected processing unit access ports AP1 to APN. For example, this is done by writing, by the master processing unit CPU1, to the one or more system control registers 201 of FIG. 2. For example, each processing device access port has its own dedicated control bits in the system control registers 201). Claim 19 is rejected for the reasons set forth hereinabove for claim 16, Kataria and Chbani teach the method of claim 16, further comprising clearing one or more bits indicating the debug authentication indication in response to a failed performance of the authentication procedure ( Kataria , para [0045], A failure to validate any one these values may result in validation circuit 122 denying certificate 135 and refusing access to debug features 230. Chbani , para [0011], the first processing unit is configured: to read from the host register an authentication request from the external device; to authenticate the external device; and to set at least one of the one or more processing unit access ports to an open state, thereby causing the indication of the state of the one or more processing unit access ports to be updated in the status register. Para [0012], According to one embodiment, the first processing unit is configured to authenticate the external device by: storing an authentication challenge or password request to the device register; reading an authentication certificate or password from the host register; and verifying the certificate or password. Para [0047-0049], the authentication interface circuit. Para [0050], FIG. 3, the status register 302 stores, for each access port, a first bit APOP to AP15P indicating whether the corresponding access port AP0 to AP15 is present, and a second bit AP0S to AP15S indicating the current status of the corresponding access port AP0 to AP15, in other words whether it is open or closed. Para [0051], Upon power-up of the electronic device 100, the contents of the status register 302 is for example loaded, by a state machine (not illustrated), from secure storage in a non-volatile memory, such as the memory 104 of FIG. 1. For example, by default, upon power-up, the access ports AP1 to APn are all set to be closed, whereas the access port AP0 is set to be open. The open or closed status to each of the access ports AP0 to. Fig. 4 and para [0069-0070], In an operation 407 (MASTER CPU VERIFIES CERTIFICATE+UNLOCKS APs), the master processing unit CPU1 is for example configured to verify the certificate, and if validated, to unlock, and thus set to open status, one or more of the processing unit access ports AP1 to APn based on the credentials indicated by the certificate. In other words, debug is opened for all or for selected processing unit access ports AP1 to APN. For example, this is done by writing, by the master processing unit CPU1, to the one or more system control registers 201 of FIG. 2. For example, each processing device access port has its own dedicated control bits in the system control registers 201). Claim 20 is rejected for the reasons set forth hereinabove for claim 16, Kataria and Chbani teach the method of claim 16, further comprising disallowing a debug session in response to a failed performance of the authentication procedure ( Kataria , para [0045], A failure to validate any one these values may result in validation circuit 122 denying certificate 135 and refusing access to debug features 230 Chbani , para [0011], the first processing unit is configured: to read from the host register an authentication request from the external device; to authenticate the external device; and to set at least one of the one or more processing unit access ports to an open state, thereby causing the indication of the state of the one or more processing unit access ports to be updated in the status register. Para [0012], According to one embodiment, the first processing unit is configured to authenticate the external device by: storing an authentication challenge or password request to the device register; reading an authentication certificate or password from the host register; and verifying the certificate or password. Para [0047-0049], the authentication interface circuit. Para [0050], FIG. 3, the status register 302 stores, for each access port, a first bit APOP to AP15P indicating whether the corresponding access port AP0 to AP15 is present, and a second bit AP0S to AP15S indicating the current status of the corresponding access port AP0 to AP15, in other words whether it is open or closed. Para [0051], Upon power-up of the electronic device 100, the contents of the status register 302 is for example loaded, by a state machine (not illustrated), from secure storage in a non-volatile memory, such as the memory 104 of FIG. 1. For example, by default, upon power-up, the access ports AP1 to APn are all set to be closed, whereas the access port AP0 is set to be open. The open or closed status to each of the access ports AP0 to. Fig. 4 and para [0069-0070], In an operation 407 (MASTER CPU VERIFIES CERTIFICATE+UNLOCKS APs), the master processing unit CPU1 is for example configured to verify the certificate, and if validated, to unlock, and thus set to open status, one or more of the processing unit access ports AP1 to APn based on the credentials indicated by the certificate. In other words, debug is opened for all or for selected processing unit access ports AP1 to APN. For example, this is done by writing, by the master processing unit CPU1, to the one or more system control registers 201 of FIG. 2. For example, each processing device access port has its own dedicated control bits in the system control registers 201). Conclusion 07-39 AIA 8. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY KHUONG THANH NGUYEN whose telephone number is (571)270-7139. The examiner can normally be reached Monday - Friday 0800-1630. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lewis Bullock can be reached at 5712723759. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DUY KHUONG T NGUYEN/ Primary Examiner, Art Unit 2199 Application/Control Number: 18/621,032 Page 2 Art Unit: 2199 Application/Control Number: 18/621,032 Page 3 Art Unit: 2199 Application/Control Number: 18/621,032 Page 4 Art Unit: 2199 Application/Control Number: 18/621,032 Page 5 Art Unit: 2199 Application/Control Number: 18/621,032 Page 6 Art Unit: 2199 Application/Control Number: 18/621,032 Page 7 Art Unit: 2199 Application/Control Number: 18/621,032 Page 8 Art Unit: 2199 Application/Control Number: 18/621,032 Page 9 Art Unit: 2199 Application/Control Number: 18/621,032 Page 10 Art Unit: 2199 Application/Control Number: 18/621,032 Page 11 Art Unit: 2199 Application/Control Number: 18/621,032 Page 12 Art Unit: 2199 Application/Control Number: 18/621,032 Page 13 Art Unit: 2199 Application/Control Number: 18/621,032 Page 14 Art Unit: 2199 Application/Control Number: 18/621,032 Page 15 Art Unit: 2199 Application/Control Number: 18/621,032 Page 16 Art Unit: 2199 Application/Control Number: 18/621,032 Page 17 Art Unit: 2199 Application/Control Number: 18/621,032 Page 18 Art Unit: 2199 Application/Control Number: 18/621,032 Page 19 Art Unit: 2199 Application/Control Number: 18/621,032 Page 20 Art Unit: 2199 Application/Control Number: 18/621,032 Page 21 Art Unit: 2199 Application/Control Number: 18/621,032 Page 22 Art Unit: 2199 Application/Control Number: 18/621,032 Page 23 Art Unit: 2199 Application/Control Number: 18/621,032 Page 24 Art Unit: 2199 Application/Control Number: 18/621,032 Page 25 Art Unit: 2199 Application/Control Number: 18/621,032 Page 26 Art Unit: 2199 Application/Control Number: 18/621,032 Page 27 Art Unit: 2199 Application/Control Number: 18/621,032 Page 28 Art Unit: 2199 Application/Control Number: 18/621,032 Page 29 Art Unit: 2199 Application/Control Number: 18/621,032 Page 30 Art Unit: 2199 Application/Control Number: 18/621,032 Page 31 Art Unit: 2199 Application/Control Number: 18/621,032 Page 32 Art Unit: 2199 Application/Control Number: 18/621,032 Page 33 Art Unit: 2199 Application/Control Number: 18/621,032 Page 34 Art Unit: 2199 Application/Control Number: 18/621,032 Page 35 Art Unit: 2199 Application/Control Number: 18/621,032 Page 36 Art Unit: 2199 Application/Control Number: 18/621,032 Page 37 Art Unit: 2199 Application/Control Number: 18/621,032 Page 38 Art Unit: 2199
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