Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of the device invention in the reply filed on July 13, 2026 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1,21,24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al (PG Pub 2016/0190339 A1) and Wei et al (PG Pub 2022/0139911 A1).
Regarding claim 1, Xie teaches a semiconductor structure comprising: a device layer including a plurality of field effect transistors (fig. 2W), each of the plurality of field effect transistors having a first source-drain region (138, paragraph [0034]), a second source-drain region (138), at least one channel region (108/112/116,paragraph [0026]) coupling the first source-drain region and the second source-drain region and a gate(150, paragraph [0042]) surrounding the at least one channel region; a front side wiring layer (160/161) with wiring coupled to the plurality of field effect transistors at a front side of the device layer.
Xie does not teach a back side power rail at a back side of the device layer; and a back side gate via interconnecting the back side power rail to the gate of at least one of the plurality of field effect transistors.
In the same field of endeavor, Wei teaches a back side power rail (482, paragraph [0128], figs. 3R and 4E) at a back side (paragraph [0128]) of the device layer; and a back side gate via (482) interconnecting the back side power rail to the gate (paragraph [0128]) of at least one of the plurality of field effect transistors, for the benefit of scaling the device (paragraph [0016]).
Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to include a back side power rail at a back side of the device layer; and a back side gate via interconnecting the back side power rail to the gate of at least one of the plurality of field effect transistors, for the benefit of scaling the device.
Regarding claim 21, Xie in view of Wei (see claim 1) teaches an integrated circuit comprising: a device layer including a plurality of field effect transistors, each of the plurality of field effect transistors having a first source-drain region, a second source-drain region, at least one channel region coupling the first source-drain region and the second source-drain region, and a gate (150 of Xie, paragraph [0042]) surrounding the at least one channel region; a front side wiring layer with wiring coupled to the plurality of field effect transistors at a front side of the device layer; and a back side gate via interconnecting the back side power rail to the gate of at least one of the plurality of field effect transistors.
Xie does not teach the back side power rail is coupled to one of a voltage supply terminal and a ground terminal.
It would have been obvious to the skilled in the art before the effective filing date of the invention to couple the back side power rail is to one of a voltage supply terminal and a ground terminal, for the benefit of providing the necessary potential to the gate to turn on/off the transistor.
Regarding claim 24, Xie in view of Wei teaches (see claim 1) a semiconductor device comprising: a device layer including a plurality of field effect transistors, each of the plurality of field effect transistors having a first source-drain region, a second source-drain region, at least one channel region coupling the first source-drain region and the second source-drain region, and a gate surrounding the at least one channel region; a front side wiring layer with wiring coupled to the plurality of field effect transistors at a front side of the device layer; a back side inter-layer dielectric layer (380, figs. 3R and 4E of Wei) on a back side of the device layer; a back side power rail on the back side inter-layer dielectric layer; and a back side gate via (483 of Wei) extending through the back side inter-layer dielectric layer and interconnecting the back side power rail to the gate of at least one of the plurality of field effect transistors.
Claim(s) 1 and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al (PG Pub 2016/0190339 A1) and Wei et al (PG Pub 2023/0067354 A1).
Regarding claim 1, Xie teaches a semiconductor structure comprising: a device layer including a plurality of field effect transistors (fig. 2W), each of the plurality of field effect transistors having a first source-drain region (138, paragraph [0034]), a second source-drain region (138), at least one channel region (108/112/116,paragraph [0026]) coupling the first source-drain region and the second source-drain region and a gate(150, paragraph [0042]) surrounding the at least one channel region; a front side wiring layer (160/161) with wiring coupled to the plurality of field effect transistors at a front side of the device layer.
Xie does not teach a back side power rail at a back side of the device layer; and a back side gate via interconnecting the back side power rail to the gate of at least one of the plurality of field effect transistors.
In the same field of endeavor, Wei teaches a back side power rail (118a/118b, paragraph [0025], fig. 1A) at a back side (paragraph [0018]) of the device layer; and a back side gate via (122a/122b) interconnecting the back side power rail to the gate of at least one of the plurality of field effect transistors, for the benefit of providing electrical isolation between adjacent devices (paragraph [0010]).
Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to include a back side power rail at a back side of the device layer; and a back side gate via interconnecting the back side power rail to the gate of at least one of the plurality of field effect transistors, for the benefit of providing electrical isolation between adjacent devices.
Regarding claim 4, Wei teaches the semiconductor structure of claim1, further comprising, for the at least one of the plurality of field effect transistors, bottom dielectric isolation (106, fig. 1A, paragraph [0022]) beneath the at least one channel region (112), wherein the gate includes gate footings (120 below 112) extending downward on either side of the at least one channel region, and wherein the back side gate via interconnects the back side power rail to the gate using one of the gate footings (fig. 1A).
Claim(s) 2,3,22,23,25,26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al (PG Pub 2016/0190339 A1) and Wei et al (PG Pub 2022/0139911 A1) as applied to claims 1,21,24 above, and further in view of Wei (PG Pub 2023/0067354 A1, hereafter Wei354).
Regarding claim 2, the previous combination remains as applied in claim 1.
The previous combination does not teach a voltage supply terminal, and wherein the back side power rail is coupled to the voltage supply terminal.
It would have been obvious to the skilled in the art before the effective filing date of the invention to provide a voltage supply terminal and to couple the back side power rail is to the voltage supply terminal, for the benefit of providing the necessary potential to the gate to turn on/off the transistor.
The previous combination does not teach wherein the at least one of the plurality of field effect transistors is a p-type field effect transistor.
In the same field of endeavor, Wei354 teaches wherein the at least one of the plurality of field effect transistors is a p-type field effect transistor (paragraph [0011]), for the benefit or providing isolation between adjacent devices (paragraph [0010]).
Regarding claim 3, the previous combination remains as applied in claim 1.
The previous combination does not teach a ground terminal, and wherein the back side power rail is coupled to the ground terminal.
It would have been obvious to the skilled in the art before the effective filing date of the invention to provide a ground terminal and to couple the back side power rail is to the ground terminal, for the benefit of providing the necessary potential to the gate to turn on/off the transistor.
The previous combination does not teach wherein the at least one of the plurality of field effect transistors is a n-type field effect transistor.
In the same field of endeavor, Wei354 teaches wherein the at least one of the plurality of field effect transistors is an n-type field effect transistor (paragraph [0011]), for the benefit or providing isolation between adjacent devices (paragraph [0010]).
Regarding claims 22 and 25, Wei in view of Wei354 teaches the integrated circuit of claims 21 and 24, wherein the at least one of the plurality of field effect transistors is a p-type field effect transistor (paragraph [0011] of Wei354), and wherein the back side power rail is coupled to the voltage supply terminal (VDD, paragraph [0011] of Wei 354).
Regarding claims 23 and 26, Wei in view of Wei354 teaches the integrated circuit of claims 21 and 24, wherein the at least one of the plurality of field effect transistors is an n-type field effect transistor (paragraph [0011] of Wei354), and wherein the back side power rail is coupled to the ground terminal (VSS, paragraph [0011] of Wei 354).
Claim(s) 8 and 10-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al (PG Pub 2016/0190339 A1) and Wei et al (PG Pub 2022/0139911 A1) as applied to claim 1 above, and further in view of Yu et al (PG Pub 2016/0049500 A1).
Regarding claim 8, the previous combination remains as applied in claim 1.
The previous combination does not teach the back side gate via tapers from a wider dimension adjacent to the back side power rail to a narrower dimension adjacent to the gate of the at least one of the plurality of field effect transistors.
In the same field of endeavor, Yu teaches a tapered via (33, fig. 28) facilitates filling of conductive material into the via (paragraph [0077]).
It would have been obvious to the skilled in the art before the effective filing date of the invention to make the back side gate via taper from a wider dimension adjacent to the back side power rail to a narrower dimension adjacent to the gate of the at least one of the plurality of field effect transistors, for the benefit of facilitating filling of conductive material into the via.
Regarding claim 10, Xie teaches the semiconductor structure of claim8, wherein the gate of each of the plurality of field effect transistors comprises a high-K metal gate structure including a high-K dielectric and a gate metal (paragraph [0006]).
Regarding claim 11, Xie teaches the semiconductor structure of claim 10, wherein the high-K dielectric is selected from the group consisting of hafnium silicon oxide, zirconium silicon oxide, hafnium oxide (paragraph [0038]), or zirconium oxide.
Regarding claim 12, Xie teaches the semiconductor structure of claim11, wherein the gate metal is a work-function-tunable material (paragraph [0153]).
Regarding claim 13, Xie teaches the semiconductor structure of claim 12, wherein the work-function-tunable material is selected from the group consisting of titanium nitride (paragraph [0042]), titanium aluminum nitride, titanium silicon nitride, tantalum nitride, tantalum aluminum nitride, or tantalum silicon nitride.
Regarding claim 14, Xie teaches the semiconductor structure of claim13, wherein the back side gate via includes a material selected from the group consisting of tungsten (155, fig. 2Q, paragraph [0042]) and ruthenium.
Allowable Subject Matter
Claims 5-7 and 9 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Prior art does not teach.
“the gate footings extend downward beyond respective lowest extensions of the first source-drain region and the second source-drain region of the at least one of the plurality of field effect transistors” (claim 5);
“the back side power rail tapers from a wider dimension towards a back side of the semiconductor structure to a narrower dimension adjacent to the back side gate via” (claim 9).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FEIFEI YEUNG LOPEZ whose telephone number is (571)270-1882. The examiner can normally be reached M-F: 8am to 4pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571 270 7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/FEIFEI YEUNG LOPEZ/Primary Examiner, Art Unit 2899
Prosecution Insights